| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/drivers/ |
| D | fsl_clock.c | 18 #define CGC_SOSCDIV_DIV1_VAL(reg) \ argument
21 #define CGC_SOSCDIV_DIV2_VAL(reg) \ argument
24 #define CGC_SOSCDIV_DIV3_VAL(reg) \ argument
27 #define CGC_FRODIV_DIV1_VAL(reg) \ argument
30 #define CGC_FRODIV_DIV2_VAL(reg) \ argument
33 #define CGC_FRODIV_DIV3_VAL(reg) \ argument
293 uint32_t reg; in CLOCK_SetIpSrc() local
506 uint32_t reg = PCC_REG(name); in CLOCK_SetIpSrcDiv() local
1356 static uint32_t CLOCK_GetPccFreq(uint32_t pccInst, clock_ip_name_t name, uint32_t reg) in CLOCK_GetPccFreq()
1508 uint32_t reg; in CLOCK_GetIpFreq() local
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/drivers/ |
| D | fsl_clock.c | 18 #define CGC_SOSCDIV_DIV1_VAL(reg) \ argument
21 #define CGC_SOSCDIV_DIV2_VAL(reg) \ argument
24 #define CGC_SOSCDIV_DIV3_VAL(reg) \ argument
27 #define CGC_FRODIV_DIV1_VAL(reg) \ argument
30 #define CGC_FRODIV_DIV2_VAL(reg) \ argument
33 #define CGC_FRODIV_DIV3_VAL(reg) \ argument
293 uint32_t reg; in CLOCK_SetIpSrc() local
506 uint32_t reg = PCC_REG(name); in CLOCK_SetIpSrcDiv() local
1356 static uint32_t CLOCK_GetPccFreq(uint32_t pccInst, clock_ip_name_t name, uint32_t reg) in CLOCK_GetPccFreq()
1508 uint32_t reg; in CLOCK_GetIpFreq() local
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/drivers/ |
| D | fsl_clock.c | 18 #define CGC_SOSCDIV_DIV1_VAL(reg) \ argument
21 #define CGC_SOSCDIV_DIV2_VAL(reg) \ argument
24 #define CGC_SOSCDIV_DIV3_VAL(reg) \ argument
27 #define CGC_FRODIV_DIV1_VAL(reg) \ argument
30 #define CGC_FRODIV_DIV2_VAL(reg) \ argument
33 #define CGC_FRODIV_DIV3_VAL(reg) \ argument
293 uint32_t reg; in CLOCK_SetIpSrc() local
506 uint32_t reg = PCC_REG(name); in CLOCK_SetIpSrcDiv() local
1356 static uint32_t CLOCK_GetPccFreq(uint32_t pccInst, clock_ip_name_t name, uint32_t reg) in CLOCK_GetPccFreq()
1508 uint32_t reg; in CLOCK_GetIpFreq() local
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/drivers/ |
| D | fsl_clock.c | 18 #define CGC_SOSCDIV_DIV1_VAL(reg) \ argument
21 #define CGC_SOSCDIV_DIV2_VAL(reg) \ argument
24 #define CGC_SOSCDIV_DIV3_VAL(reg) \ argument
27 #define CGC_FRODIV_DIV1_VAL(reg) \ argument
30 #define CGC_FRODIV_DIV2_VAL(reg) \ argument
33 #define CGC_FRODIV_DIV3_VAL(reg) \ argument
293 uint32_t reg; in CLOCK_SetIpSrc() local
506 uint32_t reg = PCC_REG(name); in CLOCK_SetIpSrcDiv() local
1356 static uint32_t CLOCK_GetPccFreq(uint32_t pccInst, clock_ip_name_t name, uint32_t reg) in CLOCK_GetPccFreq()
1508 uint32_t reg; in CLOCK_GetIpFreq() local
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/drivers/ |
| D | fsl_clock.c | 18 #define CGC_SOSCDIV_DIV1_VAL(reg) \ argument
21 #define CGC_SOSCDIV_DIV2_VAL(reg) \ argument
24 #define CGC_SOSCDIV_DIV3_VAL(reg) \ argument
27 #define CGC_FRODIV_DIV1_VAL(reg) \ argument
30 #define CGC_FRODIV_DIV2_VAL(reg) \ argument
33 #define CGC_FRODIV_DIV3_VAL(reg) \ argument
293 uint32_t reg; in CLOCK_SetIpSrc() local
506 uint32_t reg = PCC_REG(name); in CLOCK_SetIpSrcDiv() local
1356 static uint32_t CLOCK_GetPccFreq(uint32_t pccInst, clock_ip_name_t name, uint32_t reg) in CLOCK_GetPccFreq()
1508 uint32_t reg; in CLOCK_GetIpFreq() local
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/spc/ |
| D | fsl_spc.c | 66 uint32_t reg; in SPC_GetPeriphIOIsolationStatus() local
84 uint32_t reg; in SPC_SetLowPowerRequestConfig() local
148 uint32_t reg; in SPC_SetActiveModeBandgapModeConfig() local
241 uint32_t reg; in SPC_SetLowPowerModeBandgapmodeConfig() local
295 uint32_t reg = 0UL; in SPC_SetCoreVoltageDetectConfig() local
461 uint32_t reg = 0UL; in SPC_SetSystemVoltageDetectConfig() local
606 uint32_t reg; in SPC_SetIOVDDLowVoltageLevel() local
631 uint32_t reg = 0UL; in SPC_SetIOVoltageDetectConfig() local
776 uint32_t reg = 0UL; in SPC_SetExternalVoltageDomainsConfig() local
942 uint32_t reg; in SPC_SetActiveModeSystemLDORegulatorConfig() local
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/mcx_spc/ |
| D | fsl_spc.c | 68 uint32_t reg; in SPC_GetPeriphIOIsolationStatus() local
86 uint32_t reg; in SPC_SetLowPowerRequestConfig() local
115 uint32_t reg; in SPC_ConfigVddCoreGlitchDetector() local
140 uint32_t reg = 0UL; in SPC_SetSRAMOperateVoltage() local
179 uint32_t reg; in SPC_SetActiveModeBandgapModeConfig() local
255 uint32_t reg; in SPC_SetLowPowerModeBandgapmodeConfig() local
321 uint32_t reg = 0UL; in SPC_SetCoreVoltageDetectConfig() local
494 uint32_t reg = 0UL; in SPC_SetSystemVoltageDetectConfig() local
639 uint32_t reg; in SPC_SetIOVDDLowVoltageLevel() local
664 uint32_t reg = 0UL; in SPC_SetIOVoltageDetectConfig() local
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/msmc/ |
| D | fsl_msmc.c | 24 uint32_t reg; in SMC_SetPowerModeRun() local
43 uint32_t reg; in SMC_SetPowerModeHsrun() local
81 uint32_t reg; in SMC_SetPowerModeStop() local
123 uint32_t reg; in SMC_SetPowerModeVlpr() local
160 uint32_t reg; in SMC_SetPowerModeVlps() local
203 uint32_t reg; in SMC_SetPowerModeLls() local
249 uint32_t reg; in SMC_SetPowerModeVlls0() local
279 uint32_t reg; in SMC_SetPowerModeVlls2() local
309 uint32_t reg; in SMC_SetPowerModeVlls() local
357 uint32_t reg; in SMC_ConfigureResetPinFilter() local
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/qtmr_1/ |
| D | fsl_qtmr.c | 175 uint16_t reg; in QTMR_SetupPwm() local
283 uint16_t reg; in QTMR_SetupInputCapture() local
320 uint16_t reg; in QTMR_EnableInterrupts() local
366 uint16_t reg; in QTMR_DisableInterrupts() local
412 uint16_t reg; in QTMR_GetEnabledInterrupts() local
458 uint16_t reg; in QTMR_GetStatus() local
502 uint16_t reg; in QTMR_ClearStatusFlags() local
609 uint16_t reg; in QTMR_EnableDma() local
642 uint16_t reg; in QTMR_DisableDma() local
674 uint16_t reg = base->CHANNEL[channel].SCTRL; in QTMR_SetPwmOutputToIdle() local
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/ftm/ |
| D | fsl_ftm.c | 96 uint32_t reg = 0, syncReg = 0; in FTM_SetPwmSync() local
164 uint32_t reg = 0; in FTM_SetReloadPoints() local
245 uint32_t reg; in FTM_Init() local
438 uint32_t mod, reg; in FTM_SetupPwm() local
671 uint32_t reg = base->CONTROLS[chnlNumber].CnSC; in FTM_UpdateChnlEdgeLevelSelect() local
706 uint32_t reg; in FTM_SetupPwmMode() local
848 uint32_t reg; in FTM_SetupInputCapture() local
897 uint32_t reg; in FTM_SetupOutputCompare() local
946 uint32_t reg; in FTM_SetupDualEdgeCapture() local
998 uint32_t reg; in FTM_SetupQuadDecode() local
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/smc/ |
| D | fsl_smc.c | 92 uint32_t reg = base->PARAM; in SMC_GetParam() local
154 smc_reg_t reg; in SMC_SetPowerModeRun() local
174 smc_reg_t reg; in SMC_SetPowerModeHsrun() local
212 smc_reg_t reg; in SMC_SetPowerModeStop() local
259 smc_reg_t reg; in SMC_SetPowerModeVlpr() local
310 smc_reg_t reg; in SMC_SetPowerModeVlps() local
351 smc_reg_t reg; in SMC_SetPowerModeLls() local
407 smc_reg_t reg; in SMC_SetPowerModeVlls() local
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| /hal_nxp-latest/mcux/mcux-sdk/components/video/camera/device/max9286/ |
| D | fsl_max9286.c | 39 #define MAX9286_Write(handle, reg, value) \ argument
43 #define MAX9286_Read(handle, reg, value) \ argument
59 uint16_t reg; member
402 static status_t MAX9271_Write(camera_device_handle_t *handle, uint8_t i2cAddr, uint32_t reg, uint8_… in MAX9271_Write()
421 static status_t OV10635_Write(camera_device_handle_t *handle, uint8_t i2cAddr, uint32_t reg, uint8_… in OV10635_Write()
440 static status_t OV10635_Read(camera_device_handle_t *handle, uint8_t i2cAddr, uint32_t reg, uint8_t… in OV10635_Read()
499 uint8_t reg = 0; in MAX9286_ReorderVC() local
528 uint8_t reg = 0U; in OV10635_Init() local
746 uint8_t reg = 0; in MAX9286_InitExt() local
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/edma_rev2/ |
| D | fsl_edma_rev2.c | 22 #define EDMA_REG_ACCESS(reg)\ argument
25 #define EDMA_REG_INDEX(reg) ((reg) & EDMA_REGISTER_INDEX_MASK) argument
52 static uint32_t EDMA_GetChannelRegBase(edma_config_t *cfg, int channel, uint32_t reg) in EDMA_GetChannelRegBase()
77 void EDMA_ChannelRegWrite(edma_config_t *cfg, int channel, uint32_t reg, uint32_t value) in EDMA_ChannelRegWrite()
84 uint32_t EDMA_ChannelRegRead(edma_config_t *cfg, int channel, uint32_t reg) in EDMA_ChannelRegRead()
91 void EDMA_ChannelRegUpdate(edma_config_t *cfg, int channel, uint32_t reg, in EDMA_ChannelRegUpdate()
105 void EDMA_MPRegWrite(edma_config_t *cfg, uint32_t reg, uint32_t value) in EDMA_MPRegWrite()
112 uint32_t EDMA_MPRegRead(edma_config_t *cfg, uint32_t reg) in EDMA_MPRegRead()
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/asmc/ |
| D | fsl_asmc.c | 24 uint32_t reg; in ASMC_SetPowerModeRun() local
44 uint32_t reg; in ASMC_SetPowerModeHsrun() local
82 uint32_t reg; in ASMC_SetPowerModeStop() local
116 uint32_t reg; in ASMC_SetPowerModeVlpr() local
154 uint32_t reg; in ASMC_SetPowerModeVlps() local
182 uint32_t reg; in ASMC_SetPowerModeLls() local
210 uint32_t reg; in ASMC_SetPowerModeVlls() local
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/cmc/ |
| D | fsl_cmc.c | 49 uint32_t reg; in CMC_SetClockMode() local
73 uint32_t reg; in CMC_SetPowerModeProtection() local
96 uint32_t reg = base->RPC; in CMC_ConfigResetPin() local
129 uint32_t reg = base->SRAMDIS[0]; in CMC_PowerOffSRAMAllMode() local
147 uint32_t reg = base->SRAMRET[0]; in CMC_PowerOffSRAMLowPowerOnly() local
169 uint32_t reg; in CMC_ConfigSRAMVoltage() local
202 uint32_t reg = 0UL; in CMC_ConfigFlashMode() local
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/mcx_cmc/ |
| D | fsl_cmc.c | 42 uint32_t reg; in CMC_SetClockMode() local
66 uint32_t reg; in CMC_SetPowerModeProtection() local
89 uint32_t reg = base->RPC; in CMC_ConfigResetPin() local
123 uint32_t reg = base->SRAMDIS[0]; in CMC_PowerOffSRAMAllMode() local
142 uint32_t reg = base->SRAMRET[0]; in CMC_PowerOffSRAMLowPowerOnly() local
165 uint32_t reg = 0UL; in CMC_ConfigFlashMode() local
190 uint32_t reg = 0UL; in CMC_ConfigFlashMode() local
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/drivers/ |
| D | fsl_clock.c | 41 #define PCC_PCS_VAL(reg) (((reg)&PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT) argument
42 #define PCC_FRAC_VAL(reg) (((reg)&PCC_CLKCFG_FRAC_MASK) >> PCC_CLKCFG_FRAC_SHIFT) argument
43 #define PCC_PCD_VAL(reg) (((reg)&PCC_CLKCFG_PCD_MASK) >> PCC_CLKCFG_PCD_SHIFT) argument
191 uint32_t reg = (*(volatile uint32_t *)((uint32_t)name)); in CLOCK_GetIpFreq() local
369 uint32_t reg = SCG->SOSCCSR; in CLOCK_DeinitSysOsc() local
509 uint32_t reg = SCG->SIRCCSR; in CLOCK_DeinitSirc() local
670 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc() local
840 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll() local
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/drivers/ |
| D | fsl_clock.c | 42 #define PCC_PCS_VAL(reg) (((reg)&PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT) argument
43 #define PCC_FRAC_VAL(reg) (((reg)&PCC_CLKCFG_FRAC_MASK) >> PCC_CLKCFG_FRAC_SHIFT) argument
44 #define PCC_PCD_VAL(reg) (((reg)&PCC_CLKCFG_PCD_MASK) >> PCC_CLKCFG_PCD_SHIFT) argument
192 uint32_t reg = (*(volatile uint32_t *)((uint32_t)name)); in CLOCK_GetIpFreq() local
370 uint32_t reg = SCG->SOSCCSR; in CLOCK_DeinitSysOsc() local
510 uint32_t reg = SCG->SIRCCSR; in CLOCK_DeinitSirc() local
666 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc() local
836 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll() local
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/drivers/ |
| D | fsl_clock.c | 41 #define PCC_PCS_VAL(reg) (((reg)&PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT) argument
42 #define PCC_FRAC_VAL(reg) (((reg)&PCC_CLKCFG_FRAC_MASK) >> PCC_CLKCFG_FRAC_SHIFT) argument
43 #define PCC_PCD_VAL(reg) (((reg)&PCC_CLKCFG_PCD_MASK) >> PCC_CLKCFG_PCD_SHIFT) argument
191 uint32_t reg = (*(volatile uint32_t *)((uint32_t)name)); in CLOCK_GetIpFreq() local
369 uint32_t reg = SCG->SOSCCSR; in CLOCK_DeinitSysOsc() local
509 uint32_t reg = SCG->SIRCCSR; in CLOCK_DeinitSirc() local
670 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc() local
840 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll() local
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/drivers/ |
| D | fsl_clock.c | 42 #define PCC_PCS_VAL(reg) (((reg)&PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT) argument
43 #define PCC_FRAC_VAL(reg) (((reg)&PCC_CLKCFG_FRAC_MASK) >> PCC_CLKCFG_FRAC_SHIFT) argument
44 #define PCC_PCD_VAL(reg) (((reg)&PCC_CLKCFG_PCD_MASK) >> PCC_CLKCFG_PCD_SHIFT) argument
192 uint32_t reg = (*(volatile uint32_t *)((uint32_t)name)); in CLOCK_GetIpFreq() local
370 uint32_t reg = SCG->SOSCCSR; in CLOCK_DeinitSysOsc() local
510 uint32_t reg = SCG->SIRCCSR; in CLOCK_DeinitSirc() local
666 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc() local
836 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll() local
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/drivers/ |
| D | fsl_clock.c | 41 #define PCC_PCS_VAL(reg) (((reg)&PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT) argument
42 #define PCC_FRAC_VAL(reg) (((reg)&PCC_CLKCFG_FRAC_MASK) >> PCC_CLKCFG_FRAC_SHIFT) argument
43 #define PCC_PCD_VAL(reg) (((reg)&PCC_CLKCFG_PCD_MASK) >> PCC_CLKCFG_PCD_SHIFT) argument
191 uint32_t reg = (*(volatile uint32_t *)((uint32_t)name)); in CLOCK_GetIpFreq() local
369 uint32_t reg = SCG->SOSCCSR; in CLOCK_DeinitSysOsc() local
509 uint32_t reg = SCG->SIRCCSR; in CLOCK_DeinitSirc() local
670 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc() local
840 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll() local
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/qtmr_2/ |
| D | fsl_qtmr.c | 163 uint16_t reg; in QTMR_SetupPwm() local
237 uint16_t reg; in QTMR_SetupInputCapture() local
273 uint16_t reg; in QTMR_EnableInterrupts() local
316 uint16_t reg; in QTMR_DisableInterrupts() local
361 uint16_t reg; in QTMR_GetEnabledInterrupts() local
406 uint16_t reg; in QTMR_GetStatus() local
449 uint16_t reg; in QTMR_ClearStatusFlags() local
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/pwm/ |
| D | fsl_pwm.c | 270 uint16_t reg; in PWM_Init() local
828 uint16_t reg = 0; in PWM_SetupInputCapture() local
938 uint16_t reg; in PWM_SetupFaults() local
1055 uint16_t reg; in PWM_SetupForceSignal() local
1144 uint16_t reg; in PWM_ClearStatusFlags() local
1273 uint16_t reg = base->SM[subModule].CTRL; in PWM_SetClockMode() local
1304 uint16_t reg = base->SM[subModule].CTRL2; in PWM_SetPwmForceOutputToZero() local
1359 uint16_t reg = base->SM[subModule].CTRL2; in PWM_SetChannelOutput() local
1439 uint16_t reg = base->SM[subModule].CTRL2; in PWM_SetPhaseDelay() local
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/drivers/ |
| D | fsl_clock.c | 45 #define PCC_PCS_VAL(reg) (((reg)&PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT) argument
46 #define PCC_FRAC_VAL(reg) (((reg)&PCC_CLKCFG_FRAC_MASK) >> PCC_CLKCFG_FRAC_SHIFT) argument
47 #define PCC_PCD_VAL(reg) (((reg)&PCC_CLKCFG_PCD_MASK) >> PCC_CLKCFG_PCD_SHIFT) argument
195 uint32_t reg = (*(volatile uint32_t *)((uint32_t)name)); in CLOCK_GetIpFreq() local
373 uint32_t reg = SCG->SOSCCSR; in CLOCK_DeinitSysOsc() local
513 uint32_t reg = SCG->SIRCCSR; in CLOCK_DeinitSirc() local
669 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc() local
842 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll() local
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/drivers/ |
| D | fsl_clock.c | 103 #define PCC_PCS_VAL(reg) (((reg)&PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT) argument
104 #define PCC_FRAC_VAL(reg) (((reg)&PCC_CLKCFG_FRAC_MASK) >> PCC_CLKCFG_FRAC_SHIFT) argument
105 #define PCC_PCD_VAL(reg) (((reg)&PCC_CLKCFG_PCD_MASK) >> PCC_CLKCFG_PCD_SHIFT) argument
402 uint32_t reg = (*(volatile uint32_t *)(uint32_t)name); in CLOCK_GetIpFreq() local
635 uint32_t reg = SCG->SOSCCSR; in CLOCK_DeinitSysOsc() local
783 uint32_t reg = SCG->SIRCCSR; in CLOCK_DeinitSirc() local
951 uint32_t reg = SCG->FIRCCSR; in CLOCK_DeinitFirc() local
1156 uint32_t reg = SCG->APLLCSR; in CLOCK_DeinitAuxPll() local
1457 uint32_t reg = SCG->SPLLCSR; in CLOCK_DeinitSysPll() local
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