| /hal_infineon-3.5.0/mtb-pdl-cat1/drivers/third_party/ethernet/src/ |
| D | edd.c | 183 uint32_t reg = CPS_UncachedRead32( in maxHwQs() local
759 uint32_t reg, q; in setRxQBufferSizes() local
819 uint32_t reg; in readDesignConfig() local
2601 uint32_t reg; in emacSetIntrptModerate() local
2616 uint32_t reg; in emacGetIntrptModerate() local
2633 uint32_t reg; in emacSetIfSpeed() local
2663 uint32_t reg; in emacGetIfSpeed() local
2681 uint32_t reg; in emacSetJumboFramesRx() local
2705 uint32_t reg; in emacSetJumboFrameRxMaxLen() local
2735 uint32_t reg; in emacSetUniDirEnable() local
[all …]
|
| D | edd_rx.c | 372 uint32_t reg; in emacReadRxBuf() local
474 uint32_t reg, wd1; in emacGetRxDescStat() local
554 uint32_t reg; in emacRxEnabled() local
565 uint32_t reg; in emacEnableRx() local
577 uint32_t reg; in emacDisableRx() local
792 uint32_t reg; in emacGetRxStatus() local
816 uint32_t reg = 0; in emacClearRxStatus() local
841 uint32_t reg; in emacSetHdrDataSplit() local
880 uint32_t reg, enableField; in emacSetRscEnable() local
907 uint32_t reg; in emacGetRscEnable() local
[all …]
|
| D | edd_tx.c | 577 uint32_t reg; in emacFreeTxDesc() local
902 uint32_t reg; in emacGetTxStatus() local
963 uint32_t reg; in emacSetTxPartialStFwd() local
989 uint32_t reg; in emacGetTxPartialStFwd() local
1023 uint32_t reg; in emacEnableCbs() local
1067 uint32_t reg; in emacDisableCbs() local
1095 uint32_t reg, enabled; in emacGetCbsQSetting() local
1139 uint32_t reg; in emacSetIpgStretch() local
1170 uint32_t reg, stretch; in emacGetIpgStretch() local
|
| /hal_infineon-3.5.0/XMCLib/drivers/src/ |
| D | xmc_ledts.c | 172 uint32_t reg; in XMC_LEDTS_InitTSBasic() local
198 uint32_t reg; in XMC_LEDTS_InitTSAdvanced() local
254 uint32_t reg; in XMC_LEDTS_SetActivePADNo() local
279 uint32_t reg; in XMC_LEDTS_SetLEDLinePattern() local
297 uint32_t reg; in XMC_LEDTS_SetColumnBrightness() local
314 uint32_t reg; in XMC_LEDTS_SetCommonOscillationWindow() local
370 uint32_t reg; in XMC_LEDTS_SetOscillationWindow() local
|
| D | xmc_hrpwm.c | 294 uint32_t reg; in XMC_HRPWM_HRC_ConfigSourceSelect0() local
336 uint32_t reg; in XMC_HRPWM_HRC_ConfigSourceSelect1() local
386 uint32_t reg; in XMC_HRPWM_CSG_Init() local
441 uint32_t reg; in XMC_HRPWM_CSG_SelBlankingInput() local
462 uint32_t reg; in XMC_HRPWM_CSG_SelClampingInput() local
|
| D | xmc_posif.c | 201 uint8_t reg; in XMC_POSIF_QD_Init() local
249 uint32_t reg; in XMC_POSIF_SelectInputSource() local
264 uint32_t reg; in XMC_POSIF_SetInterruptNode() local
|
| D | xmc_bccu.c | 243 uint32_t reg; in XMC_BCCU_ConcurrentConfigTrigger() local
380 uint32_t reg; in XMC_BCCU_EnableChannelTrigger() local
416 uint32_t reg; in XMC_BCCU_CH_ConfigTrigger() local
570 uint32_t reg; in XMC_BCCU_DIM_ConfigDimCurve() local
|
| D | xmc_vadc.c | 198 uint32_t reg; in XMC_VADC_GLOBAL_Init() local
1051 uint32_t reg; in XMC_VADC_GROUP_ScanInit() local
1165 uint32_t reg; in XMC_VADC_GROUP_ScanGetNumChannelsPending() local
1225 uint32_t reg; in XMC_VADC_GLOBAL_BackgroundInit() local
1377 uint32_t reg; in XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending() local
1412 uint32_t reg; in XMC_VADC_GROUP_QueueInit() local
|
| D | xmc_eth_mac.c | 354 __IO uint32_t *reg; in XMC_ETH_MAC_SetAddressPerfectFilter() local
369 __IO uint32_t *reg; in XMC_ETH_MAC_SetAddressPerfectFilterEx() local
535 __IO uint32_t *reg; in XMC_ETH_MAC_SetManagmentClockDivider() local
|
| D | xmc_can.c | 596 uint32_t reg; in XMC_CAN_MO_Config() local
|
| /hal_infineon-3.5.0/core-lib/include/ |
| D | cy_utils.h | 299 #define _CLR_SET_FLD32U(reg, field, value) \ argument
312 #define CY_REG32_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD32U((reg), field, (value))) argument
324 #define _CLR_SET_FLD16U(reg, field, value) \ argument
337 #define CY_REG16_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD16U((reg), field, (value))) argument
349 #define _CLR_SET_FLD8U(reg, field, value) \ argument
362 #define CY_REG8_CLR_SET(reg, field, value) ((reg) = _CLR_SET_FLD8U((reg), field, (value))) argument
|
| /hal_infineon-3.5.0/mtb-pdl-cat1/drivers/source/ |
| D | cy_ephy.c | 178 uint32_t ulConfig, reg, bmsr; in Cy_EPHY_Configure() local
322 uint32_t reg; in Cy_EPHY_GetAutoNegotiationStatus() local
350 uint32_t reg; in Cy_EPHY_getLinkPartnerCapabilities() local
|
| D | cy_ble_clk.c | 694 uint16_t reg = CY_BLE_RF_DCXO_CFG_REG_VALUE; in Cy_BLE_HAL_EcoSetTrim() local
|
| D | cy_prot.c | 829 static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t pcMask, in Prot_ConfigPpuAtt()
|
| D | cy_sysclk.c | 1216 uint32_t reg = _VAL2FLD(SRSS_CLK_TRIM_ECO_CTL_WDTRIM, 7UL) | in Cy_SysClk_EcoConfigure() local
|
| /hal_infineon-3.5.0/bless/ |
| D | cy_ble_clk.c | 694 uint16_t reg = CY_BLE_RF_DCXO_CFG_REG_VALUE; in Cy_BLE_HAL_EcoSetTrim() local
|
| /hal_infineon-3.5.0/mtb-pdl-cat1/drivers/third_party/ethernet/include/ |
| D | edd_int.h | 151 #define CEDI_RegAddr(reg) (&(((struct emac_regs *)(CEDI_PdVar(cfg).regBase))->reg)) argument
|
| /hal_infineon-3.5.0/mtb-pdl-cat1/drivers/include/ |
| D | cy_usbfs_dev_drv_reg.h | 209 #define CY_USBFS_DEV_READ_ODD(reg) ( (uint32_t) (CY_LO8((reg) | ((reg) >> 8U))) ) argument
|
| D | cy_crypto_core_hw.h | 522 #define REG_CRYPTO_VU_RF_DATA(base, reg) ( (volatile uint32_t*)((uint32_t)(base) + cy_cryptoIP->c… argument
|
| /hal_infineon-3.5.0/XMCLib/devices/XMC4500/Include/ |
| D | XMC4500.h | 208 #define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ argument
213 #define WR_REG_SIZE(reg, mask, pos, val, size) { \ argument
222 #define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) argument
225 #define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ argument
229 #define SET_BIT(reg, pos) (reg |= ((uint32_t)1<<pos)) argument
232 #define CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) ) argument
|
| /hal_infineon-3.5.0/XMCLib/devices/XMC4700/Include/ |
| D | XMC4700.h | 208 #define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ argument
213 #define WR_REG_SIZE(reg, mask, pos, val, size) { \ argument
222 #define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) argument
225 #define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ argument
229 #define SET_BIT(reg, pos) (reg |= ((uint32_t)1<<pos)) argument
232 #define CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) ) argument
|
| /hal_infineon-3.5.0/XMCLib/devices/XMC4800/Include/ |
| D | XMC4800.h | 214 #define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ argument
219 #define WR_REG_SIZE(reg, mask, pos, val, size) { \ argument
228 #define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) argument
231 #define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ argument
235 #define SET_BIT(reg, pos) (reg |= ((uint32_t)1<<pos)) argument
238 #define CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) ) argument
|
| /hal_infineon-3.5.0/wifi-host-driver/WiFi_Host_Driver/src/include/ |
| D | whd_wlioctl.h | 3061 uint8_t reg; member
|
