Searched defs:refDiv1 (Results 1 – 15 of 15) sorted by relevance
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | system_MIMX8MQ5_cm4.c | 122 …uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_M… in GetSSCGPllFreq() local
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ6/ |
| D | system_MIMX8MQ6_cm4.c | 122 …uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_M… in GetSSCGPllFreq() local
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/ |
| D | system_MIMX8MQ7_cm4.c | 122 …uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_M… in GetSSCGPllFreq() local
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | system_MIMX8MD6_cm4.c | 122 …uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_M… in GetSSCGPllFreq() local
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | system_MIMX8MD7_cm4.c | 122 …uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_VAL(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIVR1_M… in GetSSCGPllFreq() local
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/drivers/ |
| D | fsl_clock.c | 920 …uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIV… in CLOCK_GetSSCGPllFreq() local
|
| D | fsl_clock.h | 1002 …uint8_t refDiv1; /*!< A 3bit divider to make sure the REF must be within the range 25MHZ~235MHZ ,p… member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ6/drivers/ |
| D | fsl_clock.c | 920 …uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIV… in CLOCK_GetSSCGPllFreq() local
|
| D | fsl_clock.h | 1002 …uint8_t refDiv1; /*!< A 3bit divider to make sure the REF must be within the range 25MHZ~235MHZ ,p… member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/drivers/ |
| D | fsl_clock.c | 920 …uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIV… in CLOCK_GetSSCGPllFreq() local
|
| D | fsl_clock.h | 1002 …uint8_t refDiv1; /*!< A 3bit divider to make sure the REF must be within the range 25MHZ~235MHZ ,p… member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD6/drivers/ |
| D | fsl_clock.c | 920 …uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIV… in CLOCK_GetSSCGPllFreq() local
|
| D | fsl_clock.h | 1002 …uint8_t refDiv1; /*!< A 3bit divider to make sure the REF must be within the range 25MHZ~235MHZ ,p… member
|
| /hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD7/drivers/ |
| D | fsl_clock.c | 920 …uint8_t refDiv1 = (uint8_t)CCM_BIT_FIELD_EXTRACTION(sscgCfg2, CCM_ANALOG_SYS_PLL1_CFG2_PLL_REF_DIV… in CLOCK_GetSSCGPllFreq() local
|
| D | fsl_clock.h | 1002 …uint8_t refDiv1; /*!< A 3bit divider to make sure the REF must be within the range 25MHZ~235MHZ ,p… member
|
