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Searched defs:refDiv (Results 1 – 16 of 16) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/
Dsystem_MIMX8MQ5_cm4.c81 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_… in GetFracPllFreq() local
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ6/
Dsystem_MIMX8MQ6_cm4.c81 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_… in GetFracPllFreq() local
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/
Dsystem_MIMX8MQ7_cm4.c81 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_… in GetFracPllFreq() local
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD6/
Dsystem_MIMX8MD6_cm4.c81 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_… in GetFracPllFreq() local
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD7/
Dsystem_MIMX8MD7_cm4.c81 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_VAL(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFCLK_DIV_… in GetFracPllFreq() local
/hal_nxp-3.5.0/mcux/mcux-sdk/components/codec/wm8962/
Dfsl_wm8962.c143 uint16_t refDiv = 0U, fllLock = 0U; in WM8962_SetInternalFllConfig() local
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/drivers/
Dfsl_clock.c836 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFC… in CLOCK_GetFracPllFreq() local
Dfsl_clock.h984 … uint8_t refDiv; /*!< A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ6/drivers/
Dfsl_clock.c836 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFC… in CLOCK_GetFracPllFreq() local
Dfsl_clock.h984 … uint8_t refDiv; /*!< A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/drivers/
Dfsl_clock.c836 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFC… in CLOCK_GetFracPllFreq() local
Dfsl_clock.h984 … uint8_t refDiv; /*!< A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD6/drivers/
Dfsl_clock.c836 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFC… in CLOCK_GetFracPllFreq() local
Dfsl_clock.h984 … uint8_t refDiv; /*!< A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD7/drivers/
Dfsl_clock.c836 …uint8_t refDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg0, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_REFC… in CLOCK_GetFracPllFreq() local
Dfsl_clock.h984 … uint8_t refDiv; /*!< A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ */ member