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28 #ifndef __ALTERA_AVALON_SGDMA_DESCRIPTOR_H__
29 #define __ALTERA_AVALON_SGDMA_DESCRIPTOR_H__
30 
31 #include "alt_types.h"
32 
33 /* Each Scatter-gather DMA buffer descriptor spans 0x20 of memory */
34 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE (0x20)
35 
36 
37 /*
38  * Descriptor control bit masks & offsets
39  *
40  * Note: The control byte physically occupies bits [31:24] in memory.
41  *       The following bit-offsets are expressed relative to the LSB of
42  *       the control register bitfield.
43  */
44 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x1)
45 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_OFST (0)
46 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x2)
47 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_OFST (1)
48 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x4)
49 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_OFST (2)
50 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_ATLANTIC_CHANNEL_MSK (0x8)
51 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_ATLANTIC_CHANNEL_OFST (3)
52 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x80)
53 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_OFST (7)
54 
55 /*
56  * Descriptor status bit masks & offsets
57  *
58  * Note: The status byte physically occupies bits [23:16] in memory.
59  *       The following bit-offsets are expressed relative to the LSB of
60  *       the status register bitfield.
61  */
62 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_E_CRC_MSK (0x1)
63 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_E_CRC_OFST (0)
64 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_E_PARITY_MSK (0x2)
65 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_E_PARITY_OFST (1)
66 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_E_OVERFLOW_MSK (0x4)
67 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_E_OVERFLOW_OFST (2)
68 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_E_SYNC_MSK (0x8)
69 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_E_SYNC_OFST (3)
70 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_E_UEOP_MSK (0x10)
71 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_E_UEOP_OFST (4)
72 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_E_MEOP_MSK (0x20)
73 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_E_MEOP_OFST (5)
74 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_E_MSOP_MSK (0x40)
75 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_E_MSOP_OFST (6)
76 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x80)
77 #define ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_OFST (7)
78 
79 /*
80  * To ensure that a descriptor is created without spaces
81  * between the struct members, we call upon GCC's ability
82  * to pack to a byte-aligned boundary.
83  */
84 #define alt_avalon_sgdma_packed __attribute__ ((packed,aligned(1)))
85 
86 /*
87  * Buffer Descriptor data structure
88  *
89  * The SGDMA controller buffer descriptor allocates
90  * 64 bits for each address. To support ANSI C, the
91  * struct implementing a descriptor places 32-bits
92  * of padding directly above each address; each pad must
93  * be cleared when initializing a descriptor.
94  */
95 typedef struct {
96     alt_u32   *read_addr;
97     alt_u32   read_addr_pad;
98 
99     alt_u32   *write_addr;
100     alt_u32   write_addr_pad;
101 
102     alt_u32   *next;
103     alt_u32   next_pad;
104 
105     alt_u16   bytes_to_transfer;
106     alt_u8    read_burst;
107     alt_u8    write_burst;
108 
109     alt_u16   actual_bytes_transferred;
110     alt_u8    status;
111     alt_u8    control;
112 
113 } alt_avalon_sgdma_packed alt_sgdma_descriptor;
114 
115 #endif /* __ALTERA_AVALON_SGDMA_DESCRIPTOR_H__ */
116