1 /***************************************************************************//**
2 * \file cy_smif_memslot.h
3 * \version 2.60
4 *
5 * \brief
6 * This file provides the constants and parameter values for the memory-level
7 * APIs of the SMIF driver.
8 *
9 * Note:
10 *
11 ********************************************************************************
12 * \copyright
13 * Copyright 2016-2022 Cypress Semiconductor Corporation
14 * SPDX-License-Identifier: Apache-2.0
15 *
16 * Licensed under the Apache License, Version 2.0 (the "License");
17 * you may not use this file except in compliance with the License.
18 * You may obtain a copy of the License at
19 *
20 * http://www.apache.org/licenses/LICENSE-2.0
21 *
22 * Unless required by applicable law or agreed to in writing, software
23 * distributed under the License is distributed on an "AS IS" BASIS,
24 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25 * See the License for the specific language governing permissions and
26 * limitations under the License.
27 *******************************************************************************/
28
29 #if !defined (CY_SMIF_MEMORYSLOT_H)
30 #define CY_SMIF_MEMORYSLOT_H
31
32 #include "cy_device.h"
33
34 #if defined (CY_IP_MXSMIF)
35
36 #include <stdint.h>
37 #include <stdbool.h>
38 #include "cy_syslib.h"
39 #include "cy_smif.h"
40
41 #if defined(__cplusplus)
42 extern "C" {
43 #endif
44
45 /**
46 * \addtogroup group_smif_macros_status
47 * \{
48 */
49
50 /***************************************
51 * Constants
52 ****************************************/
53 #define CY_SMIF_DEVICE_BUSY (1U) /**< The external memory is busy */
54 #define CY_SMIF_DEVICE_READY (0U) /**< The external memory is ready */
55
56 /** \} group_smif_macros_status */
57
58 /**
59 * \addtogroup group_smif_macros_cmd
60 * \{
61 */
62 #define CY_SMIF_CMD_WITHOUT_PARAM (0U) /**< No parameter */
63 #define CY_SMIF_TX_LAST_BYTE (1U) /**< The last byte in the command transmission
64 * (SS is set high after the transmission)
65 */
66 #define CY_SMIF_TX_NOT_LAST_BYTE (0U) /**< Not the last byte in the command transmission
67 * (SS remains low after the transmission)
68 */
69 #define CY_SMIF_READ_ONE_BYTE (1U) /**< Read 1 byte */
70 #define CY_SMIF_WRITE_ONE_BYTE (1U) /**< Write 1 byte */
71 #define CY_SMIF_WRITE_TWO_BYTES (2U) /**< Write 2 bytes */
72 #define CY_SMIF_ONE_WORD (4U) /**< 4 bytes */
73
74 #define CY_SMIF_DUAL_QUAD_DISABLED (0U) /**< The dual quad transmission mode is disabled */
75 #define CY_SMIF_DUAL_QUAD_ENABLED (1U) /**< The dual quad transmission mode is enabled */
76
77
78 /** \} group_smif_macros_status */
79
80 /**
81 * \addtogroup group_smif_macros_flags
82 * \{
83 */
84
85 #define CY_SMIF_FLAG_ALL_DISABLED (0U) /**< All memory configuration flags are disabled */
86 /** Enables the write capability for the memory slave in the memory-mapped
87 * mode. Valid when the memory-mapped mode is enabled */
88 #define CY_SMIF_FLAG_WRITE_ENABLE (1U)
89 /** Determines if the device is memory-mapped. If enabled, this memory slot will
90 * be initialized in System init */
91 #define CY_SMIF_FLAG_MEMORY_MAPPED (2U)
92 #define CY_SMIF_FLAG_DETECT_SFDP (4U) /**< Enables the Autodetect using the SFDP */
93 /** Enables the crypto support for this memory slave. All access to the
94 * memory device goes through the encryption/decryption
95 * Valid when the memory-mapped mode is enabled */
96 #define CY_SMIF_FLAG_CRYPTO_ENABLE (8U)
97
98 #if (CY_IP_MXSMIF_VERSION>=2) || defined (CY_DOXYGEN)
99 /**
100 * \note
101 * This macro is available for CAT1B, CAT1C and CAT1D devices.
102 **/
103 /** Enables IP version 3 features such as octal SPI/DDR mode/ 2 byte addressing
104 */
105 #define CY_SMIF_FLAG_SMIF_REV_3 (16U)
106
107 /** Continuous transfer merge enable.
108 * This skips the overhead (command, address, mode, dummy cycles) for a continuous
109 * (linear sequential) transfer. */
110 #define CY_SMIF_FLAG_MERGE_ENABLE (32U)
111
112 #endif /* CY_IP_MXSMIF_VERSION */
113
114 /** \} group_smif_macros_flags */
115
116 /**
117 * \addtogroup group_smif_macros_sfdp
118 * \{
119 */
120
121 /***************************************
122 * SFDP constants
123 ****************************************/
124 #define CY_SMIF_SFDP_ADDRESS_LENGTH (0x03U) /**< The length of the SFDP address */
125 #define CY_SMIF_SFDP_PARAM_HEADER_LENGTH (0x8U) /**< The length of the Parameter header */
126 #define CY_SMIF_SFDP_PARAMETER_TABLE_LENGTH (0x80U) /**< The length of the Parameter table */
127 #define CY_SMIF_SFDP_LENGTH (CY_SMIF_SFDP_PARAMETER_TABLE_LENGTH) /**< The length of the SFDP */
128 #define CY_SMIF_SFDP_SIGNATURE_BYTE_00 (0x00U) /**< The SFDP Signature byte 0x00. Should be "S" */
129 #define CY_SMIF_SFDP_SIGNATURE_BYTE_01 (0x01U) /**< The SFDP Signature byte 0x01. Should be "F" */
130 #define CY_SMIF_SFDP_SIGNATURE_BYTE_02 (0x02U) /**< The SFDP Signature byte 0x02. Should be "D" */
131 #define CY_SMIF_SFDP_SIGNATURE_BYTE_03 (0x03U) /**< The SFDP Signature byte 0x03. Should be "P" */
132 #define CY_SMIF_SFDP_MINOR_REV (0x04U) /**< The SFDP Header byte 0x04. Defines the JEDEC JESD216 Revision */
133 #define CY_SMIF_SFDP_MAJOR_REV (0x05U) /**< The SFDP Header byte 0x05. Defines the SFDP Major Revision */
134 #define CY_SMIF_SFDP_MAJOR_REV_1 (0x01U) /**< The SFDP Major Revision is 1 */
135 #define CY_SMIF_SFDP_JEDEC_REV_0 (0x00U) /**< The JEDEC JESD216 Revision is 0 */
136 #define CY_SMIF_SFDP_JEDEC_REV_B (0x06U) /**< The JEDEC JESD216 Revision is B */
137 #define CY_SMIF_SFDP_PARAM_TABLE_PTR (0x0CU) /**< Specifies the start of the JEDEC Basic Flash
138 * Parameter Table in the SFDP structure
139 */
140 #define CY_SMIF_SFDP_THREE_BYTES_ADDR_CODE (0x00U) /**< Code for the SFDP Address Bytes Number 3 */
141 #define CY_SMIF_SFDP_THREE_OR_FOUR_BYTES_ADDR_CODE (0x01U) /**< Code for the SFDP Address Bytes Number 3 or 4 */
142 #define CY_SMIF_SFDP_FOUR_BYTES_ADDR_CODE (0x02U) /**< Code for the SFDP Address Bytes Number 4 */
143 #define CY_SMIF_THREE_BYTES_ADDR (0x03U) /**< The address Bytes Number is 3 */
144 #define CY_SMIF_FOUR_BYTES_ADDR (0x04U) /**< The address Bytes Number is 4 */
145 #define CY_SMIF_READ_MODE_BYTE (0x5AU) /**< The mode byte for the SMIF read */
146 #define CY_SMIF_WRITE_STATUS_REG1_CMD (0x01U) /**< The write status register 1 command */
147 #define CY_SMIF_SINGLE_PROGRAM_CMD (0x02U) /**< The command for a single SMIF program */
148 #define CY_SMIF_SINGLE_READ_CMD (0x03U) /**< The command for a single SMIF read */
149 #define CY_SMIF_WRITE_DISABLE_CMD (0x04U) /**< The Write Disable command */
150 #define CY_SMIF_READ_STATUS_REG1_CMD (0x05U) /**< The read status register 1 command */
151 #define CY_SMIF_WRITE_ENABLE_CMD (0x06U) /**< The Write Enable command */
152 #define CY_SMIF_READ_STATUS_REG2_T1_CMD (0x35U) /**< The read status register 2 type 1 command */
153 #define CY_SMIF_WRITE_STATUS_REG2_T1_CMD (0x3EU) /**< The write status register 2 type 1 command */
154 #define CY_SMIF_WRITE_STATUS_REG2_T2_CMD (0x31U) /**< The write status register 2 type 2 command */
155 #define CY_SMIF_READ_STATUS_REG2_T2_CMD (0x3FU) /**< The read status register 2 type 2 command */
156 #define CY_SMIF_CHIP_ERASE_CMD (0x60U) /**< The Chip Erase command */
157 #define CY_SMIF_POWER_DOWN_CMD (0xB9U) /**< The Power-down command */
158 #define CY_SMIF_RELEASE_POWER_DOWN_CMD (0xABU) /**< The Release Power-down command */
159 #define CY_SMIF_QE_BIT_STATUS_REG2_T1 (0x02U) /**< The QE bit is in status register 2 type 1.
160 * It should be written as the second byte.
161 */
162 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_1S_1S (0x0CU) /**< The command for a 1S-1S-1S SMIF fast read with 4-byte addressing */
163 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_1S_2S (0x3CU) /**< The command for a 1S-1S-2S SMIF fast read with 4-byte addressing */
164 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_2S_2S (0xBCU) /**< The command for a 1S-2S-2S SMIF fast read with 4-byte addressing */
165 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_1S_4S (0x6CU) /**< The command for a 1S-1S-4S SMIF fast read with 4-byte addressing */
166 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_4S_4S (0xECU) /**< The command for a 1S-4S-4S SMIF fast read with 4-byte addressing */
167 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_1S_8S (0x7CU) /**< The command for a 1S-1S-8S SMIF fast read with 4-byte addressing */
168 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_8S_8S (0xCCU) /**< The command for a 1S-8S-8S SMIF fast read with 4-byte addressing */
169
170 #if (CY_IP_MXSMIF_VERSION>=2) || defined (CY_DOXYGEN)
171 /**
172 * \note
173 * This macro is available for CAT1B, CAT1C and CAT1D devices.
174 **/
175 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_4D_4D (0xEEU) /**< The command for a 1S-4D-4D SMIF fast read with 4-byte addressing */
176 #define CY_SMIF_FAST_READ_4_BYTES_CMD_1S_8D_8D (0xFDU) /**< The command for a 1S-8D-8D SMIF fast read with 4-byte addressing */
177 #endif /* CY_IP_MXSMIF_VERSION */
178
179 #define CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_1S_1S (0x12U) /**< The command for a 1S-1S-1S SMIF page program with 4-byte addressing */
180 #define CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_1S_4S (0x34U) /**< The command for a 1S-1S-4S SMIF page program with 4-byte addressing */
181 #define CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_4S_4S (0x3EU) /**< The command for a 1S-4S-4S SMIF page program with 4-byte addressing */
182 #define CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_1S_8S (0x84U) /**< The command for a 1S-1S-8S SMIF page program with 4-byte addressing */
183 #define CY_SMIF_PAGE_PROGRAM_4_BYTES_CMD_1S_8S_8S (0x8EU) /**< The command for a 1S-8S-8S SMIF page program with 4-byte addressing */
184
185 #define CY_SMIF_BRWR_EXTADD_MASK (0x80U) /**< The Extended Address Enable (EXTADD) mask */
186
187 #define CY_SMIF_SFDP_ERASE_TIME_1MS (1U) /**< Units of Erase Typical Time in ms */
188 #define CY_SMIF_SFDP_ERASE_TIME_16MS (16U) /**< Units of Erase Typical Time in ms */
189 #define CY_SMIF_SFDP_ERASE_TIME_128MS (128U) /**< Units of Erase Typical Time in ms */
190 #define CY_SMIF_SFDP_ERASE_TIME_1S (1000U) /**< Units of Erase Typical Time in ms */
191
192 #define CY_SMIF_SFDP_CHIP_ERASE_TIME_16MS (16U) /**< Units of Chip Erase Typical Time in ms */
193 #define CY_SMIF_SFDP_CHIP_ERASE_TIME_256MS (256U) /**< Units of Chip Erase Typical Time in ms */
194 #define CY_SMIF_SFDP_CHIP_ERASE_TIME_4S (4000U) /**< Units of Chip Erase Typical Time in ms */
195 #define CY_SMIF_SFDP_CHIP_ERASE_TIME_64S (64000U) /**< Units of Chip Erase Typical Time in ms */
196
197 #define CY_SMIF_SFDP_PROG_TIME_8US (8U) /**< Units of Page Program Typical Time in us */
198 #define CY_SMIF_SFDP_PROG_TIME_64US (64U) /**< Units of Page Program Typical Time in us */
199
200 #define CY_SMIF_SFDP_PROG_TIME_DEFAULT (100000U) /**< Default Page Program Time in us - 100 ms */
201 #define CY_SMIF_SFDP_PAGE_SIZE_DEFAULT (256U) /**< Default Page size used for SFDP 1.0 devices */
202
203 #define CY_SMIF_SFDP_UNIT_0 (0U) /**< Units of Basic Flash Parameter Table Time Parameters */
204 #define CY_SMIF_SFDP_UNIT_1 (1U) /**< Units of Basic Flash Parameter Table Time Parameters */
205 #define CY_SMIF_SFDP_UNIT_2 (2U) /**< Units of Basic Flash Parameter Table Time Parameters */
206 #define CY_SMIF_SFDP_UNIT_3 (3U) /**< Units of Basic Flash Parameter Table Time Parameters */
207
208
209 #define CY_SMIF_STATUS_REG_BUSY_MASK (0x01U) /**< The busy mask for the status registers */
210 #define CY_SMIF_NO_COMMAND_OR_MODE (0xFFFFFFFFUL) /**< No command or mode present */
211 #define CY_SMIF_SFDP_QE_BIT_1_OF_SR_2 (0x02UL) /**< The QE is bit 1 of the status register 2 */
212 #define CY_SMIF_SFDP_QE_BIT_6_OF_SR_1 (0x40UL) /**< The QE is bit 6 of the status register 1 */
213 #define CY_SMIF_SFDP_QE_BIT_7_OF_SR_2 (0x80UL) /**< The QE is bit 7 of the status register 2 */
214 #define CY_SMIF_SFDP_BFPT_BYTE_02 (0x02U) /**< The byte 0x02 of the JEDEC Basic Flash Parameter Table */
215 #define CY_SMIF_SFDP_BFPT_BYTE_04 (0x04U) /**< The byte 0x04 of the JEDEC Basic Flash Parameter Table */
216 #define CY_SMIF_SFDP_BFPT_BYTE_05 (0x05U) /**< The byte 0x05 of the JEDEC Basic Flash Parameter Table */
217 #define CY_SMIF_SFDP_BFPT_BYTE_06 (0x06U) /**< The byte 0x06 of the JEDEC Basic Flash Parameter Table:
218 * number of Parameter Headers (zero based, 05h = 6 parameters)
219 */
220 #define CY_SMIF_SFDP_BFPT_BYTE_08 (0x08U) /**< The byte 0x08 of the JEDEC Basic Flash Parameter Table */
221 #define CY_SMIF_SFDP_BFPT_BYTE_09 (0x09U) /**< The byte 0x09 of the JEDEC Basic Flash Parameter Table */
222 #define CY_SMIF_SFDP_BFPT_BYTE_0A (0x0AU) /**< The byte 0x0A of the JEDEC Basic Flash Parameter Table */
223 #define CY_SMIF_SFDP_BFPT_BYTE_0B (0x0BU) /**< The byte 0x0B of the JEDEC Basic Flash Parameter Table */
224 #define CY_SMIF_SFDP_BFPT_BYTE_0C (0x0CU) /**< The byte 0x0C of the JEDEC Basic Flash Parameter Table */
225 #define CY_SMIF_SFDP_BFPT_BYTE_0D (0x0DU) /**< The byte 0x0D of the JEDEC Basic Flash Parameter Table */
226 #define CY_SMIF_SFDP_BFPT_BYTE_0E (0x0EU) /**< The byte 0x0E of the JEDEC Basic Flash Parameter Table */
227 #define CY_SMIF_SFDP_BFPT_BYTE_0F (0x0FU) /**< The byte 0x0F of the JEDEC Basic Flash Parameter Table */
228 #define CY_SMIF_SFDP_BFPT_BYTE_1C (0x1CU) /**< The byte 0x1C of the JEDEC Basic Flash Parameter Table */
229 #define CY_SMIF_SFDP_BFPT_BYTE_1D (0x1DU) /**< The byte 0x1D of the JEDEC Basic Flash Parameter Table */
230 #define CY_SMIF_SFDP_BFPT_BYTE_23 (0x23U) /**< The byte 0x23 of the JEDEC Basic Flash Parameter Table */
231 #define CY_SMIF_SFDP_BFPT_BYTE_28 (0x28U) /**< The byte 0x28 of the JEDEC Basic Flash Parameter Table */
232 #define CY_SMIF_SFDP_BFPT_BYTE_3A (0x3AU) /**< The byte 0x3A of the JEDEC Basic Flash Parameter Table */
233 #define CY_SMIF_SFDP_BFPT_BYTE_3C (0x3CU) /**< The byte 0x3C of the JEDEC Basic Flash Parameter Table */
234 #define CY_SMIF_SFDP_BFPT_BYTE_3F (0x3FU) /**< The byte 0x3F of the JEDEC Basic Flash Parameter Table */
235 #define CY_SMIF_SFDP_BFPT_BYTE_40 (0x40U) /**< The byte 0x40 of the JEDEC Basic Flash Parameter Table */
236 #define CY_SMIF_SFDP_BFPT_BYTE_41 (0x41U) /**< The byte 0x41 of the JEDEC Basic Flash Parameter Table */
237 #define CY_SMIF_SFDP_BFPT_BYTE_42 (0x42U) /**< The byte 0x42 of the JEDEC Basic Flash Parameter Table */
238 #define CY_SMIF_SFDP_BFPT_BYTE_43 (0x43U) /**< The byte 0x43 of the JEDEC Basic Flash Parameter Table */
239
240 #define CY_SMIF_SFDP_BFPT_ERASE_BYTE (36U) /**< The byte 36 of the JEDEC Basic Flash Parameter Table */
241
242 #define CY_SMIF_JEDEC_BFPT_10TH_DWORD (9U) /**< Offset to JEDEC Basic Flash Parameter Table: 10th DWORD */
243 #define CY_SMIF_JEDEC_BFPT_11TH_DWORD (10U) /**< Offset to JEDEC Basic Flash Parameter Table: 11th DWORD */
244
245 #define CY_SMIF_SFDP_SCCR_MAP_BYTE_3B (0x3BU) /**< DWORD-16 of SCCR Map SPI table */
246 #define CY_SMIF_SFDP_OCTAL_ENABLE_WRITE_CMD_Pos (0U) /**< SCCR Map DWORD-16 Octal mode enable write command position */
247 #define CY_SMIF_SFDP_OCTAL_ENABLE_WRITE_CMD_Msk (0xFFU) /**< SCCR Map DWORD-16 Octal mode enable write command mask */
248 #define CY_SMIF_SFDP_OCTAL_ENABLE_READ_CMD_Pos (8U) /**< SCCR Map DWORD-16 Octal mode enable read command position */
249 #define CY_SMIF_SFDP_OCTAL_ENABLE_READ_CMD_Msk (0xFF00U) /**< SCCR Map DWORD-16 Octal mode enable read command mask */
250 #define CY_SMIF_SFDP_OCTAL_ENABLE_REG_ADDR_Pos (16U) /**< SCCR Map DWORD-16 Octal mode enable register address position */
251 #define CY_SMIF_SFDP_OCTAL_ENABLE_REG_ADDR_Msk (0xFF0000U) /**< SCCR Map DWORD-16 Octal mode enable register address mask */
252 #define CY_SMIF_SFDP_OCTAL_ENABLE_BIT_Pos (24U) /**< SCCR Map DWORD-16 Octal mode enable bit position */
253 #define CY_SMIF_SFDP_OCTAL_ENABLE_BIT_Msk (0x7000000U) /**< SCCR Map DWORD-16 Octal mode enable bit mask */
254 #define CY_SMIF_SFDP_OCTAL_ENABLE_USE_ADDRESS_Pos (28U) /**< SCCR Map DWORD-16 Octal mode enable uses address to set/clear position */
255 #define CY_SMIF_SFDP_OCTAL_ENABLE_USE_ADDRESS_Msk (0x10000000U) /**< SCCR Map DWORD-16 Octal mode enable uses address to set/clear mask */
256 #define CY_SMIF_SFDP_OCTAL_ENABLE_BIT_SUPPORT_Pos (31U) /**< SCCR Map DWORD-16 Octal mode enable bit support position */
257 #define CY_SMIF_SFDP_OCTAL_ENABLE_BIT_SUPPORT_Msk (0x80000000U) /**< SCCR Map DWORD-16 Octal mode enable bit support mask */
258
259 #define CY_SMIF_SFDP_SECTOR_MAP_CMD_OFFSET (1UL) /**< The offset for the detection command instruction in the Sector Map command descriptor */
260 #define CY_SMIF_SFDP_SECTOR_MAP_ADDR_LEN_OFFSET (2UL) /**< The offset for the detection command address length in the Sector Map command descriptor */
261 #define CY_SMIF_SFDP_SECTOR_MAP_REG_MSK_OFFSET (3UL) /**< The offset for the read data mask in the Sector Map command descriptor */
262 #define CY_SMIF_SFDP_SECTOR_MAP_REG_ADDR_OFFSET (4UL) /**< The offset for the detection command address in the Sector Map command descriptor */
263 #define CY_SMIF_SFDP_SECTOR_MAP_REGION_COUNT_OFFSET (2UL) /**< The offset for the regions count in the Sector Map descriptor */
264 #define CY_SMIF_SFDP_SECTOR_MAP_CONFIG_ID_OFFSET (2UL) /**< The offset for the configuration ID in the Sector Map descriptor */
265 #define CY_SMIF_SFDP_SECTOR_MAP_SUPPORTED_ET_MASK (0xFU) /**< The mask for the supported erase type code in the Sector Map descriptor */
266 #define CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES_Msk (0xC0UL) /**< The mask for the configuration detection command address bytes in the Sector Map descriptor */
267 #define CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES_Pos (6UL) /**< The position of the configuration detection command address bytes in the Sector Map descriptor */
268 #define CY_SMIF_SFDP_SECTOR_MAP_DUMMY_CYCLES_Msk (0xFUL) /**< The mask for the configuration detection command read latency cycles in the Sector Map descriptor */
269 #define CY_SMIF_SFDP_SECTOR_MAP_DUMMY_CYCLES_Pos (0UL) /**< The position of the configuration detection command read latency cycles in the Sector Map descriptor */
270
271 #define FOUR_BYTE_ADDRESS_TABLE_BYTE_0 (0U) /**< Byte 0x00 of the JEDEC 4-byte Address Instruction Table */
272 #define FOUR_BYTE_ADDRESS_TABLE_BYTE_1 (1U) /**< Byte 0x01 of the JEDEC 4-byte Address Instruction Table */
273
274
275 /* ---------------------------- 1st DWORD ---------------------------- */
276 #define CY_SMIF_SFDP_FAST_READ_1_1_4_Pos (6UL) /**< The SFDP 1-1-4 fast read support (Bit 6) */
277 #define CY_SMIF_SFDP_FAST_READ_1_1_4_Msk (0x40UL) /**< The SFDP 1-1-4 fast read support (Bitfield-Mask: 0x01) */
278 #define CY_SMIF_SFDP_FAST_READ_1_4_4_Pos (5UL) /**< The SFDP 1-4-4 fast read support (Bit 5) */
279 #define CY_SMIF_SFDP_FAST_READ_1_4_4_Msk (0x20UL) /**< The SFDP 1-4-4 fast read support (Bitfield-Mask: 0x01) */
280 #define CY_SMIF_SFDP_FAST_READ_1_2_2_Pos (4UL) /**< The SFDP 1-2-2 fast read support (Bit 4) */
281 #define CY_SMIF_SFDP_FAST_READ_1_2_2_Msk (0x10UL) /**< The SFDP 1-2-2 fast read support (Bitfield-Mask: 0x01) */
282
283 #if (CY_IP_MXSMIF_VERSION>=2) || defined (CY_DOXYGEN)
284 /**
285 * \note
286 * This macro is available for CAT1B, CAT1C and CAT1D devices.
287 **/
288 #define CY_SMIF_SFDP_DTR_SUPPORT_Pos (3UL) /**< The SFDP DTR support (Bit 3) */
289 /**
290 * \note
291 * This macro is available for CAT1B, CAT1C and CAT1D devices.
292 **/
293 #define CY_SMIF_SFDP_DTR_SUPPORT_Msk (0x08UL) /**< The SFDP DTR support (Bitfield-Mask: 0x08) */
294 #endif /* CY_IP_MXSMIF_VERSION */
295
296 #define CY_SMIF_SFDP_ADDRESS_BYTES_Pos (1UL) /**< The SFDP number of address bytes (Bit 1) */
297 #define CY_SMIF_SFDP_ADDRESS_BYTES_Msk (0x06UL) /**< The SFDP number of address bytes (Bitfield-Mask: 0x03) */
298 #define CY_SMIF_SFDP_FAST_READ_1_1_2_Pos (0UL) /**< The SFDP 1-1-2 fast read support (Bit 0) */
299 #define CY_SMIF_SFDP_FAST_READ_1_1_2_Msk (0x01UL) /**< The SFDP 1-1-2 fast read support (Bitfield-Mask: 0x01) */
300
301 /* ---------------------------- 2nd DWORD ---------------------------- */
302 #define CY_SMIF_SFDP_SIZE_ABOVE_4GB_Msk (0x80000000UL) /**< Flash memory density bit define if it >= 4 Gbit or <= 2Gbit */
303
304 /* ---------------------------- 3rd DWORD ---------------------------- */
305 #define CY_SMIF_SFDP_1_4_4_DUMMY_CYCLES_Pos (0UL) /**< The SFDP number of 1-4-4 fast read dummy cycles (Bit 0) */
306 #define CY_SMIF_SFDP_1_4_4_DUMMY_CYCLES_Msk (0x1FUL) /**< The SFDP number of 1-4-4 fast read dummy cycles (Bitfield-Mask: 0x1F) */
307 #define CY_SMIF_SFDP_1_4_4_MODE_CYCLES_Pos (5UL) /**< The SFDP number of 1-4-4 fast read mode cycles (Bit 5) */
308 #define CY_SMIF_SFDP_1_4_4_MODE_CYCLES_Msk (0xE0UL) /**< The SFDP number of 1-4-4 fast read mode cycles (Bitfield-Mask: 0x07) */
309 #define CY_SMIF_SFDP_1_1_4_DUMMY_CYCLES_Pos (0UL) /**< The SFDP number of 1-1-4 fast read dummy cycles (Bit 0) */
310 #define CY_SMIF_SFDP_1_1_4_DUMMY_CYCLES_Msk (0x1FUL) /**< The SFDP number of 1-1-4 fast read dummy cycles (Bitfield-Mask: 0x1F) */
311 #define CY_SMIF_SFDP_1_1_4_MODE_CYCLES_Pos (5UL) /**< The SFDP number of 1-1-4 fast read mode cycles (Bit 5) */
312 #define CY_SMIF_SFDP_1_1_4_MODE_CYCLES_Msk (0xE0UL) /**< The SFDP number of 1-1-4 fast read mode cycles (Bitfield-Mask: 0x07) */
313
314 /* ---------------------------- 4th DWORD ---------------------------- */
315 #define CY_SMIF_SFDP_1_1_2_DUMMY_CYCLES_Pos (0UL) /**< The SFDP number of 1_1_2 fast read dummy cycles (Bit 0) */
316 #define CY_SMIF_SFDP_1_1_2_DUMMY_CYCLES_Msk (0x1FUL) /**< The SFDP number of 1_1_2 fast read dummy cycles (Bitfield-Mask: 0x1F) */
317 #define CY_SMIF_SFDP_1_1_2_MODE_CYCLES_Pos (5UL) /**< The SFDP number of 1_1_2 fast read mode cycles (Bit 5) */
318 #define CY_SMIF_SFDP_1_1_2_MODE_CYCLES_Msk (0xE0UL) /**< The SFDP number of 1_1_2 fast read mode cycles (Bitfield-Mask: 0x07) */
319 #define CY_SMIF_SFDP_1_2_2_DUMMY_CYCLES_Pos (0UL) /**< The SFDP number of 1_2_2 fast read dummy cycles (Bit 0) */
320 #define CY_SMIF_SFDP_1_2_2_DUMMY_CYCLES_Msk (0x1FUL) /**< The SFDP number of 1_2_2 fast read dummy cycles (Bitfield-Mask: 0x1F) */
321 #define CY_SMIF_SFDP_1_2_2_MODE_CYCLES_Pos (5UL) /**< The SFDP number of 1_2_2 fast read mode cycles (Bit 5) */
322 #define CY_SMIF_SFDP_1_2_2_MODE_CYCLES_Msk (0xE0UL) /**< The SFDP number of 1_2_2 fast read mode cycles (Bitfield-Mask: 0x07) */
323
324 /* ---------------------------- 10th DWORD --------------------------- */
325 #define CY_SMIF_SFDP_ERASE_T1_COUNT_Pos (4UL) /**< Erase Type 1 Erase, Typical time: count (Bits 8:4) */
326 #define CY_SMIF_SFDP_ERASE_T1_COUNT_Msk (0x1F0UL) /**< Erase Type 1 Erase, Typical time: count (Bitfield-Mask ) */
327 #define CY_SMIF_SFDP_ERASE_T1_UNITS_Pos (9UL) /**< Erase Type 1 Erase, Typical time: units (Bits 10:9) */
328 #define CY_SMIF_SFDP_ERASE_T1_UNITS_Msk (0x600UL) /**< Erase Type 1 Erase, Typical time: units (Bitfield-Mask ) */
329 #define CY_SMIF_SFDP_ERASE_MUL_COUNT_Pos (0UL) /**< Multiplier from typical erase time to maximum erase time (Bits 3:0) */
330 #define CY_SMIF_SFDP_ERASE_MUL_COUNT_Msk (0x0FUL) /**< Multiplier from typical erase time to maximum erase time (Bitfield-Mask ) */
331
332
333 /* ---------------------------- 11th DWORD --------------------------- */
334 #define CY_SMIF_SFDP_PAGE_SIZE_Pos (4UL) /**< The SFDP page size (Bit 4) */
335 #define CY_SMIF_SFDP_PAGE_SIZE_Msk (0xF0UL) /**< The SFDP page size (Bitfield-Mask: 0x0F) */
336 #define CY_SMIF_SFDP_PAGE_PROG_COUNT_Pos (8UL) /**< The SFDP Chip Page Program Typical time: count (Bits 12:8) */
337 #define CY_SMIF_SFDP_PAGE_PROG_COUNT_Msk (0x1F00UL) /**< The SFDP Chip Page Program Typical time: count (Bitfield-Mask)*/
338 #define CY_SMIF_SFDP_PAGE_PROG_UNITS_Pos (13UL) /**< The SFDP Chip Page Program Typical time: units (Bit 13) */
339 #define CY_SMIF_SFDP_PAGE_PROG_UNITS_Msk (0x2000UL) /**< The SFDP Chip Page Program Typical time: units (Bitfield-Mask)*/
340 #define CY_SMIF_SFDP_CHIP_ERASE_COUNT_Pos (24UL) /**< The SFDP Chip Erase Typical time: count (Bits 28:24) */
341 #define CY_SMIF_SFDP_CHIP_ERASE_COUNT_Msk (0x1F000000UL) /**< The SFDP Chip Erase Typical time: count (Bitfield-Mask) */
342 #define CY_SMIF_SFDP_CHIP_ERASE_UNITS_Pos (29UL) /**< The SFDP Chip Erase Typical time: units (Bits 29:30) */
343 #define CY_SMIF_SFDP_CHIP_ERASE_UNITS_Msk (0x60000000UL) /**< The SFDP Chip Erase Typical time: units (Bitfield-Mask) */
344 #define CY_SMIF_SFDP_PROG_MUL_COUNT_Pos (0UL) /**< Multiplier from typical time to max time for Page or byte program (Bits 3:0) */
345 #define CY_SMIF_SFDP_PROG_MUL_COUNT_Msk (0x0FUL) /**< Multiplier from typical time to max time for Page or byte program (Bitfield-Mask) */
346
347 /* ---------------------------- 15th DWORD --------------------------- */
348 #define CY_SMIF_SFDP_QE_REQUIREMENTS_Pos (4UL) /**< The SFDP quad enable requirements field (Bit 4) */
349 #define CY_SMIF_SFDP_QE_REQUIREMENTS_Msk (0x70UL) /**< The SFDP quad enable requirements field (Bitfield-Mask: 0x07) */
350
351
352 /* ---------------------------- 16th DWORD --------------------------- */
353 #define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7 (1U) /**< Issue 0xB7 instruction */
354 #define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_WR_EN_B7 (2U) /**< Issue write enable instruction followed with 0xB7 */
355 #define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_ALWAYS_4_BYTE (0x40U) /**< Memory always operates in 4-byte mode */
356 #define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7_CMD (0xB7U) /**< The instruction required to enter 4-byte addressing mode */
357 #define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_SUPPORTED_MASK (0x7FU) /**< Mask indicating 4-byte address mode entry supported */
358
359 /* ---------------------------- 17th DWORD --------------------------- */
360 #define CY_SMIF_SFDP_FAST_READ_1_1_8_Pos (0UL) /**< The SFDP 1-1-8 fast read support (Bitfield 24:31) */
361 #define CY_SMIF_SFDP_FAST_READ_1_1_8_Msk (0xFFUL) /**< The SFDP 1-1-8 fast read support (Bitfield-Mask: 0xFF) */
362 #define CY_SMIF_SFDP_1_1_8_MODE_CYCLES_Pos (5UL) /**< The SFDP number of 1-1-8 fast read mode cycles (Bitfield 21:23) */
363 #define CY_SMIF_SFDP_1_1_8_MODE_CYCLES_Msk (0xE0UL) /**< The SFDP number of 1-1-8 fast read mode cycles (Bitfield-Mask: 0xE) */
364 #define CY_SMIF_SFDP_1_1_8_DUMMY_CYCLES_Pos (0UL) /**< The SFDP number of 1_1_8 fast read dummy cycles (Bit 16:19) */
365 #define CY_SMIF_SFDP_1_1_8_DUMMY_CYCLES_Msk (0x1FUL) /**< The SFDP number of 1_1_8 fast read dummy cycles (Bitfield-Mask: 0x1F) */
366 #define CY_SMIF_SFDP_FAST_READ_1_8_8_Pos (0UL) /**< The SFDP 1-8-8 fast read support (Bitfield 8:15) */
367 #define CY_SMIF_SFDP_FAST_READ_1_8_8_Msk (0xFFUL) /**< The SFDP 1-8-8 fast read support (Bitfield-Mask: 0xFF) */
368 #define CY_SMIF_SFDP_1_8_8_MODE_CYCLES_Pos (5UL) /**< The SFDP number of 1-8-8 fast read mode cycles (Bitfield 5:7) */
369 #define CY_SMIF_SFDP_1_8_8_MODE_CYCLES_Msk (0xE0UL) /**< The SFDP number of 1-8-8 fast read mode cycles (Bitfield-Mask: 0xE) */
370 #define CY_SMIF_SFDP_1_8_8_DUMMY_CYCLES_Pos (0UL) /**< The SFDP number of 1_8_8 fast read dummy cycles (Bit 0:4) */
371 #define CY_SMIF_SFDP_1_8_8_DUMMY_CYCLES_Msk (0x1FUL) /**< The SFDP number of 1_8_8 fast read dummy cycles (Bitfield-Mask: 0x1F) */
372
373 /* ---------------------------- 19th DWORD --------------------------- */
374 #define CY_SMIF_SFDP_OCTAL_ENABE_BIT_Pos (20UL) /**< Octal Enable bit present in the flash or not (Bitfiled 20:22)*/
375 #define CY_SMIF_SFDP_OCTAL_ENABE_BIT_Msk (0x700000) /**< Octal Enable bit present Mask (Bitfiled-Mask 0x7)*/
376
377 /* ---------------------------- xSPI Profile 1.0 ------------------------ */
378 #define XSPI_PROFILE_1_TABLE_BYTE_0 (0U) /**< Byte 0x00 of the JEDEC xSPI Profile 1.0 */
379 #define XSPI_PROFILE_1_TABLE_BYTE_1 (1U) /**< Byte 0x01 of the JEDEC xSPI Profile 1.0 */
380 #define XSPI_PROFILE_1_TABLE_BYTE_16 (0x10U) /**< DWORD 5 => Byte 16 of the JEDEC xSPI Profile 1.0 */
381
382 /* ---------------------------- 1st DWORD --------------------------- */
383 #define CY_SMIF_SFDP_OCTAL_DDR_READ_CMD_Pos (0UL) /**< Octal DDR 8D-8D-8D read command support position (Bitfield 8:15) */
384 #define CY_SMIF_SFDP_OCTAL_DDR_READ_CMD_Msk (0xFFUL) /**< Octal DDR 8D-8D-8D read command support Mask Bitfield-Mask: 0xFF00) */
385 #define CY_SMIF_SFDP_ODDR_166MHZ_DUMMY_CYCLES_Pos (27UL) /**< Octal DDR 8D-8D-8D dummy cycles for 166 Mhz (Bitfield 27:31) */
386 #define CY_SMIF_SFDP_ODDR_166MHZ_DUMMY_CYCLES_Msk (0xF8000000UL) /**< Octal DDR 8D-8D-8D dummy cycles for 166 Mhz Mask */
387 #define CY_SMIF_SFDP_ODDR_200MHZ_DUMMY_CYCLES_Pos (7UL) /**< Octal DDR 8D-8D-8D dummy cycles for 200 Mhz (Bitfield 7:11) */
388 #define CY_SMIF_SFDP_ODDR_200MHZ_DUMMY_CYCLES_Msk (0xF80UL) /**< Octal DDR 8D-8D-8D dummy cycles for 200 Mhz Mask */
389
390 /* ---------------------------- Command Sequence to Change to Octal DDR ------------------------ */
391 #define CMD_SEQ_OCTAL_DDR_CMD1_LEN_BYTE_OFFSET (3U) /**< Octal DDR enable command 1 sequence length byte offset */
392 #define CMD_SEQ_OCTAL_DDR_CMD2_LEN_BYTE_OFFSET (11U) /**< Octal DDR enable command 1 sequence length byte offset */
393 #define CY_SMIF_SFDP_ODDR_CMD_SEQ_MAX_LEN (8U) /**< Octal DDR enable command sequence maximum length */
394
395 /* --------------------------------- HyperBus Macros ------------------------------------------- */
396 #if (CY_IP_MXSMIF_VERSION>=2)
397 /** Following Hyperbus commands are to be used in a sequence as specified in the Hyper Flash/RAM data sheet.
398 Please check the Command Summery section in the respective data sheet for the sequence to be followed. */
399 /** LLD Command Definition */
400 #define CY_SMIF_NOR_CFI_QUERY_CMD (0x98) /**< HyperBus NOR CFI Query Command */
401 #define CY_SMIF_NOR_CHIP_ERASE_CMD (0x10) /**< HyperBus NOR Chip Erase Command */
402 #define CY_SMIF_NOR_ERASE_SETUP_CMD (0x80) /**< HyperBus NOR Erase Setup Command */
403 #define CY_SMIF_NOR_RESET_CMD (0xF0) /**< HyperBus NOR Reset Command */
404 #define CY_SMIF_NOR_SECSI_SECTOR_ENTRY_CMD (0x88) /**< HyperBus NOR SECI Sector Entry Command */
405 #define CY_SMIF_NOR_SECTOR_ERASE_CMD (0x30) /**< HyperBus NOR Sector Erase Command */
406 #define CY_SMIF_NOR_WRITE_BUFFER_LOAD_CMD (0x25) /**< HyperBus NOR Write Buffer load Command */
407 #define CY_SMIF_NOR_WRITE_BUFFER_PGM_CONFIRM_CMD (0x29) /**< HyperBus NOR Write Buffer Program Confirm Command */
408 #define CY_SMIF_NOR_SET_CONFIG_CMD (0xD0) /**< HyperBus NOR Set Config Command */
409 #define CY_SMIF_NOR_BIT_FIELD_CMD (0xBF) /**< HyperBus NOR Bit Field Command */
410
411 #define CY_SMIF_NOR_ERASE_SUSPEND_CMD (0xB0) /**< HyperBus NOR Erase Suspend Command */
412 #define CY_SMIF_NOR_ERASE_RESUME_CMD (0x30) /**< HyperBus NOR Erase Resume Command */
413 #define CY_SMIF_NOR_PROGRAM_SUSPEND_CMD (0x51) /**< HyperBus NOR Program Suspend Command */
414 #define CY_SMIF_NOR_PROGRAM_RESUME_CMD (0x50) /**< HyperBus NOR Program Resume Command */
415 #define CY_SMIF_NOR_STATUS_REG_READ_CMD (0x70) /**< HyperBus NOR Status Register Read Command */
416 #define CY_SMIF_NOR_STATUS_REG_CLEAR_CMD (0x71) /**< HyperBus NOR Status Register Clear Command */
417 #define CY_SMIF_NOR_BLANK_CHECK_CMD (0x33) /**< HyperBus NOR Blank Check Command */
418
419 #define CY_SMIF_ENTER_SPI_MODE_CMD (0xF5) /**< HyperBus NOR Enter SPI Mode Command */
420
421 /** Command code definition */
422 #define CY_SMIF_NOR_AUTOSELECT_CMD (0x90) /**< HyperBus NOR Auto Select Command */
423 #define CY_SMIF_NOR_PROGRAM_CMD (0xA0) /**< HyperBus NOR Program Command */
424 #define CY_SMIF_NOR_SECSI_SECTOR_EXIT_SETUP_CMD (0x90) /**< HyperBus NOR SECSI Sector Exit Setup Command */
425 #define CY_SMIF_NOR_SECSI_SECTOR_EXIT_CMD (0x00) /**< HyperBus NOR SECSI Sector Exit Command */
426 #define CY_SMIF_NOR_UNLOCK_BYPASS_ENTRY_CMD (0x20) /**< HyperBus NOR Unlock Bypass Entry Command */
427 #define CY_SMIF_NOR_UNLOCK_BYPASS_PROGRAM_CMD (0xA0) /**< HyperBus NOR Unlock Bypass Program Command */
428 #define CY_SMIF_NOR_UNLOCK_BYPASS_RESET_CMD1 (0x90) /**< HyperBus NOR Unlock Bypass Reset Command One */
429 #define CY_SMIF_NOR_UNLOCK_BYPASS_RESET_CMD2 (0x00) /**< HyperBus NOR Unlock Bypass Reset Command Two*/
430 #define CY_SMIF_NOR_UNLOCK_DATA1 (0xAA) /**< HyperBus NOR Unlock Data One */
431 #define CY_SMIF_NOR_UNLOCK_DATA2 (0x55) /**< HyperBus NOR Unlock Data Two */
432 #define CY_SMIF_NOR_SUSPEND_CMD (0xB0) /**< HyperBus NOR Suspend Command */
433 #define CY_SMIF_NOR_RESUME_CMD (0x30) /**< HyperBus NOR Resume Command */
434 #define CY_SMIF_NOR_READ_CONFIG_CMD (0xC6) /**< HyperBus NOR Read Config Command */
435 #define CY_SMIF_NOR_WRITE_BUFFER_ABORT_RESET_CMD (0xF0) /**< HyperBus NOR Write Buffer Abort Reset Command */
436
437 /** ---------------------------- Hyperbus Devise status register information -------------------- */
438
439 #define CY_SMIF_DEV_RDY_MASK (0x80) /**< Device Ready Bit */
440 #define CY_SMIF_DEV_ERASE_SUSP_MASK (0x40) /**< Erase Suspend Bit */
441 #define CY_SMIF_DEV_ERASE_MASK (0x20) /**< Erase Status Bit */
442 #define CY_SMIF_DEV_PROGRAM_MASK (0x10) /**< Program Status Bit */
443 #define CY_SMIF_DEV_RFU_MASK (0x08) /**< Reserved */
444 #define CY_SMIF_DEV_PROGRAM_SUSP_MASK (0x04) /**< Program Suspend Bit */
445 #define CY_SMIF_DEV_SEC_LOCK_MASK (0x02) /**< Sector lock Bit */
446 #define CY_SMIF_DEV_BANK_MASK (0x01) /**< Operation in current bank */
447 #define CY_SMIF_DEV_CRCSSB_MASK (0x0100) /**< CRC Suspend Bit, 1: suspend, 0: no suspend*/
448 #define CY_SMIF_DEV_ESTAT_MASK (0x01) /**< Sector Erase Status Bit (for Evaluate Erase Status)*/
449 /**<0=previous erase did not complete successfully*/
450 /**<1=previous erase completed successfully*/
451
452
453 #define CY_SMIF_HB_FLASH_UNLOCK_ADDR1 0x00000555 /**< HyperBus Unlock Address One */
454 #define CY_SMIF_HB_FLASH_UNLOCK_ADDR2 0x000002AA /**< HyperBus Unlock Address Two */
455 #define CY_SMIF_HB_FLASH_CFI_UNLOCK_ADDR1 0x00000055 /**< HyperBus CFI Unlock Address One */
456 typedef uint32_t CY_SMIF_FLASHDATA; /**< HyperBus Flash Data Type */
457 #endif /* (CY_IP_MXSMIF_VERSION>=2) */
458
459
460 /** \cond INTERNAL */
461
462 #if (CY_IP_MXSMIF_VERSION>=2)
463 /*****************************************************
464 * Define Hyper Flash/RAM read/write macro to be used by LLD *
465 *****************************************************/
466 #define CY_SMIF_FLASH_OFFSET(b,o) (*(( (volatile CY_SMIF_FLASHDATA*)(b) ) + (o)))
467
468 #if (CY_CPU_CORTEX_M7)
469 #define CY_SMIF_FLASH_WR(b,o,d)\
470 {\
471 __DMB();\
472 CY_SMIF_FLASH_OFFSET((b),(o)) = (d);\
473 }
474 #else
475 #define CY_SMIF_FLASH_WR(b,o,d) CY_SMIF_FLASH_OFFSET((b),(o)) = (d)
476 #endif
477 #define CY_SMIF_FLASH_RD(b,o) CY_SMIF_FLASH_OFFSET((b),(o))
478
479 #define CY_SMIF_HB_FLASH_BUF_SIZE_MULTIPLIER 1
480 #define HB_REG_SIZE_IN_HALFWORD 1
481
482 #endif /* (CY_IP_MXSMIF_VERSION>=2) */
483
484
485 /*******************************************************************************
486 * These are legacy constants and API. They are left here just
487 * for backward compatibility.
488 * Do not use them in new designs.
489 *******************************************************************************/
490
491 #define CY_SMIF_FLAG_WR_EN CY_SMIF_FLAG_WRITE_ENABLE
492 #define CY_SMIF_FLAG_CRYPTO_EN CY_SMIF_FLAG_CRYPTO_ENABLE
493 #define CY_SMIF_SFDP_SING_BYTE_00 CY_SMIF_SFDP_SIGNATURE_BYTE_00
494 #define CY_SMIF_SFDP_SING_BYTE_01 CY_SMIF_SFDP_SIGNATURE_BYTE_01
495 #define CY_SMIF_SFDP_SING_BYTE_02 CY_SMIF_SFDP_SIGNATURE_BYTE_02
496 #define CY_SMIF_SFDP_SING_BYTE_03 CY_SMIF_SFDP_SIGNATURE_BYTE_03
497 #define CY_SMIF_WR_STS_REG1_CMD CY_SMIF_WRITE_STATUS_REG1_CMD
498 #define CY_SMIF_WR_DISABLE_CMD CY_SMIF_WRITE_DISABLE_CMD
499 #define CY_SMIF_RD_STS_REG1_CMD CY_SMIF_READ_STATUS_REG1_CMD
500 #define CY_SMIF_WR_ENABLE_CMD CY_SMIF_WRITE_ENABLE_CMD
501 #define CY_SMIF_RD_STS_REG2_T1_CMD CY_SMIF_READ_STATUS_REG2_T1_CMD
502 #define CY_SMIF_WR_STS_REG2_CMD CY_SMIF_WRITE_STATUS_REG2_CMD
503 #define CY_SMIF_RD_STS_REG2_T2_CMD CY_SMIF_READ_STATUS_REG2_T2_CMD
504 #define CY_SMIF_QE_BIT_STS_REG2_T1 CY_SMIF_QE_BIT_STATUS_REG2_T1
505 #define CY_SMIF_STS_REG_BUSY_MASK CY_SMIF_STATUS_REG_BUSY_MASK
506
507 #define Cy_SMIF_Memslot_Init Cy_SMIF_MemInit
508 #define Cy_SMIF_Memslot_DeInit Cy_SMIF_MemDeInit
509 #define Cy_SMIF_Memslot_CmdWriteEnable Cy_SMIF_MemCmdWriteEnable
510 #define Cy_SMIF_Memslot_CmdWriteDisable Cy_SMIF_MemCmdWriteDisable
511 #define Cy_SMIF_Memslot_IsBusy Cy_SMIF_MemIsBusy
512 #define Cy_SMIF_Memslot_QuadEnable Cy_SMIF_MemQuadEnable
513 #define Cy_SMIF_Memslot_CmdReadSts Cy_SMIF_MemCmdReadStatus
514 #define Cy_SMIF_Memslot_CmdWriteSts Cy_SMIF_MemCmdWriteStatus
515 #define Cy_SMIF_Memslot_CmdChipErase Cy_SMIF_MemCmdChipErase
516 #define Cy_SMIF_Memslot_CmdSectorErase Cy_SMIF_MemCmdSectorErase
517 #define Cy_SMIF_Memslot_SfdpDetect Cy_SMIF_MemSfdpDetect
518 #define Cy_SMIF_Memslot_CmdProgram Cy_SMIF_MemCmdProgram
519 #define Cy_SMIF_Memslot_CmdRead Cy_SMIF_MemCmdRead
520
521 #define PARAM_ID_MSB_OFFSET (0x08U) /* The offset of Parameter ID MSB */
522 #define PARAM_ID_LSB_MASK (0xFFUL) /* The mask of Parameter ID LSB */
523 #define MEM_ADDR_VALID(addr, size) (0U == ((addr)%(size))) /* This address must be a multiple of
524 * the SMIF XIP memory size
525 */
526 #define MEM_MAPPED_SIZE_VALID(size) (((size) >= 0x10000U) && (0U == ((size)&((size)-1U))) )
527 #define MEM_ADDR_SIZE_VALID(addrSize) ((0U < (addrSize)) && ((addrSize) <= CY_SMIF_FOUR_BYTES_ADDR))
528
529 /* ----------------------------------------- HyperBus Internal definitions ----------------------------------- */
530 #if (CY_IP_MXSMIF_VERSION>=2)
531
532
533 /* Hyperbus address format
534 *
535 */
536
537 #define SMIF_HYPERBUS_ADR_LOWER_COL_ADDRESS_Pos 0UL
538 #define SMIF_HYPERBUS_ADR_LOWER_COL_ADDRESS_Msk 0x7UL
539 #define SMIF_HYPERBUS_ADR_BYTE_ENABLE_Pos 13UL
540 #define SMIF_HYPERBUS_ADR_BYTE_ENABLE_Msk 0x6000UL
541 #define SMIF_HYPERBUS_ADR_ROW_AND_UPPER_COL_ADDRESS_Pos 16UL
542 #define SMIF_HYPERBUS_ADR_ROW_AND_UPPER_COL_ADDRESS_Msk 0xFFFF0000UL
543
544 #define SMIF_HYPERBUS_CMD_ADDRESS_LAST_BYTE_Pos 0UL
545 #define SMIF_HYPERBUS_CMD_ADDRESS_LAST_BYTE_Msk 0x3FUL
546 #define SMIF_HYPERBUS_CMD_BURST_TYPE_Pos 13UL
547 #define SMIF_HYPERBUS_CMD_BURST_TYPE_Msk 0x2000UL
548 #define SMIF_HYPERBUS_CMD_TARGET_TYPE_Pos 14UL
549 #define SMIF_HYPERBUS_CMD_TARGET_TYPE_Msk 0x4000UL
550 #define SMIF_HYPERBUS_CMD_READ_WRITE_Pos 15UL
551 #define SMIF_HYPERBUS_CMD_READ_WRITE_Msk 0x8000UL
552 #endif /* (CY_IP_MXSMIF_VERSION>=2) */
553
554 /** \endcond */
555 /** \} group_smif_macros_sfdp */
556
557
558 /**
559 * \addtogroup group_smif_data_structures_memslot
560 * \{
561 */
562
563 /** This command structure is used to store the Read/Write command
564 * configuration. */
565 typedef struct
566 {
567 uint32_t command; /**< The 8-bit command. This value is 0xFFFFFFFF when there is no command present */
568 cy_en_smif_txfr_width_t cmdWidth; /**< The width of the command transfer */
569 cy_en_smif_txfr_width_t addrWidth; /**< The width of the address transfer */
570 uint32_t mode; /**< The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present */
571 cy_en_smif_txfr_width_t modeWidth; /**< The width of the mode transfer */
572 uint32_t dummyCycles; /**< The number of the dummy cycles. A zero value suggests no dummy cycles */
573 cy_en_smif_txfr_width_t dataWidth; /**< The width of the data transfer */
574 #if (CY_IP_MXSMIF_VERSION>=2) || defined (CY_DOXYGEN)
575 /**
576 * \note
577 * This parameter is available for CAT1B, CAT1C and CAT1D devices.
578 **/
579 cy_en_smif_data_rate_t dataRate; /**< The Data rate of data */
580 /**
581 * \note
582 * This parameter is available for CAT1B, CAT1C and CAT1D devices.
583 **/
584 cy_en_smif_field_presence_t dummyCyclesPresence; /**< This specifies the presence of the dummy field */
585 /**
586 * \note
587 * This parameter is available for CAT1B, CAT1C and CAT1D devices.
588 **/
589 cy_en_smif_field_presence_t modePresence; /**< This specifies the presence of the mode field */
590 /**
591 * \note
592 * This parameter is available for CAT1B, CAT1C and CAT1D devices.
593 **/
594 uint32_t modeH; /**< The 8-bit command. This value is 0x0 when there is no higher byte mode present */
595 /**
596 * \note
597 * This parameter is available for CAT1B, CAT1C and CAT1D devices.
598 **/
599 cy_en_smif_data_rate_t modeRate; /**< The Data rate of mode */
600 /**
601 * \note
602 * This parameter is available for CAT1B, CAT1C and CAT1D devices.
603 **/
604 cy_en_smif_data_rate_t addrRate; /**< The Data rate of address */
605 /**
606 * \note
607 * This parameter is available for CAT1B, CAT1C and CAT1D devices.
608 **/
609 cy_en_smif_field_presence_t cmdPresence; /**< This specifies the presence of the command field */
610 /**
611 * \note
612 * This parameter is available for CAT1B, CAT1C and CAT1D devices.
613 **/
614 uint32_t commandH; /**< The 8-bit command. This value is 0x0 when there is no higher byte command present */
615 /**
616 * \note
617 * This parameter is available for CAT1B, CAT1C and CAT1D devices.
618 **/
619 cy_en_smif_data_rate_t cmdRate; /**< The Data rate of command */
620 #endif /* CY_IP_MXSMIF_VERSION */
621 } cy_stc_smif_mem_cmd_t;
622
623 /** This structure specifies data used for memory with hybrid sectors */
624 typedef struct
625 {
626 uint32_t regionAddress; /**< This specifies the address where a region starts */
627 uint32_t sectorsCount; /**< This specifies the number of sectors in the region */
628 uint32_t eraseCmd; /**< This specifies the region specific erase instruction */
629 uint32_t eraseSize; /**< This specifies the size of one sector */
630 uint32_t eraseTime; /**< Max time for sector erase type 1 cycle time in ms */
631 } cy_stc_smif_hybrid_region_info_t;
632
633 #if(CY_IP_MXSMIF_VERSION>=2)
634 /** This structure specifies data used for memory with hybrid sectors */
635 typedef struct
636 {
637 uint8_t cmdSeq1Len; /**< This specifies command sequence 1 length. */
638 uint8_t cmdSeq2Len; /**< This specifies command sequence 2 length. */
639 uint8_t cmdSeq1[CY_SMIF_SFDP_ODDR_CMD_SEQ_MAX_LEN]; /**< This specifies command sequence 1. */
640 uint8_t cmdSeq2[CY_SMIF_SFDP_ODDR_CMD_SEQ_MAX_LEN]; /**< This specifies command sequence 2. */
641 } cy_stc_smif_octal_ddr_en_seq_t;
642 #endif
643
644
645 /* ------------------------------------------------- HyperBus Enums ---------------------------------------------- */
646 #if (CY_IP_MXSMIF_VERSION>=2)
647
648 /** Specifies top 8 bit of read/write sequence (bit 47 ~ bit 40). only top 3 bits have meaning */
649 /** bit 47: Identifies the transaction as a Read or Write. R/W#=1 indicates a Read operation and R/W#=0 indicates a Write operation. */
650 /** bit 46: Indicates whether the Read or Write operation accesses the memory or register spaces. */
651 /** bit 45: Indicates whether the burst will be continuous or wrapped. Burst Type=0 indicates Wrapped Burst, Burst Type=1 indicates Continuous Burst. */
652 /** bit 46 is always 0, since this drive assumes accessing memory space in XIP mode */
653 typedef enum
654 {
655 CY_SMIF_HB_READ_WRAPPED_BURST = 0x80, /**< bit 47 = 1: read, bit 45 = 0: wrapped burst */
656 CY_SMIF_HB_READ_CONTINUOUS_BURST = 0xA0, /**< bit 47 = 1: read, bit 45 = 1: continuous burst */
657 } cy_en_smif_hb_rd_cmd_t;
658
659 /** see \ref cy_en_smif_hb_rd_cmd_t */
660 typedef enum
661 {
662 CY_SMIF_HB_WRITE_WRAPPED_BURST = 0x00, /**< bit 47 = 0: write, bit 45 = 0: wrapped burst */
663 CY_SMIF_HB_WRITE_CONTINUOUS_BURST = 0x20, /**< bit 47 = 0: write, bit 45 = 1: continuous burst */
664 } cy_en_smif_hb_wt_cmd_t;
665
666 /** Specifies hyper bus device type. FLASH or SRAM */
667 typedef enum
668 {
669 CY_SMIF_HB_FLASH = 0, /**< Hyper bus FLASH */
670 CY_SMIF_HB_SRAM = 1, /**< Hyper bus SRAM */
671 } cy_en_smif_hb_dev_type_t;
672
673 /** The size of the device region specified by DEVICE_MASK register */
674 typedef enum // casting int32_t is to avoid compiler error.
675 {
676 CY_SMIF_DEVICE_1M_BYTE = (int32_t)(0xFFF00000UL), /**< for 1M size device */
677 CY_SMIF_DEVICE_2M_BYTE = (int32_t)(0xFFE00000UL), /**< for 2M size device */
678 CY_SMIF_DEVICE_4M_BYTE = (int32_t)(0xFFC00000UL), /**< for 4M size device */
679 CY_SMIF_DEVICE_8M_BYTE = (int32_t)(0xFF800000UL), /**< for 8M size device */
680 CY_SMIF_DEVICE_16M_BYTE = (int32_t)(0xFF000000UL), /**< for 16M size device */
681 CY_SMIF_DEVICE_32M_BYTE = (int32_t)(0xFE000000UL), /**< for 32M size device */
682 CY_SMIF_DEVICE_64M_BYTE = (int32_t)(0xFC000000UL), /**< for 64M size device */
683 CY_SMIF_DEVICE_128M_BYTE = (int32_t)(0xF8000000UL), /**< for 128M size device */
684 CY_SMIF_DEVICE_256M_BYTE = (int32_t)(0xF0000000UL), /**< for 256M size device */
685 CY_SMIF_DEVICE_512M_BYTE = (int32_t)(0xE0000000UL), /**< for 512M size device */
686 CY_SMIF_DEVICE_1G_BYTE = (int32_t)(0xC0000000UL), /**< for 1G size device */
687 CY_SMIF_DEVICE_2G_BYTE = (int32_t)(0x80000000UL), /**< for 2G size device */
688 CY_SMIF_DEVICE_4G_BYTE = (int32_t)(0x00000000UL), /**< for 4G size device */
689 } cy_en_device_size_t;
690
691 /** Specifies the size of a memory sub page */
692 typedef enum
693 {
694 SUB_PAGE_SIZE_8BYTE = 0, /**< sub_page_size = 8 words = 16 bytes (default) */
695 SUB_PAGE_SIZE_16BYTE = 1, /**< sub_page_size = 16 words = 32 bytes */
696 SUB_PAGE_SIZE_32BYTE = 2, /**< sub_page_size = 32 words = 64 bytes */
697 SUB_PAGE_SIZE_64BYTE = 3,/**< sub_page_size = 64 words = 128 bytes */
698 } en_cy_sub_page_size_t;
699
700 /** Specifies the number of sub pages per page */
701 typedef enum
702 {
703 SUB_PAGE_1_PER_PAGE = 0, /**< 1 sub pages per page, i.e. page_size = sub_page_size */
704 SUB_PAGE_2_PER_PAGE = 1, /**< 2 sub pages per page, i.e. page_size = 2 x sub_page_size */
705 SUB_PAGE_4_PER_PAGE = 2, /**< 4 sub pages per page, i.e. page_size = 4 x sub_page_size */
706 SUB_PAGE_8_PER_PAGE = 3, /**< 8 sub pages per page, i.e. page_size = 8 x sub_page_size */
707 } en_cy_sub_page_nr_t;
708
709 /** Specifies the size of the XIP device address in Bytes */
710 typedef enum
711 {
712 CY_SMIF_XIP_ADDRESS_1_BYTE = 0, /**< 1 Byte address */
713 CY_SMIF_XIP_ADDRESS_2_BYTE = 1, /**< 2 Byte address */
714 CY_SMIF_XIP_ADDRESS_3_BYTE = 2, /**< 3 Byte address */
715 CY_SMIF_XIP_ADDRESS_4_BYTE = 3, /**< 4 Byte address */
716 CY_SMIF_XIP_ADDRESS_5_BYTE = 7, /**< 4 Byte address (spread over 5 bytes) according to Hyperbus protocol */
717 } cy_en_smif_xip_addr_byte_t;
718
719 /** Specify whether command to be transmitted is last one or not */
720 typedef enum
721 {
722 NOT_LAST_COMMAND = 0, /**< not last command */
723 LAST_COMMAND_BYTE = 1,/**< last command */
724 } cy_en_smif_cmd_last_t;
725
726 typedef enum
727 {
728 CY_SMIF_HB_WRAPPED_BURST = 0, /**< continue to wrap within the burst length */
729 CY_SMIF_HB_COUTINUOUS_BURST = 1, /**< output data in a sequential manner across page boundaries */
730 } cy_en_hb_burst_type_t;
731
732 /** read target. memory or register */
733 typedef enum
734 {
735 CY_SMIF_HB_TARGET_MEMORY = 0, /**< memory */
736 CY_SMIF_HB_TARGET_REGISTER = 1, /**< register. it is used only for hyper SRAM */
737 } cy_en_hb_target_t;
738
739 /** read or write */
740 typedef enum
741 {
742 CY_SMIF_HB_WRITE = 0, /**< write */
743 CY_SMIF_HB_READ = 1, /**< read */
744 } cy_en_hb_read_write_t;
745
746
747 /* ----------------------------------------------------- HyperBus Data Structures ----------------------------------- */
748
749
750 typedef struct
751 {
752 cy_en_smif_hb_rd_cmd_t xipReadCmd; /**< read command value \ref cy_en_smif_hb_rd_cmd_t */
753 cy_en_smif_hb_wt_cmd_t xipWriteCmd; /**< write command value \ref cy_en_smif_hb_rd_cmd_t */
754 cy_en_smif_hb_dev_type_t hbDevType; /**< hyper bus device type \ref cy_en_smif_hb_dev_type_t */
755 cy_en_device_size_t memSize; /**< The memory size: For densities of 2 gigabits or less - the size in bytes;
756 * For densities 4 gigabits and above - bit-31 is set to 1b to define that
757 * this memory is 4 gigabits and above; and other 30:0 bits define N where
758 * the density is computed as 2^N bytes.
759 * For example, 0x80000021 corresponds to 2^30 = 1 gigabyte.
760 */
761 uint32_t dummyCycles; /**< dummy Cycles based on Frequency of operation */
762 } cy_stc_smif_hbmem_device_config_t;
763 #endif /* (CY_IP_MXSMIF_VERSION>=2) */
764 /**
765 *
766 * This configuration structure of the SMIF memory device is used to store
767 * device-specific parameters.
768 * These parameters are used to set up the memory mode initialization and the
769 * memory API.
770 */
771 typedef struct
772 {
773 uint32_t numOfAddrBytes; /**< This specifies the number of address bytes used by the
774 * memory slave device, valid values 1-4 */
775 uint32_t memSize; /**< The memory size: For densities of 2 gigabits or less - the size in bytes;
776 * For densities 4 gigabits and above - bit-31 is set to 1b to define that
777 * this memory is 4 gigabits and above; and other 30:0 bits define N where
778 * the density is computed as 2^N bytes.
779 * For example, 0x80000021 corresponds to 2^30 = 1 gigabyte.
780 */
781 cy_stc_smif_mem_cmd_t* readCmd; /**< This specifies the Read command */
782 cy_stc_smif_mem_cmd_t* writeEnCmd; /**< This specifies the Write Enable command */
783 cy_stc_smif_mem_cmd_t* writeDisCmd; /**< This specifies the Write Disable command */
784 cy_stc_smif_mem_cmd_t* eraseCmd; /**< This specifies the Erase command */
785 uint32_t eraseSize; /**< This specifies the sector size of each Erase */
786 cy_stc_smif_mem_cmd_t* chipEraseCmd; /**< This specifies the Chip Erase command */
787 cy_stc_smif_mem_cmd_t* programCmd; /**< This specifies the Program command */
788 uint32_t programSize; /**< This specifies the page size for programming */
789 cy_stc_smif_mem_cmd_t* readStsRegWipCmd; /**< This specifies the command to read the WIP-containing status register */
790 cy_stc_smif_mem_cmd_t* readStsRegQeCmd; /**< This specifies the command to read the QE-containing status register */
791 cy_stc_smif_mem_cmd_t* writeStsRegQeCmd; /**< This specifies the command to write into the QE-containing status register */
792 cy_stc_smif_mem_cmd_t* readSfdpCmd; /**< This specifies the read SFDP command */
793 uint32_t stsRegBusyMask; /**< The Busy mask for the status registers */
794 uint32_t stsRegQuadEnableMask; /**< The QE mask for the status registers */
795 uint32_t eraseTime; /**< Max time for erase type 1 cycle time in ms */
796 uint32_t chipEraseTime; /**< Max time for chip erase cycle time in ms */
797 uint32_t programTime; /**< Max time for page program cycle time in us */
798 uint32_t hybridRegionCount; /**< This specifies the number of regions for memory with hybrid sectors */
799 cy_stc_smif_hybrid_region_info_t** hybridRegionInfo; /**< This specifies data for memory with hybrid sectors */
800 cy_stc_smif_mem_cmd_t* readLatencyCmd; /**< This specifies the command to read variable latency cycles configuration register */
801 cy_stc_smif_mem_cmd_t* writeLatencyCmd; /**< This specifies the command to write variable latency cycles configuration register */
802 uint32_t latencyCyclesRegAddr; /**< This specifies the address for variable latency cycle address */
803 uint32_t latencyCyclesMask; /**< This specifies variable latency cycles Mask */
804 #if(CY_IP_MXSMIF_VERSION>=2)
805 cy_stc_smif_octal_ddr_en_seq_t* octalDDREnableSeq; /**< This specifies data for memory with hybrid sectors */
806 cy_stc_smif_mem_cmd_t* readStsRegOeCmd; /**< This specifies the command to read the OE-containing status register */
807 cy_stc_smif_mem_cmd_t* writeStsRegOeCmd; /**< This specifies the command to write into the OE-containing status register */
808 uint32_t stsRegOctalEnableMask; /**< The QE mask for the status registers */
809 uint32_t octalEnableRegAddr; /**< Octal enable register address */
810 cy_en_smif_interface_freq_t freq_of_operation; /**< Frequency of operation used in Octal mode */
811 #endif
812 } cy_stc_smif_mem_device_cfg_t;
813
814
815 /**
816 *
817 * This SMIF memory configuration structure is used to store the memory configuration for the memory mode of operation.
818 * This data structure is stored in a fixed location in the flash. The data structure is required
819 * for the initialization of the SMIF in the SystemInit.
820 */
821 typedef struct
822 {
823 /** Determines the slave select where the memory device is placed */
824 cy_en_smif_slave_select_t slaveSelect;
825 /** Determines if the device is memory-mapped, enables the Autodetect
826 * using the SFDP, enables the write capability, or enables the crypto
827 * support for this memory slave */
828 uint32_t flags;
829 /** The data-line selection options for a slave device */
830 cy_en_smif_data_select_t dataSelect;
831 /** The base address the memory slave is mapped to in the PSoC memory map.
832 * This address must be a multiple of the SMIF XIP memory size/capacity. The
833 * SMIF XIP memory region should NOT overlap with other memory regions
834 * (with exception to dual quad mode). Valid when the memory-mapped mode is
835 * enabled.
836 */
837 uint32_t baseAddress;
838 /** The size/capacity allocated in the PSoC memory map for the memory slave
839 * device. The capacity is allocated from the base address. The capacity
840 * must be a power of 2 and greater or equal than 64 KB. Valid when
841 * memory-mapped mode is enabled
842 */
843 uint32_t memMappedSize;
844 /** Defines if this memory device is one of the devices in the dual quad SPI
845 * configuration. Equals the sum of the slave-slot numbers. */
846 uint32_t dualQuadSlots;
847 cy_stc_smif_mem_device_cfg_t* deviceCfg; /**< The configuration of the device */
848 #if(CY_IP_MXSMIF_VERSION>=2)
849 /** Continuous transfer merge timeout.
850 * After this period the memory device is deselected. A later transfer, even from a
851 * continuous address, starts with the overhead phases (command, address, mode, dummy cycles).
852 * This configuration parameter is available for CAT1B, CAT1C and CAT1D devices. */
853 cy_en_smif_merge_timeout_t mergeTimeout;
854
855 cy_stc_smif_hbmem_device_config_t* hbdeviceCfg; /**< The configuration of the hyperbus device */
856 #endif /* CY_IP_MXSMIF_VERSION */
857
858 } cy_stc_smif_mem_config_t;
859
860
861 /**
862 *
863 * This SMIF memory configuration structure is used to store the memory configuration for the memory mode of operation.
864 * This data structure is stored in a fixed location in the flash. The data structure is required
865 * for the initialization of the SMIF in the SystemInit.
866 */
867 typedef struct
868 {
869 uint32_t memCount; /**< The number of SMIF memory defined */
870 cy_stc_smif_mem_config_t** memConfig; /**< The pointer to the array of the memory configuration structures of size Memory_count */
871 uint32_t majorVersion; /**< The version of the SMIF driver */
872 uint32_t minorVersion; /**< The version of the SMIF Driver */
873 } cy_stc_smif_block_config_t;
874
875
876 /** \} group_smif_data_structures_memslot */
877
878
879 /**
880 * \addtogroup group_smif_mem_slot_functions
881 * \{
882 */
883 cy_en_smif_status_t Cy_SMIF_MemInit(SMIF_Type *base,
884 cy_stc_smif_block_config_t const * blockConfig,
885 cy_stc_smif_context_t *context);
886 void Cy_SMIF_MemDeInit(SMIF_Type *base);
887 cy_en_smif_status_t Cy_SMIF_MemCmdWriteEnable( SMIF_Type *base,
888 cy_stc_smif_mem_config_t const *memDevice,
889 cy_stc_smif_context_t const *context);
890 cy_en_smif_status_t Cy_SMIF_MemCmdWriteDisable(SMIF_Type *base,
891 cy_stc_smif_mem_config_t const *memDevice,
892 cy_stc_smif_context_t const *context);
893 bool Cy_SMIF_MemIsBusy(SMIF_Type *base, cy_stc_smif_mem_config_t const *memDevice,
894 cy_stc_smif_context_t const *context);
895 cy_en_smif_status_t Cy_SMIF_MemQuadEnable(SMIF_Type *base,
896 cy_stc_smif_mem_config_t const *memDevice,
897 cy_stc_smif_context_t const *context);
898 #if (CY_IP_MXSMIF_VERSION>=2) || defined (CY_DOXYGEN)
899 cy_en_smif_status_t Cy_SMIF_MemOctalEnable(SMIF_Type *base,
900 cy_stc_smif_mem_config_t const *memDevice,
901 cy_en_smif_data_rate_t dataRate,
902 cy_stc_smif_context_t const *context);
903 #endif
904
905 cy_en_smif_status_t Cy_SMIF_MemCmdReadStatus(SMIF_Type *base,
906 cy_stc_smif_mem_config_t const *memDevice,
907 uint8_t *status, uint8_t command,
908 cy_stc_smif_context_t const *context);
909 cy_en_smif_status_t Cy_SMIF_MemCmdWriteStatus(SMIF_Type *base,
910 cy_stc_smif_mem_config_t const *memDevice,
911 void const *status, uint8_t command,
912 cy_stc_smif_context_t const *context);
913 cy_en_smif_status_t Cy_SMIF_MemCmdChipErase(SMIF_Type *base,
914 cy_stc_smif_mem_config_t const *memDevice,
915 cy_stc_smif_context_t const *context);
916 cy_en_smif_status_t Cy_SMIF_MemCmdSectorErase(SMIF_Type *base,
917 cy_stc_smif_mem_config_t const *memDevice,
918 uint8_t const *sectorAddr,
919 cy_stc_smif_context_t const *context);
920 cy_en_smif_status_t Cy_SMIF_MemCmdProgram(SMIF_Type *base,
921 cy_stc_smif_mem_config_t const *memDevice,
922 uint8_t const *addr,
923 uint8_t const *writeBuff,
924 uint32_t size,
925 cy_smif_event_cb_t cmdCompleteCb,
926 cy_stc_smif_context_t *context);
927 cy_en_smif_status_t Cy_SMIF_MemCmdRead(SMIF_Type *base,
928 cy_stc_smif_mem_config_t const *memDevice,
929 uint8_t const *addr,
930 uint8_t *readBuff,
931 uint32_t size,
932 cy_smif_event_cb_t cmdCompleteCb,
933 cy_stc_smif_context_t *context);
934 cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base,
935 cy_stc_smif_mem_device_cfg_t *device,
936 cy_en_smif_slave_select_t slaveSelect,
937 cy_en_smif_data_select_t dataSelect,
938 cy_stc_smif_context_t *context);
939
940 cy_en_smif_status_t Cy_SMIF_MemInitSfdpMode(SMIF_Type *base,
941 const cy_stc_smif_mem_config_t *memCfg,
942 cy_en_smif_txfr_width_t maxdataWidth,
943 cy_en_smif_qer_t qer_id,
944 cy_stc_smif_context_t *context);
945
946 cy_en_smif_status_t Cy_SMIF_MemIsReady(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig,
947 uint32_t timeoutUs, cy_stc_smif_context_t const *context);
948 cy_en_smif_status_t Cy_SMIF_MemIsQuadEnabled(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig,
949 bool *isQuadEnabled, cy_stc_smif_context_t const *context);
950 cy_en_smif_status_t Cy_SMIF_MemEnableQuadMode(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig,
951 uint32_t timeoutUs, cy_stc_smif_context_t const *context);
952 cy_en_smif_status_t Cy_SMIF_MemRead(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig,
953 uint32_t address, uint8_t rxBuffer[],
954 uint32_t length, cy_stc_smif_context_t const *context);
955 cy_en_smif_status_t Cy_SMIF_MemWrite(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig,
956 uint32_t address, uint8_t const txBuffer[],
957 uint32_t length, cy_stc_smif_context_t const *context);
958 cy_en_smif_status_t Cy_SMIF_MemEraseSector(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig,
959 uint32_t address, uint32_t length,
960 cy_stc_smif_context_t const *context);
961 cy_en_smif_status_t Cy_SMIF_MemEraseChip(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig,
962 cy_stc_smif_context_t const *context);
963 cy_en_smif_status_t Cy_SMIF_MemLocateHybridRegion(cy_stc_smif_mem_config_t const *memDevice,
964 cy_stc_smif_hybrid_region_info_t** regionInfo, uint32_t address);
965 void Cy_SMIF_SetReadyPollingDelay(uint16_t pollTimeoutUs,
966 cy_stc_smif_context_t *context);
967 cy_en_smif_status_t Cy_SMIF_MemCmdPowerDown(SMIF_Type *base,
968 cy_stc_smif_mem_config_t const *memDevice,
969 cy_stc_smif_context_t const *context);
970
971 cy_en_smif_status_t Cy_SMIF_MemCmdReleasePowerDown(SMIF_Type *base,
972 cy_stc_smif_mem_config_t const *memDevice,
973 cy_stc_smif_context_t const *context);
974
975 #if (CY_IP_MXSMIF_VERSION>=2)
976
977 /*******************************************************************************
978 * Function Name: Cy_SMIF_HyperBus_InitDevice
979 ****************************************************************************//**
980 *
981 * This function sets up SMIF registers for hyper bus memory.
982 *
983 * \param device
984 * Holds the base address of the SMIF Device registers.
985 *
986 * \param memCfg
987 * Configuration to be applied to the SMIF device \ref cy_stc_smif_mem_config_t
988 *
989 * \param context
990 * This is the pointer to the context structure \ref cy_stc_smif_context_t
991 * allocated by the user. The structure is used during the SMIF
992 * operation for internal configuration and data retention. The user must not
993 * modify anything in this structure.
994 *
995 * \return
996 * - \ref CY_SMIF_BAD_PARAM
997 * - \ref CY_SMIF_SUCCESS
998 *
999 * \snippet smif/snippet/main.c snippet_Cy_SMIF_HyperBus
1000 *
1001 *******************************************************************************/
1002 cy_en_smif_status_t Cy_SMIF_HyperBus_InitDevice(SMIF_Type *base, const cy_stc_smif_mem_config_t *memCfg, cy_stc_smif_context_t *context);
1003
1004 /*******************************************************************************
1005 * Function Name: Cy_SMIF_HyperBus_CalibrateDelay
1006 ****************************************************************************//**
1007 *
1008 * This function reads the calibration data pattern in the Hyper memory for every
1009 * delay tap of the currently selected delay line and records whether it matches
1010 * the reference pattern. After all taps have been scanned, it determines the
1011 * center tap of the longest sequence of matches and applies this tap.
1012 *
1013 * \note Function assumes that any SMIF has the same number of delay taps
1014 *
1015 * \param base
1016 * Holds the base address of the SMIF Device registers.
1017 *
1018 * \param memConfig
1019 * SMIF memory configuration structure for memory mode of operation.
1020 *
1021 * \param dummyCycles
1022 * Dummy Cycles based on Frequency of operation
1023 *
1024 * \param calibrationDataOffsetFromBase
1025 * Address offset of the calibration data from the device's XIP base address
1026 *
1027 * \param context
1028 * Current SMIF driver context
1029 *
1030 * \return \ref cy_en_smif_status_t
1031 *
1032 * \snippet smif/snippet/main.c snippet_Cy_SMIF_HyperBus
1033 *
1034 *******************************************************************************/
1035 cy_en_smif_status_t Cy_SMIF_HyperBus_CalibrateDelay(SMIF_Type *base, cy_stc_smif_mem_config_t *memConfig, uint8_t dummyCycles, uint32_t calibrationDataOffsetAddress, cy_stc_smif_context_t *context);
1036
1037 /*******************************************************************************
1038 * Function Cy_SMIF_HyperBus_Read
1039 ****************************************************************************//**
1040 *
1041 * This function reads data from hyper bus memory in MMIO mode.
1042 *
1043 * \param base
1044 * Holds the base address of the SMIF block registers.
1045 *
1046 * \param memConfig
1047 * SMIF memory configuration structure for memory mode of operation.
1048 *
1049 * \param burstType
1050 * Specifies wrapped or continuous burst. \ref en_hb_bust_type_t
1051 *
1052 * \param readAddress
1053 * Specifies address of external device to be read.
1054 *
1055 * \param sizeInHalfWord
1056 * Specifies memory size to be read.
1057 * Note hyper bus memory have 16bit data per each address.
1058 *
1059 * \param buf
1060 * Pointer to buffer where read data to be stored
1061 *
1062 * \param dummyCycles
1063 * Dummy Cycles based on Frequency of operation
1064 *
1065 * \param doubleLat
1066 * double initial latency or single initial latency
1067 *
1068 * \param isblockingMode
1069 * Blocking mode or not. if this is true, process waits for the read finished in this
1070 * function. unless, the process does not wait and exit function.
1071 *
1072 * \param context
1073 * Passes a configuration structure that contains the transfer parameters of the
1074 * SMIF block.
1075 *
1076 * \return \ref cy_en_smif_status_t
1077 *
1078 * \snippet smif/snippet/main.c snippet_Cy_SMIF_HyperBus
1079 *
1080 *******************************************************************************/
1081 cy_en_smif_status_t Cy_SMIF_HyperBus_Read(SMIF_Type *base,
1082 cy_stc_smif_mem_config_t *memConfig,
1083 cy_en_hb_burst_type_t burstType,
1084 uint32_t readAddress,
1085 uint32_t sizeInHalfWord,
1086 uint16_t buf[],
1087 uint32_t dummyCycles,
1088 bool doubleLat,
1089 bool isblockingMode,
1090 cy_stc_smif_context_t *context);
1091
1092 /*******************************************************************************
1093 * Function Cy_SMIF_HyperBus_Write
1094 ****************************************************************************//**
1095 *
1096 * This function writes data into hyper bus memory in MMIO mode.
1097 *
1098 * \param base
1099 * Holds the base address of the SMIF block registers.
1100 *
1101 * \param memConfig
1102 * SMIF memory configuration structure for memory mode of operation.
1103 *
1104 * \param burstType
1105 * Specifies wrapped or continuous burst. \ref en_hb_bust_type_t
1106 *
1107 * \param writeAddress
1108 * Specifies address of external device to be write.
1109 *
1110 * \param sizeInHalfWord
1111 * Specifies memory size to be read.
1112 * Note hyper bus memory have 16bit data per each address.
1113 *
1114 * \param buf
1115 * Pointer to buffer where read data to be stored
1116 *
1117 * \param hbDevType
1118 * Specifies hyper bus type. FLASH or SRAM. \ref cy_en_smif_hb_dev_type_t
1119 *
1120 * \param dummyCycles
1121 * Dummy Cycles based on Frequency of operation.
1122 *
1123 * \param isblockingMode
1124 * Blocking mode or not. if this is true, process waits for the read finished in this
1125 * function. unless, the process does not wait and exit function.
1126 *
1127 * \param context
1128 * Passes a configuration structure that contains the transfer parameters of the
1129 * SMIF block.
1130 *
1131 * \return \ref cy_en_smif_status_t
1132 *
1133 * \snippet smif/snippet/main.c snippet_Cy_SMIF_HyperBus
1134 *
1135 *******************************************************************************/
1136 cy_en_smif_status_t Cy_SMIF_HyperBus_Write(SMIF_Type *base,
1137 cy_stc_smif_mem_config_t *memConfig,
1138 cy_en_hb_burst_type_t burstType,
1139 uint32_t writeAddress,
1140 uint32_t sizeInHalfWord,
1141 uint16_t buf[],
1142 cy_en_smif_hb_dev_type_t hbDevType,
1143 uint32_t dummyCycles,
1144 bool isblockingMode,
1145 cy_stc_smif_context_t *context);
1146
1147 /*******************************************************************************
1148 * Function Name: CY_SMIF_HyperBus_ReadStatus
1149 ****************************************************************************//**
1150 *
1151 * This function reads the flash status register bits.
1152 *
1153 * \param base
1154 * Holds the base address of the SMIF block registers.
1155 *
1156 * \param memConfig
1157 * SMIF memory configuration structure for memory mode of operation.
1158 *
1159 * \param regStatus
1160 * output status register value.
1161 *
1162 * \return \ref cy_en_smif_status_t
1163 *
1164
1165 *******************************************************************************/
1166 cy_en_smif_status_t CY_SMIF_HyperBus_ReadStatus(SMIF_Type *base, cy_stc_smif_mem_config_t *memConfig, uint16_t *regStatus, cy_stc_smif_context_t *context);
1167
1168 /*******************************************************************************
1169 * Function Name: CY_SMIF_HyperBus_ClearStatus
1170 ****************************************************************************//**
1171 *
1172 * This function clears the flash status register bits.
1173 *
1174 * \param base
1175 * Holds the base address of the SMIF block registers.
1176 *
1177 * \param memConfig
1178 * SMIF memory configuration structure for memory mode of operation.
1179 *
1180 * \return \ref cy_en_smif_status_t
1181 *
1182 *******************************************************************************/
1183 cy_en_smif_status_t CY_SMIF_HyperBus_ClearStatus(SMIF_Type *base, cy_stc_smif_mem_config_t *memConfig, cy_stc_smif_context_t *context);
1184
1185 /*******************************************************************************
1186 * Function Name: Cy_SMIF_HyperBus_EraseSector
1187 ****************************************************************************//**
1188 *
1189 * This function Erases the data in the given sector.
1190 *
1191 * \param base
1192 * Holds the base address of the SMIF block registers.
1193 *
1194 * \param memConfig
1195 * SMIF memory configuration structure for memory mode of operation.
1196 *
1197 * \param offset
1198 * offset of the sector to be erased.
1199 *
1200 * \return \ref cy_en_smif_status_t
1201 *
1202 * \snippet smif/snippet/main.c snippet_Cy_SMIF_HyperBus
1203 *
1204 *******************************************************************************/
1205 cy_en_smif_status_t Cy_SMIF_HyperBus_EraseSector(SMIF_Type *base, cy_stc_smif_mem_config_t *memConfig, uint32_t offset, cy_stc_smif_context_t *context);
1206
1207 /*******************************************************************************
1208 * Function Name: Cy_SMIF_HyperBus_EraseChip
1209 ****************************************************************************//**
1210 *
1211 * This function Erases the data in the entire flash memory.
1212 *
1213 * \param base
1214 * Holds the base address of the SMIF block registers.
1215 *
1216 * \param memConfig
1217 * SMIF memory configuration structure for memory mode of operation.
1218 *
1219 * \return \ref cy_en_smif_status_t
1220 *
1221 *******************************************************************************/
1222 cy_en_smif_status_t Cy_SMIF_HyperBus_EraseChip(SMIF_Type *base, cy_stc_smif_mem_config_t *memConfig, cy_stc_smif_context_t *context);
1223
1224 #endif /* (CY_IP_MXSMIF_VERSION>=2) */
1225
1226 /** \} group_smif_mem_slot_functions */
1227
1228 __STATIC_INLINE void SfdpGetQuadEnableParameters(cy_stc_smif_mem_device_cfg_t *device,
1229 cy_en_smif_qer_t qerId);
1230 __STATIC_INLINE void XipRegInit(SMIF_DEVICE_Type volatile *dev, cy_stc_smif_mem_config_t const * memCfg);
1231
1232 __STATIC_INLINE cy_en_smif_status_t ReadAnyReg(SMIF_Type *base,
1233 cy_en_smif_slave_select_t slaveSelect,
1234 uint8_t *value,
1235 uint8_t command,
1236 uint8_t dummyCycles,
1237 uint8_t const *address,
1238 uint32_t addressSize,
1239 cy_stc_smif_context_t const *context);
1240 __STATIC_INLINE void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startPos, uint32_t size);
1241 __STATIC_INLINE uint32_t ByteArrayToValue(uint8_t const *byteArray, uint32_t size);
1242
1243 /*******************************************************************************
1244 * Function Name: SfdpGetQuadEnableParameters
1245 ****************************************************************************//**
1246 *
1247 * Gets the Quad Enable parameters.
1248 *
1249 * \param device
1250 * The device structure instance declared by the user. This is where the detected
1251 * parameters are stored and returned.
1252 *
1253 * \param qerId
1254 * quad enable requirement ID
1255 *
1256 *******************************************************************************/
SfdpGetQuadEnableParameters(cy_stc_smif_mem_device_cfg_t * device,cy_en_smif_qer_t qerId)1257 __STATIC_INLINE void SfdpGetQuadEnableParameters(cy_stc_smif_mem_device_cfg_t *device,
1258 cy_en_smif_qer_t qerId)
1259 {
1260 CY_ASSERT_L1(NULL != device->readStsRegQeCmd);
1261 CY_ASSERT_L1(NULL != device->writeStsRegQeCmd);
1262
1263 /* The command transfer width */
1264 device->writeStsRegQeCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE;
1265
1266 /* The QE mask for the status registers */
1267 switch (qerId)
1268 {
1269 case CY_SMIF_SFDP_QER_0:
1270 device->stsRegQuadEnableMask = CY_SMIF_NO_COMMAND_OR_MODE;
1271 device->writeStsRegQeCmd->command = CY_SMIF_NO_COMMAND_OR_MODE;
1272 device->readStsRegQeCmd->command = CY_SMIF_NO_COMMAND_OR_MODE;
1273 #if (CY_IP_MXSMIF_VERSION>=2)
1274 device->writeStsRegQeCmd->cmdPresence = CY_SMIF_NOT_PRESENT;
1275 device->readStsRegQeCmd->cmdPresence = CY_SMIF_NOT_PRESENT;
1276 #endif /* CY_IP_MXSMIF_VERSION */
1277 break;
1278 case CY_SMIF_SFDP_QER_1:
1279 case CY_SMIF_SFDP_QER_4:
1280 case CY_SMIF_SFDP_QER_5:
1281 device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_1_OF_SR_2;
1282
1283 /* The command to write into the QE-containing status register */
1284 /* The 8-bit command. QE WRSR */
1285 device->writeStsRegQeCmd->command = CY_SMIF_WRITE_STATUS_REG1_CMD;
1286 device->readStsRegQeCmd->command = CY_SMIF_READ_STATUS_REG2_T1_CMD;
1287 #if (CY_IP_MXSMIF_VERSION>=2)
1288 device->writeStsRegQeCmd->cmdPresence = CY_SMIF_PRESENT_1BYTE;
1289 device->readStsRegQeCmd->cmdPresence = CY_SMIF_PRESENT_1BYTE;
1290 #endif /* CY_IP_MXSMIF_VERSION */
1291 break;
1292 case CY_SMIF_SFDP_QER_2:
1293 device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_6_OF_SR_1;
1294
1295 /* The command to write into the QE-containing status register */
1296 /* The 8-bit command. QE WRSR */
1297 device->writeStsRegQeCmd->command = CY_SMIF_WRITE_STATUS_REG1_CMD;
1298 device->readStsRegQeCmd->command = CY_SMIF_READ_STATUS_REG1_CMD;
1299 #if (CY_IP_MXSMIF_VERSION>=2)
1300 device->writeStsRegQeCmd->cmdPresence = CY_SMIF_PRESENT_1BYTE;
1301 device->readStsRegQeCmd->cmdPresence = CY_SMIF_PRESENT_1BYTE;
1302 #endif /* CY_IP_MXSMIF_VERSION */
1303 break;
1304 case CY_SMIF_SFDP_QER_3:
1305 device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_7_OF_SR_2;
1306
1307 /* The command to write into the QE-containing status register */
1308 /* The 8-bit command. QE WRSR */
1309 device->writeStsRegQeCmd->command = CY_SMIF_WRITE_STATUS_REG2_T1_CMD;
1310 device->readStsRegQeCmd->command = CY_SMIF_READ_STATUS_REG2_T2_CMD;
1311 #if (CY_IP_MXSMIF_VERSION>=2)
1312 device->writeStsRegQeCmd->cmdPresence = CY_SMIF_PRESENT_1BYTE;
1313 device->readStsRegQeCmd->cmdPresence = CY_SMIF_PRESENT_1BYTE;
1314 #endif /* CY_IP_MXSMIF_VERSION */
1315 break;
1316 case CY_SMIF_SFDP_QER_6:
1317 device->stsRegQuadEnableMask = CY_SMIF_SFDP_QE_BIT_1_OF_SR_2;
1318
1319 /* The command to write into the QE-containing status register */
1320 /* The 8-bit command. QE WRSR */
1321 device->writeStsRegQeCmd->command = CY_SMIF_WRITE_STATUS_REG2_T2_CMD;
1322 device->readStsRegQeCmd->command = CY_SMIF_READ_STATUS_REG2_T1_CMD;
1323 #if (CY_IP_MXSMIF_VERSION>=2)
1324 device->writeStsRegQeCmd->cmdPresence = CY_SMIF_PRESENT_1BYTE;
1325 device->readStsRegQeCmd->cmdPresence = CY_SMIF_PRESENT_1BYTE;
1326 #endif /* CY_IP_MXSMIF_VERSION */
1327 break;
1328 default:
1329 /* Unsupported quad enable requirement */
1330 break;
1331 }
1332 }
1333
1334 /*******************************************************************************
1335 * Function Name: XipRegInit
1336 ****************************************************************************//**
1337 *
1338 * \internal
1339 * This function initializes the memory device registers used for the XIP mode of
1340 * the specified device.
1341 *
1342 * \param dev
1343 * The SMIF memory device registers structure. \ref SMIF_DEVICE_Type
1344 *
1345 * \param memCfg
1346 * The memory configuration structure that configures the SMIF memory device to
1347 * map into the PSoC memory map. \ref cy_stc_smif_mem_config_t
1348 *
1349 *******************************************************************************/
XipRegInit(SMIF_DEVICE_Type volatile * dev,cy_stc_smif_mem_config_t const * memCfg)1350 __STATIC_INLINE void XipRegInit(SMIF_DEVICE_Type volatile *dev, cy_stc_smif_mem_config_t const * memCfg)
1351 {
1352 cy_stc_smif_mem_device_cfg_t const * devCfg = memCfg->deviceCfg;
1353 cy_stc_smif_mem_cmd_t const * read = devCfg->readCmd;
1354 cy_stc_smif_mem_cmd_t const * prog = devCfg->programCmd;
1355
1356 SMIF_DEVICE_ADDR(dev) = (SMIF_DEVICE_ADDR_ADDR_Msk & memCfg->baseAddress);
1357
1358 /* Convert the size in the mask */
1359 SMIF_DEVICE_MASK(dev)= (SMIF_DEVICE_MASK_MASK_Msk & (~(memCfg->memMappedSize) + 1UL));
1360
1361 #if (CY_IP_MXSMIF_VERSION>=2)
1362 SMIF_DEVICE_ADDR_CTL(dev) = _VAL2FLD(SMIF_DEVICE_ADDR_CTL_SIZE3, (devCfg->numOfAddrBytes - 1UL)) |
1363 ((0UL != memCfg->dualQuadSlots)? SMIF_DEVICE_ADDR_CTL_DIV2_Msk: 0UL);
1364
1365 if((memCfg->flags & CY_SMIF_FLAG_SMIF_REV_3) != 0UL)
1366 {
1367 if(NULL != read)
1368 {
1369 SMIF_DEVICE_RD_CMD_CTL(dev) = (CY_SMIF_NO_COMMAND_OR_MODE != read->command) ?
1370 (_VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_CODE, (uint32_t)read->command) |
1371 _VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_CODEH, (uint32_t)read->commandH) |
1372 _VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_DDR_MODE, (uint32_t)read->cmdRate) |
1373 _VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_WIDTH, (uint32_t)read->cmdWidth) |
1374 _VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_PRESENT2, (uint32_t)read->cmdPresence))
1375 : 0U;
1376 SMIF_DEVICE_RD_ADDR_CTL(dev) = _VAL2FLD(SMIF_DEVICE_RD_ADDR_CTL_WIDTH, (uint32_t)read->addrWidth) |
1377 _VAL2FLD(SMIF_DEVICE_RD_ADDR_CTL_DDR_MODE, (uint32_t)read->addrRate);
1378
1379 SMIF_DEVICE_RD_MODE_CTL(dev) = (CY_SMIF_NO_COMMAND_OR_MODE != read->mode) ?
1380 (_VAL2FLD(SMIF_DEVICE_RD_MODE_CTL_CODE, (uint32_t)read->mode) |
1381 _VAL2FLD(SMIF_DEVICE_RD_MODE_CTL_CODEH, (uint32_t)read->modeH) |
1382 _VAL2FLD(SMIF_DEVICE_RD_MODE_CTL_WIDTH, (uint32_t)read->modeWidth) |
1383 _VAL2FLD(SMIF_DEVICE_RD_MODE_CTL_DDR_MODE, (uint32_t)read->modeRate) |
1384 _VAL2FLD(SMIF_DEVICE_RD_MODE_CTL_PRESENT2, read->modePresence))
1385 : 0U;
1386
1387 SMIF_DEVICE_RD_DUMMY_CTL(dev) = (0UL != read->dummyCycles)?
1388 (_VAL2FLD(SMIF_DEVICE_RD_DUMMY_CTL_SIZE5, (read->dummyCycles - 1UL)) |
1389 _VAL2FLD(SMIF_DEVICE_RD_DUMMY_CTL_PRESENT2,read->dummyCyclesPresence))
1390 : 0U;
1391
1392 SMIF_DEVICE_RD_DATA_CTL(dev) = _VAL2FLD(SMIF_DEVICE_RD_DATA_CTL_WIDTH, (uint32_t)read->dataWidth) |
1393 _VAL2FLD(SMIF_DEVICE_RD_DATA_CTL_DDR_MODE, (uint32_t)read->dataRate);
1394 }
1395
1396 if(NULL != prog)
1397 {
1398 SMIF_DEVICE_WR_CMD_CTL(dev) = (CY_SMIF_NO_COMMAND_OR_MODE != prog->command) ?
1399 _VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_CODE, (uint32_t)prog->command) |
1400 _VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_CODEH, (uint32_t)prog->commandH) |
1401 _VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_DDR_MODE, (uint32_t)prog->cmdRate) |
1402 _VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_WIDTH, (uint32_t)prog->cmdWidth) |
1403 _VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_PRESENT2, prog->cmdPresence)
1404 : 0U;
1405
1406 SMIF_DEVICE_WR_ADDR_CTL(dev) = _VAL2FLD(SMIF_DEVICE_WR_ADDR_CTL_WIDTH, (uint32_t)prog->addrWidth) |
1407 _VAL2FLD(SMIF_DEVICE_WR_ADDR_CTL_DDR_MODE, (uint32_t)prog->addrRate);
1408
1409 SMIF_DEVICE_WR_MODE_CTL(dev) = (CY_SMIF_NO_COMMAND_OR_MODE != prog->mode) ?
1410 _VAL2FLD(SMIF_DEVICE_WR_MODE_CTL_CODE, (uint32_t)prog->mode) |
1411 _VAL2FLD(SMIF_DEVICE_WR_MODE_CTL_CODEH, (uint32_t)prog->modeH) |
1412 _VAL2FLD(SMIF_DEVICE_WR_MODE_CTL_WIDTH, (uint32_t)prog->modeWidth) |
1413 _VAL2FLD(SMIF_DEVICE_WR_MODE_CTL_DDR_MODE, (uint32_t)prog->modeRate) |
1414 _VAL2FLD(SMIF_DEVICE_WR_MODE_CTL_PRESENT2, prog->modePresence)
1415 : 0UL;
1416
1417 SMIF_DEVICE_WR_DUMMY_CTL(dev) = (0UL != prog->dummyCycles) ?
1418 (_VAL2FLD(SMIF_DEVICE_WR_DUMMY_CTL_SIZE5, (prog->dummyCycles - 1UL)) |
1419 (_VAL2FLD(SMIF_DEVICE_WR_DUMMY_CTL_PRESENT2, prog->dummyCyclesPresence)))
1420 : 0U;
1421
1422 SMIF_DEVICE_WR_DATA_CTL(dev) = _VAL2FLD(SMIF_DEVICE_WR_DATA_CTL_WIDTH, (uint32_t)prog->dataWidth) |
1423 _VAL2FLD(SMIF_DEVICE_WR_DATA_CTL_DDR_MODE, (uint32_t)prog->dataRate);
1424 }
1425 }
1426 else
1427 {
1428 if(NULL != read)
1429 {
1430 SMIF_DEVICE_RD_CMD_CTL(dev) = (CY_SMIF_NO_COMMAND_OR_MODE != read->command) ?
1431 (_VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_CODE, (uint32_t)read->command) |
1432 _VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_WIDTH, (uint32_t)read->cmdWidth) |
1433 _VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_PRESENT2, 1UL))
1434 : 0U;
1435
1436 SMIF_DEVICE_RD_ADDR_CTL(dev) = _VAL2FLD(SMIF_DEVICE_RD_ADDR_CTL_WIDTH, (uint32_t)read->addrWidth);
1437
1438 SMIF_DEVICE_RD_MODE_CTL(dev) = (CY_SMIF_NO_COMMAND_OR_MODE != read->mode) ?
1439 (_VAL2FLD(SMIF_DEVICE_RD_MODE_CTL_CODE, (uint32_t)read->mode) |
1440 _VAL2FLD(SMIF_DEVICE_RD_MODE_CTL_WIDTH, (uint32_t)read->modeWidth)|
1441 _VAL2FLD(SMIF_DEVICE_RD_MODE_CTL_PRESENT2, 1UL))
1442 : 0U;
1443
1444 SMIF_DEVICE_RD_DUMMY_CTL(dev) = (0UL != read->dummyCycles)?
1445 (_VAL2FLD(SMIF_DEVICE_RD_DUMMY_CTL_SIZE5, (read->dummyCycles - 1UL)) |
1446 _VAL2FLD(SMIF_DEVICE_RD_DUMMY_CTL_PRESENT2, 1UL))
1447 : 0U;
1448
1449 SMIF_DEVICE_RD_DATA_CTL(dev) = _VAL2FLD(SMIF_DEVICE_RD_DATA_CTL_WIDTH, (uint32_t)read->dataWidth);
1450 }
1451
1452 if(NULL != prog)
1453 {
1454 SMIF_DEVICE_WR_CMD_CTL(dev) = (CY_SMIF_NO_COMMAND_OR_MODE != prog->command) ?
1455 (_VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_CODE, (uint32_t)prog->command) |
1456 _VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_WIDTH, (uint32_t)prog->cmdWidth)|
1457 _VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_PRESENT2, 1UL))
1458 : 0U;
1459
1460 SMIF_DEVICE_WR_ADDR_CTL(dev) = _VAL2FLD(SMIF_DEVICE_WR_ADDR_CTL_WIDTH, (uint32_t)prog->addrWidth);
1461
1462 SMIF_DEVICE_WR_MODE_CTL(dev) = (CY_SMIF_NO_COMMAND_OR_MODE != prog->mode) ?
1463 (_VAL2FLD(SMIF_DEVICE_WR_MODE_CTL_CODE, (uint32_t)prog->mode) |
1464 _VAL2FLD(SMIF_DEVICE_WR_MODE_CTL_WIDTH, (uint32_t)prog->modeWidth)|
1465 _VAL2FLD(SMIF_DEVICE_WR_MODE_CTL_PRESENT2, 1UL))
1466 : 0UL;
1467
1468 SMIF_DEVICE_WR_DUMMY_CTL(dev) = (0UL != prog->dummyCycles) ?
1469 (_VAL2FLD(SMIF_DEVICE_WR_DUMMY_CTL_SIZE5, (prog->dummyCycles - 1UL)) |
1470 (_VAL2FLD(SMIF_DEVICE_WR_DUMMY_CTL_PRESENT2, 1UL)))
1471 : 0U;
1472
1473 SMIF_DEVICE_WR_DATA_CTL(dev) = _VAL2FLD(SMIF_DEVICE_WR_DATA_CTL_WIDTH, (uint32_t)prog->dataWidth);
1474 }
1475 }
1476 #else
1477 SMIF_DEVICE_ADDR_CTL(dev) = _VAL2FLD(SMIF_DEVICE_ADDR_CTL_SIZE2, (devCfg->numOfAddrBytes - 1UL)) |
1478 ((0UL != memCfg->dualQuadSlots)? SMIF_DEVICE_ADDR_CTL_DIV2_Msk: 0UL);
1479
1480 if(NULL != read)
1481 {
1482 SMIF_DEVICE_RD_CMD_CTL(dev) = (CY_SMIF_NO_COMMAND_OR_MODE != read->command) ?
1483 (_VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_CODE, (uint32_t)read->command) |
1484 _VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_WIDTH, (uint32_t)read->cmdWidth) |
1485 SMIF_DEVICE_RD_CMD_CTL_PRESENT_Msk)
1486 : 0U;
1487
1488 SMIF_DEVICE_RD_ADDR_CTL(dev) = _VAL2FLD(SMIF_DEVICE_RD_ADDR_CTL_WIDTH, (uint32_t)read->addrWidth);
1489
1490 SMIF_DEVICE_RD_MODE_CTL(dev) = (CY_SMIF_NO_COMMAND_OR_MODE != read->mode) ?
1491 (_VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_CODE, (uint32_t)read->mode) |
1492 _VAL2FLD(SMIF_DEVICE_RD_CMD_CTL_WIDTH, (uint32_t)read->modeWidth)|
1493 SMIF_DEVICE_RD_CMD_CTL_PRESENT_Msk)
1494 : 0U;
1495
1496 SMIF_DEVICE_RD_DUMMY_CTL(dev) = (0UL != read->dummyCycles)?
1497 (_VAL2FLD(SMIF_DEVICE_RD_DUMMY_CTL_SIZE5, (read->dummyCycles - 1UL)) |
1498 SMIF_DEVICE_RD_DUMMY_CTL_PRESENT_Msk)
1499 : 0U;
1500
1501 SMIF_DEVICE_RD_DATA_CTL(dev) = _VAL2FLD(SMIF_DEVICE_RD_DATA_CTL_WIDTH, (uint32_t)read->dataWidth);
1502 }
1503
1504 if(NULL != prog)
1505 {
1506 SMIF_DEVICE_WR_CMD_CTL(dev) = (CY_SMIF_NO_COMMAND_OR_MODE != prog->command) ?
1507 (_VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_CODE, (uint32_t)prog->command) |
1508 _VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_WIDTH, (uint32_t)prog->cmdWidth)|
1509 SMIF_DEVICE_WR_CMD_CTL_PRESENT_Msk)
1510 : 0U;
1511
1512 SMIF_DEVICE_WR_ADDR_CTL(dev) = _VAL2FLD(SMIF_DEVICE_WR_ADDR_CTL_WIDTH, (uint32_t)prog->addrWidth);
1513
1514 SMIF_DEVICE_WR_MODE_CTL(dev) = (CY_SMIF_NO_COMMAND_OR_MODE != prog->mode) ?
1515 (_VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_CODE, (uint32_t)prog->mode) |
1516 _VAL2FLD(SMIF_DEVICE_WR_CMD_CTL_WIDTH, (uint32_t)prog->modeWidth)|
1517 SMIF_DEVICE_WR_CMD_CTL_PRESENT_Msk)
1518 : 0UL;
1519
1520 SMIF_DEVICE_WR_DUMMY_CTL(dev) = (0UL != prog->dummyCycles) ?
1521 (_VAL2FLD(SMIF_DEVICE_WR_DUMMY_CTL_SIZE5, (prog->dummyCycles - 1UL)) |
1522 SMIF_DEVICE_WR_DUMMY_CTL_PRESENT_Msk)
1523 : 0U;
1524
1525 SMIF_DEVICE_WR_DATA_CTL(dev) = _VAL2FLD(SMIF_DEVICE_WR_DATA_CTL_WIDTH, (uint32_t)prog->dataWidth);
1526 }
1527 #endif /* CY_IP_MXSMIF_VERSION */
1528 }
1529 /*******************************************************************************
1530 * Function Name: ReadAnyReg
1531 ****************************************************************************//**
1532 *
1533 * This function reads any registers by address. This function is a blocking
1534 * function, it will block the execution flow until the status register is read.
1535 *
1536 * \param base
1537 * Holds the base address of the SMIF block registers.
1538 *
1539 * \param slaveSelect
1540 * The slave select line for the device.
1541 *
1542 * \param value
1543 * The value of the register.
1544 *
1545 * \param command
1546 * The command required to read the status/configuration register.
1547 *
1548 * \param dummyCycles
1549 * Number of latency cycles to be issue after sending register address.
1550 *
1551 * \param address
1552 * The register address array.
1553 *
1554 * \param addressSize
1555 * The size of the address array.
1556 *
1557 * \param context
1558 * This is the pointer to the context structure \ref cy_stc_smif_context_t
1559 * allocated by the user. The structure is used during the SMIF
1560 * operation for internal configuration and data retention. The user must not
1561 * modify anything in this structure.
1562 *
1563 * \return A status of the command reception.
1564 * - \ref CY_SMIF_SUCCESS
1565 * - \ref CY_SMIF_CMD_FIFO_FULL
1566 * - \ref CY_SMIF_EXCEED_TIMEOUT
1567 * - \ref CY_SMIF_CMD_NOT_FOUND
1568 *
1569 *******************************************************************************/
ReadAnyReg(SMIF_Type * base,cy_en_smif_slave_select_t slaveSelect,uint8_t * value,uint8_t command,uint8_t dummyCycles,uint8_t const * address,uint32_t addressSize,cy_stc_smif_context_t const * context)1570 __STATIC_INLINE cy_en_smif_status_t ReadAnyReg(SMIF_Type *base,
1571 cy_en_smif_slave_select_t slaveSelect,
1572 uint8_t *value,
1573 uint8_t command,
1574 uint8_t dummyCycles,
1575 uint8_t const *address,
1576 uint32_t addressSize,
1577 cy_stc_smif_context_t const *context)
1578 {
1579 cy_en_smif_status_t result = CY_SMIF_CMD_NOT_FOUND;
1580
1581 /* Read the memory register */
1582 result = Cy_SMIF_TransmitCommand(base, command, CY_SMIF_WIDTH_SINGLE,
1583 address, addressSize,
1584 CY_SMIF_WIDTH_SINGLE, slaveSelect,
1585 CY_SMIF_TX_NOT_LAST_BYTE, context);
1586
1587 if ((CY_SMIF_SUCCESS == result) && (dummyCycles != 0U))
1588 {
1589 result = Cy_SMIF_SendDummyCycles(base, dummyCycles);
1590 }
1591
1592 if (CY_SMIF_SUCCESS == result)
1593 {
1594 result = Cy_SMIF_ReceiveDataBlocking( base, value,
1595 CY_SMIF_READ_ONE_BYTE, CY_SMIF_WIDTH_SINGLE, context);
1596 }
1597
1598 return(result);
1599 }
1600 /*******************************************************************************
1601 * Function Name: ValueToByteArray
1602 ****************************************************************************//**
1603 *
1604 * Unpacks 0-numBytes from a 4-byte value into the byte array byteArray.
1605 *
1606 * \param value
1607 * The 4-byte value to unpack.
1608 *
1609 * \param byteArray
1610 * The byte array to fill.
1611 *
1612 * \param startPos
1613 * The start position of the array to begin filling from.
1614 *
1615 * \param size
1616 * The size of the array.
1617 *
1618 *
1619 *******************************************************************************/
ValueToByteArray(uint32_t value,uint8_t * byteArray,uint32_t startPos,uint32_t size)1620 static void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startPos, uint32_t size)
1621 {
1622 do
1623 {
1624 size--;
1625 byteArray[size + startPos] = (uint8_t)(value & PARAM_ID_LSB_MASK);
1626 value >>= PARAM_ID_MSB_OFFSET; /* Shift to get the next byte */
1627 } while (size > 0U);
1628 }
1629
1630
1631 /*******************************************************************************
1632 * Function Name: ByteArrayToValue
1633 ****************************************************************************//**
1634 *
1635 * Packs the byte array into a single value.
1636 *
1637 * \param byteArray
1638 * The byte array to unpack.
1639 *
1640 * \param size
1641 * The size of the array.
1642 *
1643 * \return
1644 * The 4-byte value filled from the array.
1645 *
1646 *
1647 *******************************************************************************/
ByteArrayToValue(uint8_t const * byteArray,uint32_t size)1648 static uint32_t ByteArrayToValue(uint8_t const *byteArray, uint32_t size)
1649 {
1650 uint32_t value = 0UL;
1651 uint32_t idx = 0UL;
1652 for (idx = 0UL; idx < size; idx++)
1653 {
1654 value <<= 8;
1655 value |= ((uint32_t) byteArray[idx]);
1656 }
1657 return value;
1658 }
1659
1660 #if defined(__cplusplus)
1661 }
1662 #endif
1663
1664 #endif /* CY_IP_MXSMIF */
1665
1666 #endif /* (CY_SMIF_MEMORYSLOT_H) */
1667
1668
1669 /* [] END OF FILE */
1670
