1 /* 2 * Copyright (c) 2020 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file Header containing definitions for MCHP eSPI SAF 9 */ 10 11 #ifndef _SOC_ESPI_SAF_H_ 12 #define _SOC_ESPI_SAF_H_ 13 14 #include <stdint.h> 15 #include <zephyr/sys/util.h> 16 17 #define MCHP_SAF_MAX_FLASH_DEVICES 2U 18 19 /* 20 * SAF hardware state machine timings 21 * poll timeout is in 32KHz clock periods 22 * poll interval is in AHB clock(48MHz) units. 23 * suspend resume interval is in 32KHz clock periods. 24 * consecutive read timeout is in AHB clock periods. 25 * suspend check delay is in AHB clock(48MHz) periods. 26 */ 27 #define MCHP_SAF_FLASH_POLL_TIMEOUT 0x28000u 28 #define MCHP_SAF_FLASH_POLL_INTERVAL 0u 29 #define MCHP_SAF_FLASH_SUS_RSM_INTERVAL 8u 30 #define MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT 2u 31 #define MCHP_SAF_FLASH_SUS_CHK_DELAY 0u 32 33 /* Default SAF Map of eSPI TAG numbers to master numbers */ 34 #define MCHP_SAF_TAG_MAP0_DFLT 0x23221100u 35 #define MCHP_SAF_TAG_MAP1_DFLT 0x77677767u 36 #define MCHP_SAF_TAG_MAP2_DFLT 0x00000005u 37 38 /* 39 * Default QMSPI clock divider and chip select timing. 40 * QMSPI master clock is either 96 or 48 MHz depending upon 41 * Boot-ROM OTP configuration. 42 */ 43 #define MCHP_SAF_QMSPI_CLK_DIV 4u 44 45 /* SAF V2 implements dynamically changing the QMSPI clock 46 * divider for SPI read vs all other SPI commands. 47 */ 48 #define MCHP_SAF_CS_CLK_DIV(read, other) \ 49 (((uint32_t)(read) & 0xffffu) | (((uint32_t)(other) & 0xffffu) << 16)) 50 51 #define MCHP_SAF_CS0_CLK_DIV MCHP_SAF_CS_CLK_DIV(4, 4) 52 #define MCHP_SAF_CS1_CLK_DIV MCHP_SAF_CS_CLK_DIV(4, 4) 53 54 #define MCHP_SAF_QMSPI_CS_TIMING 0x03000101u 55 56 /* SAF QMSPI programming */ 57 58 #define MCHP_SAF_QMSPI_NUM_FLASH_DESCR 6u 59 #define MCHP_SAF_QMSPI_CS0_START_DESCR 0u 60 #define MCHP_SAF_QMSPI_CS1_START_DESCR \ 61 (MCHP_SAF_QMSPI_CS0_START_DESCR + MCHP_SAF_QMSPI_NUM_FLASH_DESCR) 62 63 /* SAF engine requires start indices of descriptor chains */ 64 #define MCHP_SAF_CM_EXIT_START_DESCR 12u 65 #define MCHP_SAF_CM_EXIT_LAST_DESCR 13u 66 #define MCHP_SAF_POLL_STS_START_DESCR 14u 67 #define MCHP_SAF_POLL_STS_END_DESCR 15u 68 #define MCHP_SAF_NUM_GENERIC_DESCR 4u 69 70 /* QMSPI descriptors 12-15 for all SPI flash devices */ 71 72 /* QMSPI descriptors 12-13 are exit continuous mode */ 73 #define MCHP_SAF_EXIT_CM_DESCR12 \ 74 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_ONES | \ 75 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 76 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 77 MCHP_QMSPI_C_XFR_UNITS_1 | \ 78 MCHP_QMSPI_C_NEXT_DESCR(13) | \ 79 MCHP_QMSPI_C_XFR_NUNITS(1)) 80 81 #define MCHP_SAF_EXIT_CM_DESCR13 \ 82 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \ 83 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \ 84 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \ 85 MCHP_QMSPI_C_XFR_UNITS_1 | \ 86 MCHP_QMSPI_C_NEXT_DESCR(0) | \ 87 MCHP_QMSPI_C_XFR_NUNITS(9) | \ 88 MCHP_QMSPI_C_DESCR_LAST) 89 90 #define MCHP_SAF_EXIT_CM_DUAL_DESCR12 \ 91 (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_ONES | \ 92 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 93 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 94 MCHP_QMSPI_C_XFR_UNITS_1 | \ 95 MCHP_QMSPI_C_NEXT_DESCR(13) | \ 96 MCHP_QMSPI_C_XFR_NUNITS(1)) 97 98 #define MCHP_SAF_EXIT_CM_DUAL_DESCR13 \ 99 (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS | \ 100 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \ 101 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \ 102 MCHP_QMSPI_C_XFR_UNITS_1 | \ 103 MCHP_QMSPI_C_NEXT_DESCR(0) | \ 104 MCHP_QMSPI_C_XFR_NUNITS(5) | \ 105 MCHP_QMSPI_C_DESCR_LAST) 106 107 /* 108 * QMSPI descriptors 14-15 are poll 16-bit flash status 109 * Transmit one byte opcode at 1X (no DMA). 110 * Receive two bytes at 1X (no DMA). 111 */ 112 #define MCHP_SAF_POLL_DESCR14 \ 113 (MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \ 114 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 115 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 116 MCHP_QMSPI_C_XFR_UNITS_1 | \ 117 MCHP_QMSPI_C_NEXT_DESCR(15) | \ 118 MCHP_QMSPI_C_XFR_NUNITS(1)) 119 120 #define MCHP_SAF_POLL_DESCR15 \ 121 (MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DIS | \ 122 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \ 123 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \ 124 MCHP_QMSPI_C_XFR_UNITS_1 | \ 125 MCHP_QMSPI_C_NEXT_DESCR(0) | \ 126 MCHP_QMSPI_C_XFR_NUNITS(2) | \ 127 MCHP_QMSPI_C_DESCR_LAST) 128 129 130 /* SAF Pre-fetch optimization mode */ 131 #define MCHP_SAF_PREFETCH_MODE MCHP_SAF_FL_CFG_MISC_PFOE_DFLT 132 133 #define MCHP_SAF_CFG_MISC_PREFETCH_EXPEDITED 0x03U 134 135 /* 136 * SAF Opcode 32-bit register value. 137 * Each byte contain a SPI flash 8-bit opcode. 138 * NOTE1: opcode value of 0 = flash does not support this operation 139 * NOTE2: 140 * SAF Opcode A 141 * op0 = SPI flash write-enable opcode 142 * op1 = SPI flash program/erase suspend opcode 143 * op2 = SPI flash program/erase resume opcode 144 * op3 = SPI flash read STATUS1 opcode 145 * SAF Opcode B 146 * op0 = SPI flash erase 4KB sector opcode 147 * op1 = SPI flash erase 32KB sector opcode 148 * op2 = SPI flash erase 64KB sector opcode 149 * op3 = SPI flash page program opcode 150 * SAF Opcode C 151 * op0 = SPI flash read 1-4-4 continuous mode opcode 152 * op1 = SPI flash op0 mode byte value for non-continuous mode 153 * op2 = SPI flash op0 mode byte value for continuous mode 154 * op3 = SPI flash read STATUS2 opcode 155 */ 156 #define MCHP_SAF_OPCODE_REG_VAL(op0, op1, op2, op3) \ 157 (((uint32_t)(op0)&0xffU) | (((uint32_t)(op1)&0xffU) << 8) | \ 158 (((uint32_t)(op2)&0xffU) << 16) | (((uint32_t)(op3)&0xffU) << 24)) 159 160 /* 161 * SAF Flash Config CS0/CS1 QMSPI descriptor indices register value 162 * e = First QMSPI descriptor index for enter continuous mode chain 163 * r = First QMSPI descriptor index for continuous mode read chain 164 * s = Index of QMSPI descriptor in continuous mode read chain that 165 * contains the data length field. 166 */ 167 #define MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(e, r, s) \ 168 (((uint32_t)(e)&0xfU) | (((uint32_t)(r)&0xfU) << 8) | \ 169 (((uint32_t)(s)&0xfU) << 12)) 170 171 /* W25Q128 SPI flash device connected size in bytes */ 172 #define MCHP_W25Q128_SIZE (16U * 1024U * 1024U) 173 174 /* 175 * Six QMSPI descriptors describe SPI flash opcode protocols. 176 * Example: W25Q128 177 */ 178 /* Continuous mode read: transmit-quad 24-bit address and mode byte */ 179 #define MCHP_W25Q128_CM_RD_D0 \ 180 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \ 181 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 182 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 183 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4)) 184 185 /* Continuous mode read: transmit-quad 4 dummy clocks with I/O tri-stated */ 186 #define MCHP_W25Q128_CM_RD_D1 \ 187 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \ 188 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 189 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 190 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(2)) 191 192 /* Continuous mode read: read N bytes */ 193 #define MCHP_W25Q128_CM_RD_D2 \ 194 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \ 195 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \ 196 MCHP_QMSPI_C_RX_LDMA_CH0 | MCHP_QMSPI_C_CLOSE | \ 197 MCHP_QMSPI_C_XFR_UNITS_1 | \ 198 MCHP_QMSPI_C_XFR_NUNITS(0) | MCHP_QMSPI_C_DESCR_LAST) 199 200 /* Continuous Mode: 24-bit address plus mode byte */ 201 #define MCHP_W25Q128_CM_RD_DUAL_D0 \ 202 (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DATA | \ 203 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 204 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 205 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4)) 206 207 /* Continuous mode read: read N bytes */ 208 #define MCHP_W25Q128_CM_RD_DUAL_D1 \ 209 (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS | \ 210 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \ 211 MCHP_QMSPI_C_RX_LDMA_CH0 | MCHP_QMSPI_C_CLOSE | \ 212 MCHP_QMSPI_C_XFR_UNITS_1 | \ 213 MCHP_QMSPI_C_XFR_NUNITS(0) | MCHP_QMSPI_C_DESCR_LAST) 214 215 /* Continuous mode Dual D2. Not used */ 216 #define MCHP_W25Q128_CM_RD_DUAL_D2 0 217 218 /* Enter Continuous mode: transmit-single CM quad read opcode */ 219 #define MCHP_W25Q128_ENTER_CM_D0 \ 220 (MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \ 221 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 222 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 223 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(1)) 224 225 /* Enter Continuous mode: transmit-quad 24-bit address and mode byte */ 226 #define MCHP_W25Q128_ENTER_CM_D1 \ 227 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \ 228 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 229 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 230 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4)) 231 232 /* Enter Continuous mode: read-quad 3 bytes */ 233 #define MCHP_W25Q128_ENTER_CM_D2 \ 234 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \ 235 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 236 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \ 237 MCHP_QMSPI_C_XFR_UNITS_1 | \ 238 MCHP_QMSPI_C_XFR_NUNITS(3) | MCHP_QMSPI_C_DESCR_LAST) 239 240 /* Enter Continuous mode: transmit-single CM dual read opcode */ 241 #define MCHP_W25Q128_ENTER_CM_DUAL_D0 \ 242 (MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \ 243 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 244 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 245 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(1)) 246 247 /* Enter Continuous mode: transmit-dual 24-bit address and mode byte */ 248 #define MCHP_W25Q128_ENTER_CM_DUAL_D1 \ 249 (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DATA | \ 250 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 251 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 252 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4)) 253 254 /* Enter Continuous mode: read-dual 3 bytes */ 255 #define MCHP_W25Q128_ENTER_CM_DUAL_D2 \ 256 (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS | \ 257 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 258 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \ 259 MCHP_QMSPI_C_XFR_UNITS_1 | \ 260 MCHP_QMSPI_C_XFR_NUNITS(3) | MCHP_QMSPI_C_DESCR_LAST) 261 262 #define MCHP_W25Q128_OPA MCHP_SAF_OPCODE_REG_VAL(0x06u, 0x75u, 0x7au, 0x05u) 263 #define MCHP_W25Q128_OPB MCHP_SAF_OPCODE_REG_VAL(0x20u, 0x52u, 0xd8u, 0x02u) 264 #define MCHP_W25Q128_OPC MCHP_SAF_OPCODE_REG_VAL(0xebu, 0xffu, 0xa5u, 0x35u) 265 #define MCHP_W25Q128_OPD MCHP_SAF_OPCODE_REG_VAL(0xb9u, 0xabu, 0u, 0u) 266 267 #define MCHP_W25Q128_DUAL_OPC MCHP_SAF_OPCODE_REG_VAL(0xbbu, 0xffu, 0xa5u, 0x35u) 268 269 /* W25Q128 STATUS2 bit[7] == 0 part is NOT in suspend state */ 270 #define MCHP_W25Q128_POLL2_MASK 0xff7fU 271 272 /* 273 * SAF Flash Continuous Mode Prefix register value 274 * b[7:0] = continuous mode prefix opcode 275 * b[15:8] = continuous mode prefix opcode data 276 * Some SPI flash devices require a prefix command before 277 * they will enter continuous mode. 278 * A zero value means the SPI flash does not require a prefix 279 * command. 280 */ 281 #define MCHP_W25Q128_CONT_MODE_PREFIX_VAL 0u 282 283 /* SAF Flash power down/up activity timeout in 32KHz units */ 284 #define MCHP_W25Q128_PD_TIMEOUT_32K 0x10u 285 286 /* SAF Flash minimum time between power up and down events in 287 * 48MHz time units (~20 ns) 288 */ 289 #define MCHP_W25Q128_PD_EVENT_INTERVAL 0x4ffu 290 291 #define MCHP_SAF_PD_EVENT_INTERVAL_25US 1279u 292 293 294 #define MCHP_W25Q128_FLAGS 0U 295 296 297 /* W25Q256 SPI flash device connected size in bytes */ 298 #define MCHP_W25Q256_SIZE (32U * 1024U * 1024U) 299 300 /* 301 * Six QMSPI descriptors describe SPI flash opcode protocols. 302 * W25Q256 device. 303 */ 304 305 /* Continuous Mode Read: Transmit-quad opcode plus 32-bit address */ 306 #define MCHP_W25Q256_CM_RD_D0 \ 307 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \ 308 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 309 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 310 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(5)) 311 312 #define MCHP_W25Q256_CM_RD_D1 \ 313 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \ 314 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 315 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 316 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(2)) 317 318 #define MCHP_W25Q256_CM_RD_D2 \ 319 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \ 320 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \ 321 MCHP_QMSPI_C_RX_LDMA_CH0 | MCHP_QMSPI_C_CLOSE | \ 322 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(0) | \ 323 MCHP_QMSPI_C_DESCR_LAST) 324 325 /* Enter Continuous mode: transmit-single CM quad read opcode */ 326 #define MCHP_W25Q256_ENTER_CM_D0 \ 327 (MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \ 328 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 329 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 330 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(1)) 331 332 /* Enter Continuous mode: transmit-quad 32-bit address and mode byte */ 333 #define MCHP_W25Q256_ENTER_CM_D1 \ 334 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \ 335 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 336 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 337 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(5)) 338 339 /* Enter Continuous mode: read-quad 3 bytes */ 340 #define MCHP_W25Q256_ENTER_CM_D2 \ 341 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \ 342 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 343 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \ 344 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(3) | \ 345 MCHP_QMSPI_C_DESCR_LAST) 346 347 #define MCHP_W25Q256_OPA MCHP_SAF_OPCODE_REG_VAL(0x06U, 0x75U, 0x7aU, 0x05U) 348 #define MCHP_W25Q256_OPB MCHP_SAF_OPCODE_REG_VAL(0x20U, 0x52U, 0xd8U, 0x02U) 349 #define MCHP_W25Q256_OPC MCHP_SAF_OPCODE_REG_VAL(0xebU, 0xffU, 0xa5U, 0x35U) 350 #define MCHP_W25Q256_OPD MCHP_SAF_OPCODE_REG_VAL(0xb9U, 0xabU, 0U, 0U) 351 352 #define MCHP_W25Q256_POLL2_MASK 0xff7fU 353 354 #define MCHP_W25Q256_CONT_MODE_PREFIX_VAL 0U 355 356 #define MCHP_W25Q256_FLAGS 0U 357 358 /* SAF Flash Config CS0 QMSPI descriptor indices */ 359 #define MCHP_CS0_CFG_DESCR_IDX_REG_VAL \ 360 MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(3U, 0U, 2U) 361 362 #define MCHP_CS0_CFG_DESCR_IDX_REG_VAL_DUAL \ 363 MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(3U, 0U, 1U) 364 365 /* SAF Flash Config CS1 QMSPI descriptor indices */ 366 #define MCHP_CS1_CFG_DESCR_IDX_REG_VAL \ 367 MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(9U, 6U, 8U) 368 369 #define MCHP_CS1_CFG_DESCR_IDX_REG_VAL_DUAL \ 370 MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(9U, 6U, 7U) 371 372 #define MCHP_SAF_HW_CFG_FLAG_FREQ 0x01U 373 #define MCHP_SAF_HW_CFG_FLAG_CSTM 0x02U 374 #define MCHP_SAF_HW_CFG_FLAG_CPHA 0x04U 375 376 /* enable SAF prefetch */ 377 #define MCHP_SAF_HW_CFG_FLAG_PFEN 0x10U 378 /* Use expedited prefetch instead of default */ 379 #define MCHP_SAF_HW_CFG_FLAG_PFEXP 0x20U 380 381 /* 382 * Override the default tag map value when this bit is set 383 * in a tag_map[]. 384 */ 385 #define MCHP_SAF_HW_CFG_TAGMAP_USE BIT(31) 386 387 #define MCHP_SAF_VER_1 0 388 #define MCHP_SAF_VER_2 1 389 390 struct espi_saf_hw_cfg { 391 uint8_t version; 392 uint8_t flags; 393 uint8_t rsvd1; 394 uint8_t qmspi_cpha; 395 uint32_t qmspi_cs_timing; 396 uint16_t flash_pd_timeout; 397 uint16_t flash_pd_min_interval; 398 uint32_t generic_descr[MCHP_SAF_NUM_GENERIC_DESCR]; 399 uint32_t tag_map[MCHP_ESPI_SAF_TAGMAP_MAX]; 400 }; 401 402 /* 403 * SAF local flash configuration. 404 * Version: 0 = V1, 1 = V2(this version) 405 * miscellaneous configuration flags 406 * SPI flash device size in bytes 407 * SPI opcodes for SAF Opcode A register 408 * SPI opcodes for SAF Opcode B register 409 * SPI opcodes for SAF Opcode C register 410 * SPI opcodes for SAF Opcode D register: power down/up and 411 * RPMC continuous mode read 412 * SAF controller Poll2 Mask value specific for this flash device 413 * SAF continuous mode prefix register value for those flashes requiring 414 * a prefix byte transmitted before the enter continuous mode command. 415 * Start QMSPI descriptor numbers. 416 * Power down timeout count in units of 32 KHz ticks. 417 * Minimum interval between power down/up commands in 48 MHz units. 418 * QMSPI descriptors describing SPI opcode transmit and data read. 419 */ 420 421 /* Flags */ 422 #define MCHP_FLASH_FLAG_ADDR32 BIT(0) 423 #define MCHP_FLASH_FLAG_V1_MSK 0xffu 424 #define MCHP_FLASH_FLAG_V2_MSK 0xff00u 425 #define MCHP_FLASH_FLAG_V2_PD_CS0_EN BIT(8) 426 #define MCHP_FLASH_FLAG_V2_PD_CS1_EN BIT(9) 427 #define MCHP_FLASH_FLAG_V2_PD_CS0_EC_WK_EN BIT(10) 428 #define MCHP_FLASH_FLAG_V2_PD_CS1_EC_WK_EN BIT(11) 429 430 struct espi_saf_flash_cfg { 431 uint8_t version; 432 uint8_t rsvd1; 433 uint16_t flags; 434 uint32_t flashsz; 435 uint8_t rd_freq_mhz; 436 uint8_t freq_mhz; 437 uint8_t rsvd2[2]; 438 uint32_t opa; 439 uint32_t opb; 440 uint32_t opc; 441 uint32_t opd; 442 uint16_t poll2_mask; 443 uint16_t cont_prefix; 444 uint16_t cs_cfg_descr_ids; 445 uint16_t rsvd3; 446 uint32_t descr[MCHP_SAF_QMSPI_NUM_FLASH_DESCR]; 447 }; 448 449 450 /* 451 * 17 flash protection regions 452 * Each region is described by: 453 * SPI start address. 20-bits = bits[31:12] of SPI address 454 * SPI limit address. 20-bits = bits[31:12] of last SPI address 455 * 8-bit bit map of eSPI master write-erase permission 456 * 8-bit bit map of eSPI maste read permission 457 * eSPI master numbers 0 - 7 correspond to bits 0 - 7. 458 * 459 * Protection region lock: 460 * One 32-bit register with bits[16:0] -> protection regions 16:0 461 * 462 * eSPI Host maps threads by a tag number to master numbers. 463 * Thread numbers are 4-bit 464 * Master numbers are 3-bit 465 * Master number Thread numbers Description 466 * 0 0h, 1h Host PCH HW init 467 * 1 2h, 3h Host CPU access(HW/BIOS/SMM/SW) 468 * 2 4h, 5h Host PCH ME 469 * 3 6h Host PCH LAN 470 * 4 N/A Not defined/used 471 * 5 N/A EC Firmware portal access 472 * 6 9h, Dh Host PCH IE 473 * 7 N/A Not defined/used 474 * 475 * NOTE: eSPI SAF specification allows master 0 (Host PCH HW) full 476 * access to all protection regions. 477 * 478 * SAF TAG Map registers 0 - 2 map eSPI TAG values 0h - Fh to 479 * the three bit master number. Each 32-bit register contains 3-bit 480 * fields aligned on nibble boundaries holding the master number 481 * associated with the eSPI tag (thread) number. 482 * A master value of 7h in a field indicates a non-existent map entry. 483 * 484 * bit map of registers to program 485 * b[2:0] = TAG Map[2:0] 486 * b[20:4] = ProtectionRegions[16:0] 487 * bit map of PR's to lock 488 * b[20:4] = ProtectionRegions[16:0] 489 * 490 */ 491 #define MCHP_SAF_PR_FLAG_ENABLE 0x01U 492 #define MCHP_SAF_PR_FLAG_LOCK 0x02U 493 494 #define MCHP_SAF_MSTR_HOST_PCH 0U 495 #define MCHP_SAF_MSTR_HOST_CPU 1U 496 #define MCHP_SAF_MSTR_HOST_PCH_ME 2U 497 #define MCHP_SAF_MSTR_HOST_PCH_LAN 3U 498 #define MCHP_SAF_MSTR_RSVD4 4U 499 #define MCHP_SAF_MSTR_EC 5U 500 #define MCHP_SAF_MSTR_HOST_PCH_IE 6U 501 502 struct espi_saf_pr { 503 uint32_t start; 504 uint32_t size; 505 uint8_t master_bm_we; 506 uint8_t master_bm_rd; 507 uint8_t pr_num; 508 uint8_t flags; /* bit[0]==1 is lock the region */ 509 }; 510 511 struct espi_saf_protection { 512 size_t nregions; 513 const struct espi_saf_pr *pregions; 514 }; 515 516 #endif /* _SOC_ESPI_SAF_H_ */ 517
