1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #pragma once 15 16 #include <stdbool.h> 17 #include <stddef.h> 18 #include <stdint.h> 19 #include "soc/soc.h" 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 /** 26 * @file rtc.h 27 * @brief Low-level RTC power, clock, and sleep functions. 28 * 29 * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral. 30 * RTC_CNTL peripheral handles many functions: 31 * - enables/disables clocks and power to various parts of the chip; this is 32 * done using direct register access (forcing power up or power down) or by 33 * allowing state machines to control power and clocks automatically 34 * - handles sleep and wakeup functions 35 * - maintains a 48-bit counter which can be used for timekeeping 36 * 37 * These functions are not thread safe, and should not be viewed as high level 38 * APIs. For example, while this file provides a function which can switch 39 * CPU frequency, this function is on its own is not sufficient to implement 40 * frequency switching in ESP-IDF context: some coordination with RTOS, 41 * peripheral drivers, and WiFi/BT stacks is also required. 42 * 43 * These functions will normally not be used in applications directly. 44 * ESP-IDF provides, or will provide, drivers and other facilities to use 45 * RTC subsystem functionality. 46 * 47 * The functions are loosely split into the following groups: 48 * - rtc_clk: clock switching, calibration 49 * - rtc_time: reading RTC counter, conversion between counter values and time 50 * - rtc_sleep: entry into sleep modes 51 * - rtc_init: initialization 52 */ 53 54 #define MHZ (1000000) 55 56 #define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) 57 #define RTC_SLOW_CLK_RC32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) 58 #define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) 59 60 #define RTC_SLOW_CLK_FREQ_150K 130000 61 #define RTC_SLOW_CLK_FREQ_32K 32768 62 #define RTC_SLOW_CLK_FREQ_RC32 32768 63 64 #define OTHER_BLOCKS_POWERUP 1 65 #define OTHER_BLOCKS_WAIT 1 66 67 /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, 68 * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. 69 * Valid if RTC_CNTL_DBG_ATTEN is 0. 70 */ 71 #define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias 72 #define RTC_CNTL_DBIAS_1V00 0 73 #define RTC_CNTL_DBIAS_1V05 4 74 #define RTC_CNTL_DBIAS_1V10 5 75 #define RTC_CNTL_DBIAS_1V15 6 76 #define RTC_CNTL_DBIAS_1V20 7 77 #define RTC_CNTL_DBIAS_DEFAULT 8 78 /* The value of 1V00 can be adjusted between 0~3*/ 79 80 81 /* dcdc mode 82 */ 83 #define RTC_CNTL_DCDC_TRX_MODE 0b100 84 #define RTC_CNTL_DCDC_LSLP_MODE 0b110 85 #define RTC_CNTL_DCDC_DSLP_MODE 0b101 86 #define RTC_CNTL_DCDC_FREQ_DEFAULT 3 87 88 #define DCDC_SLP_TRX_MODE 0 89 #define DCDC_SLP_LSLP_MODE 1 90 #define DCDC_SLP_DSLP_MODE 2 91 92 #define RTC_CNTL_DIG_DBIAS_0V85 0 93 #define RTC_CNTL_DIG_DBIAS_0V90 1 94 #define RTC_CNTL_DIG_DBIAS_0V95 2 95 #define RTC_CNTL_DIG_DBIAS_1V00 3 96 #define RTC_CNTL_DIG_DBIAS_1V05 4 97 #define RTC_CNTL_DIG_DBIAS_1V10 5 98 #define RTC_CNTL_DIG_DBIAS_1V15 6 99 #define RTC_CNTL_DIG_DBIAS_1V20 7 100 101 #define DELAY_FAST_CLK_SWITCH 3 102 #define DELAY_SLOW_CLK_SWITCH 300 103 #define DELAY_8M_ENABLE 50 104 105 /* Number of 8M/256 clock cycles to use for XTAL frequency estimation. 106 * 10 cycles will take approximately 300 microseconds. 107 */ 108 #define XTAL_FREQ_EST_CYCLES 10 109 110 #define DIG_DBIAS_80M RTC_CNTL_DBIAS_1V20 111 #define DIG_DBIAS_160M RTC_CNTL_DBIAS_1V20 112 113 #define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 114 #define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 115 116 #define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 117 #define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 118 #define RTC_CNTL_CK8M_WAIT_DEFAULT 20 119 #define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 120 121 #define RTC_CNTL_CK8M_DFREQ_DEFAULT 600 122 #define RTC_CNTL_SCK_DCAP_DEFAULT 128 123 #define RTC_CNTL_RC32K_DFREQ_DEFAULT 707 124 125 126 /* Various delays to be programmed into power control state machines */ 127 #define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) 128 #define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) 129 #define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) 130 #define RTC_CNTL_WAKEUP_DELAY_CYCLES (5) 131 #define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) 132 #define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) 133 134 /* 135 set sleep_init default param 136 */ 137 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 3 138 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 139 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 140 #define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 141 #define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 142 #define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 143 #define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 144 #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 145 #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254 146 147 /** 148 * @brief Possible main XTAL frequency values. 149 * 150 * Enum values should be equal to frequency in MHz. 151 */ 152 typedef enum { 153 RTC_XTAL_FREQ_32M = 32, 154 RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL 155 } rtc_xtal_freq_t; 156 157 /** 158 * @brief CPU clock source 159 */ 160 typedef enum { 161 RTC_CPU_FREQ_SRC_XTAL, //!< XTAL 162 RTC_CPU_FREQ_SRC_PLL, //!< PLL (96M) 163 RTC_CPU_FREQ_SRC_8M, //!< Internal 18M RTC oscillator 164 RTC_CPU_FREQ_SRC_XTAL_D2 //!< XTAL/2 165 } rtc_cpu_freq_src_t; 166 167 /** 168 * @brief CPU clock configuration structure 169 */ 170 typedef struct rtc_cpu_freq_config_s { 171 rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived 172 uint32_t source_freq_mhz; //!< Source clock frequency 173 uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div 174 uint32_t freq_mhz; //!< CPU clock frequency 175 } rtc_cpu_freq_config_t; 176 177 /** 178 * @brief RTC SLOW_CLK frequency values 179 */ 180 typedef enum { 181 RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator 182 RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL 183 RTC_SLOW_FREQ_RC32K = 2, //!< Internal 32 KHz RC oscillator 184 } rtc_slow_freq_t; 185 186 /** 187 * @brief RTC FAST_CLK frequency values 188 */ 189 typedef enum { 190 RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4 191 RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator 192 } rtc_fast_freq_t; 193 194 /* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */ 195 #define RTC_FAST_CLK_FREQ_APPROX 8500000 196 197 #define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal 198 199 #define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO 200 #define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO 201 202 /** 203 * @brief Clock source to be calibrated using rtc_clk_cal function 204 */ 205 typedef enum { 206 RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK 207 RTC_CAL_RC32K = 1, //!< Internal 32 kHz RC oscillator 208 RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL 209 } rtc_cal_sel_t; 210 211 /** 212 * Initialization parameters for rtc_clk_init 213 */ 214 typedef struct { 215 rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency 216 uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz 217 rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set 218 rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set 219 uint32_t clk_rtc_clk_div : 8; 220 uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) 221 uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) 222 uint32_t clk_8m_dfreq : 10; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) 223 uint32_t root_clk_slt : 2; //!< Select clock root source for esp32h2 (default 0: xtal_32M) 224 } rtc_clk_config_t; 225 226 /** 227 * Default initializer for rtc_clk_config_t 228 */ 229 #define RTC_CLK_CONFIG_DEFAULT() { \ 230 .xtal_freq = RTC_XTAL_FREQ_32M, \ 231 .cpu_freq_mhz = 32, \ 232 .fast_freq = RTC_FAST_FREQ_8M, \ 233 .slow_freq = RTC_SLOW_FREQ_RTC, \ 234 .clk_rtc_clk_div = 1, \ 235 .clk_8m_clk_div = 1, \ 236 .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ 237 .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ 238 .root_clk_slt = 0, \ 239 } 240 241 typedef struct { 242 uint32_t dac : 6; 243 uint32_t dres : 3; 244 uint32_t dgm : 3; 245 uint32_t dbuf: 1; 246 } x32k_config_t; 247 248 249 #define X32K_CONFIG_DEFAULT() { \ 250 .dac = 3, \ 251 .dres = 3, \ 252 .dgm = 3, \ 253 .dbuf = 1, \ 254 } 255 256 typedef struct { 257 uint32_t dfreq : 10; 258 } rc32k_config_t; 259 260 #define RC32K_CONFIG_DEFAULT() {\ 261 .dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT,\ 262 } 263 264 typedef struct { 265 uint16_t wifi_powerup_cycles : 7; 266 uint16_t wifi_wait_cycles : 9; 267 uint16_t bt_powerup_cycles : 7; 268 uint16_t bt_wait_cycles : 9; 269 uint16_t cpu_top_powerup_cycles : 7; 270 uint16_t cpu_top_wait_cycles : 9; 271 uint16_t dg_wrap_powerup_cycles : 7; 272 uint16_t dg_wrap_wait_cycles : 9; 273 uint16_t dg_peri_powerup_cycles : 7; 274 uint16_t dg_peri_wait_cycles : 9; 275 } rtc_init_config_t; 276 277 #define RTC_INIT_CONFIG_DEFAULT() { \ 278 .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \ 279 .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \ 280 .bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \ 281 .bt_wait_cycles = OTHER_BLOCKS_WAIT, \ 282 .cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \ 283 .cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \ 284 .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \ 285 .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \ 286 .dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \ 287 .dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \ 288 } 289 290 void rtc_clk_divider_set(uint32_t div); 291 292 void rtc_clk_8m_divider_set(uint32_t div); 293 294 /** 295 * Initialize clocks and set CPU frequency 296 * 297 * @param cfg clock configuration as rtc_clk_config_t 298 */ 299 void rtc_clk_init(rtc_clk_config_t cfg); 300 301 /** 302 * @brief Get main XTAL frequency 303 * 304 * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to 305 * rtc_clk_init function 306 * 307 * @return XTAL frequency, one of rtc_xtal_freq_t 308 */ 309 rtc_xtal_freq_t rtc_clk_xtal_freq_get(void); 310 311 /** 312 * @brief Update XTAL frequency 313 * 314 * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored 315 * after startup. 316 * 317 * @param xtal_freq New frequency value 318 */ 319 void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq); 320 321 /** 322 * @brief Enable or disable 32 kHz XTAL oscillator 323 * @param en true to enable, false to disable 324 */ 325 void rtc_clk_32k_enable(bool en); 326 327 /** 328 * @brief Configure 32 kHz XTAL oscillator to accept external clock signal 329 */ 330 void rtc_clk_32k_enable_external(void); 331 332 /** 333 * @brief Get the state of 32k XTAL oscillator 334 * @return true if 32k XTAL oscillator has been enabled 335 */ 336 bool rtc_clk_32k_enabled(void); 337 338 /** 339 * @brief Enable 32k oscillator, configuring it for fast startup time. 340 * Note: to achieve higher frequency stability, rtc_clk_32k_enable function 341 * must be called one the 32k XTAL oscillator has started up. This function 342 * will initially disable the 32k XTAL oscillator, so it should not be called 343 * when the system is using 32k XTAL as RTC_SLOW_CLK. 344 * 345 * @param cycle Number of 32kHz cycles to bootstrap external crystal. 346 * If 0, no square wave will be used to bootstrap crystal oscillation. 347 */ 348 void rtc_clk_32k_bootstrap(uint32_t cycle); 349 350 /** 351 * @brief Enable or disable 8 MHz internal oscillator 352 * 353 * Output from 8 MHz internal oscillator is passed into a configurable 354 * divider, which by default divides the input clock frequency by 256. 355 * Output of the divider may be used as RTC_SLOW_CLK source. 356 * Output of the divider is referred to in register descriptions and code as 357 * 8md256 or simply d256. Divider values other than 256 may be configured, but 358 * this facility is not currently needed, so is not exposed in the code. 359 * 360 * When 8MHz/256 divided output is not needed, the divider should be disabled 361 * to reduce power consumption. 362 * 363 * @param clk_8m_en true to enable 8MHz generator 364 * @param d256_en true to enable /256 divider 365 */ 366 void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en); 367 368 /** 369 * @brief Get the state of 8 MHz internal oscillator 370 * @return true if the oscillator is enabled 371 */ 372 bool rtc_clk_8m_enabled(void); 373 374 /** 375 * @brief Get the state of /256 divider which is applied to 8MHz clock 376 * @return true if the divided output is enabled 377 */ 378 bool rtc_clk_8md256_enabled(void); 379 380 /** 381 * @brief Enable or disable APLL 382 * 383 * Output frequency is given by the formula: 384 * apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2) 385 * 386 * The dividend in this expression should be in the range of 240 - 600 MHz. 387 * 388 * In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0. 389 * 390 * @param enable true to enable, false to disable 391 * @param sdm0 frequency adjustment parameter, 0..255 392 * @param sdm1 frequency adjustment parameter, 0..255 393 * @param sdm2 frequency adjustment parameter, 0..63 394 * @param o_div frequency divider, 0..31 395 */ 396 void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div); 397 398 /** 399 * @brief Select source for RTC_SLOW_CLK 400 * @param slow_freq clock source (one of rtc_slow_freq_t values) 401 */ 402 void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq); 403 404 /** 405 * @brief Get the RTC_SLOW_CLK source 406 * @return currently selected clock source (one of rtc_slow_freq_t values) 407 */ 408 rtc_slow_freq_t rtc_clk_slow_freq_get(void); 409 410 /** 411 * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz 412 * 413 * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000 414 * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768 415 * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000 416 * 417 * rtc_clk_cal function can be used to get more precise value by comparing 418 * RTC_SLOW_CLK frequency to the frequency of main XTAL. 419 * 420 * @return RTC_SLOW_CLK frequency, in Hz 421 */ 422 uint32_t rtc_clk_slow_freq_get_hz(void); 423 424 /** 425 * @brief Select source for RTC_FAST_CLK 426 * @param fast_freq clock source (one of rtc_fast_freq_t values) 427 */ 428 void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq); 429 430 /** 431 * @brief Get the RTC_FAST_CLK source 432 * @return currently selected clock source (one of rtc_fast_freq_t values) 433 */ 434 rtc_fast_freq_t rtc_clk_fast_freq_get(void); 435 436 /** 437 * @brief Get CPU frequency config for a given frequency 438 * @param freq_mhz Frequency in MHz 439 * @param[out] out_config Output, CPU frequency configuration structure 440 * @return true if frequency can be obtained, false otherwise 441 */ 442 bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config); 443 444 /** 445 * @brief Switch CPU frequency 446 * 447 * This function sets CPU frequency according to the given configuration 448 * structure. It enables PLLs, if necessary. 449 * 450 * @note This function in not intended to be called by applications in FreeRTOS 451 * environment. This is because it does not adjust various timers based on the 452 * new CPU frequency. 453 * 454 * @param config CPU frequency configuration structure 455 */ 456 void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config); 457 458 /** 459 * @brief Switch CPU frequency (optimized for speed) 460 * 461 * This function is a faster equivalent of rtc_clk_cpu_freq_set_config. 462 * It works faster because it does not disable PLLs when switching from PLL to 463 * XTAL and does not enabled them when switching back. If PLL is not already 464 * enabled when this function is called to switch from XTAL to PLL frequency, 465 * or the PLL which is enabled is the wrong one, this function will fall back 466 * to calling rtc_clk_cpu_freq_set_config. 467 * 468 * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data, 469 * so it is less safe to use it e.g. from a panic handler (when memory might 470 * be corrupted). 471 * 472 * @note This function in not intended to be called by applications in FreeRTOS 473 * environment. This is because it does not adjust various timers based on the 474 * new CPU frequency. 475 * 476 * @param config CPU frequency configuration structure 477 */ 478 void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config); 479 480 /** 481 * @brief Get the currently used CPU frequency configuration 482 * @param[out] out_config Output, CPU frequency configuration structure 483 */ 484 void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); 485 486 /** 487 * @brief Switch CPU clock source to XTAL 488 * 489 * Short form for filling in rtc_cpu_freq_config_t structure and calling 490 * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. 491 * Assumes that XTAL frequency has been determined — don't call in startup code. 492 */ 493 void rtc_clk_cpu_freq_set_xtal(void); 494 495 /** 496 * @brief Store new APB frequency value into RTC_APB_FREQ_REG 497 * 498 * This function doesn't change any hardware clocks. 499 * 500 * Functions which perform frequency switching and change APB frequency call 501 * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG 502 * (one of RTC general purpose retention registers). This should not normally 503 * be called from application code. 504 * 505 * @param apb_freq new APB frequency, in Hz 506 */ 507 void rtc_clk_apb_freq_update(uint32_t apb_freq); 508 509 /** 510 * @brief Get the current stored APB frequency. 511 * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz. 512 */ 513 uint32_t rtc_clk_apb_freq_get(void); 514 515 void rtc_clk_cpu_freq_set(uint32_t source, uint32_t div); 516 uint32_t rtc_clk_ahb_freq_get(void); 517 518 519 uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); 520 521 /** 522 * @brief Measure RTC slow clock's period, based on main XTAL frequency 523 * 524 * This function will time out and return 0 if the time for the given number 525 * of cycles to be counted exceeds the expected time twice. This may happen if 526 * 32k XTAL is being calibrated, but the oscillator has not started up (due to 527 * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). 528 * 529 * @param cal_clk clock to be measured 530 * @param slow_clk_cycles number of slow clock cycles to average 531 * @return average slow clock period in microseconds, Q13.19 fixed point format, 532 * or 0 if calibration has timed out 533 */ 534 uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); 535 536 /** 537 * @brief Measure ratio between XTAL frequency and RTC slow clock frequency 538 * @param cal_clk slow clock to be measured 539 * @param slow_clk_cycles number of slow clock cycles to average 540 * @return average ratio between XTAL frequency and slow clock frequency, 541 * Q13.19 fixed point format, or 0 if calibration has timed out. 542 */ 543 uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); 544 545 /** 546 * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles 547 * @param time_in_us Time interval in microseconds 548 * @param slow_clk_period Period of slow clock in microseconds, Q13.19 549 * fixed point format (as returned by rtc_slowck_cali). 550 * @return number of slow clock cycles 551 */ 552 uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); 553 554 /** 555 * @brief Convert time interval from RTC_SLOW_CLK to microseconds 556 * @param time_in_us Time interval in RTC_SLOW_CLK cycles 557 * @param slow_clk_period Period of slow clock in microseconds, Q13.19 558 * fixed point format (as returned by rtc_slowck_cali). 559 * @return time interval in microseconds 560 */ 561 uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); 562 563 /** 564 * @brief Get current value of RTC counter 565 * 566 * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK 567 * cycles. Counter value is not writable by software. The value is not adjusted 568 * when switching to a different RTC_SLOW_CLK source. 569 * 570 * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute 571 * 572 * @return current value of RTC counter 573 */ 574 uint64_t rtc_time_get(void); 575 576 uint64_t rtc_light_slp_time_get(void); 577 578 uint64_t rtc_deep_slp_time_get(void); 579 580 /** 581 * @brief Busy loop until next RTC_SLOW_CLK cycle 582 * 583 * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. 584 * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return 585 * one RTC_SLOW_CLK cycle later. 586 */ 587 void rtc_clk_wait_for_slow_cycle(void); 588 589 /** 590 * @brief Enable the rtc digital 8M clock 591 * 592 * This function is used to enable the digital rtc 8M clock to support peripherals. 593 * For enabling the analog 8M clock, using `rtc_clk_8M_enable` function above. 594 */ 595 void rtc_dig_clk8m_enable(void); 596 597 /** 598 * @brief Disable the rtc digital 8M clock 599 * 600 * This function is used to disable the digital rtc 8M clock, which is only used to support peripherals. 601 */ 602 void rtc_dig_clk8m_disable(void); 603 604 /** 605 * @brief Calculate the real clock value after the clock calibration 606 * 607 * @param cal_val Average slow clock period in microseconds, fixed point value as returned from `rtc_clk_cal` 608 * @return Frequency of the clock in Hz 609 */ 610 uint32_t rtc_clk_freq_cal(uint32_t cal_val); 611 612 /** 613 * @brief Power down flags for rtc_sleep_pd function 614 */ 615 typedef struct { 616 uint32_t dig_fpu : 1; //!< Set to 1 to power UP digital part in sleep 617 uint32_t rtc_fpu : 1; //!< Set to 1 to power UP RTC memories in sleep 618 uint32_t cpu_fpu : 1; //!< Set to 1 to power UP digital memories and CPU in sleep 619 uint32_t i2s_fpu : 1; //!< Set to 1 to power UP I2S in sleep 620 uint32_t bb_fpu : 1; //!< Set to 1 to power UP WiFi in sleep 621 uint32_t nrx_fpu : 1; //!< Set to 1 to power UP WiFi in sleep 622 uint32_t fe_fpu : 1; //!< Set to 1 to power UP WiFi in sleep 623 uint32_t sram_fpu : 1; //!< Set to 1 to power UP SRAM in sleep 624 uint32_t rom_ram_fpu : 1; //!< Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep 625 } rtc_sleep_pu_config_t; 626 627 /** 628 * Initializer for rtc_sleep_pu_config_t which sets all flags to the same value 629 */ 630 #define RTC_SLEEP_PU_CONFIG_ALL(val) {\ 631 .dig_fpu = (val), \ 632 .rtc_fpu = (val), \ 633 .cpu_fpu = (val), \ 634 .i2s_fpu = (val), \ 635 .bb_fpu = (val), \ 636 .nrx_fpu = (val), \ 637 .fe_fpu = (val), \ 638 .sram_fpu = (val), \ 639 .rom_ram_fpu = (val), \ 640 } 641 642 void rtc_sleep_pu(rtc_sleep_pu_config_t cfg); 643 644 /** 645 * @brief sleep configuration for rtc_sleep_init function 646 */ 647 typedef struct { 648 uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory) 649 uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used) 650 uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory 651 uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory 652 uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals 653 uint32_t dig_ret_pd_en : 1; //!< power down dig_ret 654 uint32_t bt_pd_en : 1; //!< power down BT 655 uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep. 656 uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator 657 uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals 658 uint32_t deep_slp : 1; //!< power down digital domain 659 uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode 660 uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode 661 uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode 662 uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode 663 uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode 664 uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator 665 uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep 666 uint32_t deep_slp_reject : 1; 667 uint32_t light_slp_reject : 1; 668 } rtc_sleep_config_t; 669 670 /** 671 * Default initializer for rtc_sleep_config_t 672 * 673 * This initializer sets all fields to "reasonable" values (e.g. suggested for 674 * production use) based on a combination of RTC_SLEEP_PD_x flags. 675 * 676 * @param RTC_SLEEP_PD_x flags combined using bitwise OR 677 */ 678 #define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG) 679 #define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ 680 .lslp_mem_inf_fpu = 0, \ 681 .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ 682 .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ 683 .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ 684 .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ 685 .dig_ret_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_RET) ? 1 : 0, \ 686 .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \ 687 .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \ 688 .int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ 689 .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \ 690 .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ 691 .wdt_flashboot_mod_en = 0, \ 692 .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ 693 .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ 694 : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ 695 : RTC_CNTL_DBIAS_SLP, \ 696 .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ 697 .rtc_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ 698 : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ 699 : RTC_CNTL_DBIAS_SLP, \ 700 .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ 701 .xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ 702 .deep_slp_reject = 1, \ 703 .light_slp_reject = 1 \ 704 }; 705 706 #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) 707 #define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals 708 #define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory 709 #define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory 710 #define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU 711 #define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator 712 #define RTC_SLEEP_PD_DIG_RET BIT(6) //!< Power down WIFI 713 #define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT 714 #define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart 715 #define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals 716 #define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator 717 #define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL 718 719 /** 720 * @brief Prepare the chip to enter sleep mode 721 * 722 * This function configures various power control state machines to handle 723 * entry into light sleep or deep sleep mode, switches APB and CPU clock source 724 * (usually to XTAL), and sets bias voltages for digital and RTC power domains. 725 * 726 * This function does not actually enter sleep mode; this is done using 727 * rtc_sleep_start function. Software may do some other actions between 728 * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure 729 * wakeup sources. 730 * @param cfg sleep mode configuration 731 */ 732 void rtc_sleep_init(rtc_sleep_config_t cfg); 733 734 /** 735 * @brief Low level initialize for rtc state machine waiting cycles after waking up 736 * 737 * This function configures the cycles chip need to wait for internal 8MHz 738 * oscillator and external 40MHz crystal. As we configure fixed time for waiting 739 * crystal, we need to pass period to calculate cycles. Now this function only 740 * used in lightsleep mode. 741 * 742 * @param slowclk_period re-calibrated slow clock period 743 */ 744 void rtc_sleep_low_init(uint32_t slowclk_period); 745 746 /** 747 * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source 748 * @param t value of RTC counter at which wakeup from sleep will happen; 749 * only the lower 48 bits are used 750 */ 751 void rtc_sleep_set_wakeup_time(uint64_t t); 752 753 #define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup 754 #define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup 755 #define RTC_WIFI_TRIG_EN BIT(5) //!< WIFI wakeup (light sleep only) 756 #define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only) 757 #define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only) 758 #define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only) 759 #define RTC_XTAL32K_DEAD_TRIG_EN BIT(12) 760 #define RTC_USB_TRIG_EN BIT(14) 761 #define RTC_BROWNOUT_DET_TRIG_EN BIT(16) 762 763 /** 764 * @brief Enter deep or light sleep mode 765 * 766 * This function enters the sleep mode previously configured using rtc_sleep_init 767 * function. Before entering sleep, software should configure wake up sources 768 * appropriately (set up GPIO wakeup registers, timer wakeup registers, 769 * and so on). 770 * 771 * If deep sleep mode was configured using rtc_sleep_init, and sleep is not 772 * rejected by hardware (based on reject_opt flags), this function never returns. 773 * When the chip wakes up from deep sleep, CPU is reset and execution starts 774 * from ROM bootloader. 775 * 776 * If light sleep mode was configured using rtc_sleep_init, this function 777 * returns on wakeup, or if sleep is rejected by hardware. 778 * 779 * @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags 780 * combined with OR) 781 * @param reject_opt bit mask of sleep reject reasons: 782 * - RTC_CNTL_GPIO_REJECT_EN 783 * - RTC_CNTL_SDIO_REJECT_EN 784 * These flags are used to prevent entering sleep when e.g. 785 * an external host is communicating via SDIO slave 786 * @return non-zero if sleep was rejected by hardware 787 */ 788 uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu); 789 790 /** 791 * @brief Enter deep sleep mode 792 * 793 * Similar to rtc_sleep_start(), but additionally uses hardware to calculate the CRC value 794 * of RTC FAST memory. On wake, this CRC is used to determine if a deep sleep wake 795 * stub is valid to execute (if a wake address is set). 796 * 797 * No RAM is accessed while calculating the CRC and going into deep sleep, which makes 798 * this function safe to use even if the caller's stack is in RTC FAST memory. 799 * 800 * @note If no deep sleep wake stub address is set then calling rtc_sleep_start() will 801 * have the same effect and takes less time as CRC calculation is skipped. 802 * 803 * @note This function should only be called after rtc_sleep_init() has been called to 804 * configure the system for deep sleep. 805 * 806 * @param wakeup_opt - same as for rtc_sleep_start 807 * @param reject_opt - same as for rtc_sleep_start 808 * 809 * @return non-zero if sleep was rejected by hardware 810 */ 811 uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); 812 813 /** 814 * RTC power and clock control initialization settings 815 */ 816 typedef struct { 817 uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready 818 uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready 819 uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready 820 uint32_t clkctl_init : 1; //!< Perform clock control related initialization 821 uint32_t pwrctl_init : 1; //!< Perform power control related initialization 822 uint32_t xtal_fpu : 1; 823 uint32_t bbpll_fpu : 1; 824 uint32_t cpu_waiti_clk_gate : 1; 825 uint32_t cali_ocode : 1; //!< Calibrate Ocode to make bangap voltage more precise. 826 uint32_t pmu_ctl : 1; 827 } rtc_config_t; 828 829 /** 830 * Default initializer of rtc_config_t. 831 * 832 * This initializer sets all fields to "reasonable" values (e.g. suggested for 833 * production use). 834 */ 835 #define RTC_CONFIG_DEFAULT() {\ 836 .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \ 837 .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \ 838 .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \ 839 .clkctl_init = 1, \ 840 .pwrctl_init = 1, \ 841 .xtal_fpu = 0, \ 842 .bbpll_fpu = 0, \ 843 .cpu_waiti_clk_gate = 1, \ 844 .cali_ocode = 0, \ 845 .pmu_ctl = 1\ 846 } 847 typedef struct { 848 /* data */ 849 uint32_t or_en_cont_cal : 1; //!< default:0 rtc_init:0 pvt can be enable by either this register or digital -- if_en_cont_cal 850 uint32_t enx_rtc_dreg : 1; //!< default:1 rtc_init:1 use i2c registers to configure rtc regulator voltage level instead of pvt result -- int_dreg 851 uint32_t enx_dig_dreg : 1; //!< default:1 rtc_init:1 use i2c registers to configure dig regulator voltage level instead of pvt result -- int_dreg 852 uint32_t en_i2c_rtc_dreg : 1; //!< default:1 rtc_init:0 1: i2c_rtc_dreg; 0: if_rtc_dreg 853 uint32_t en_i2c_dig_dreg : 1; //!< default:1 rtc_init:0 1: i2c_dig_dreg; 0: if_dig_dreg 854 uint32_t en_i2c_rtc_dreg_slp : 1; //!< default:1 rtc_init:0 1: i2c_rtc_dreg_slp; 0: if_rtc_dreg_slp 855 uint32_t en_i2c_dig_dreg_slp : 1; //!< default:1 rtc_init:0 1: i2c_dig_dreg_slp; 0: if_dig_dreg_slp 856 uint32_t or_xpd_rtc_slave_3p3 : 1; //!< default:1 rtc_init:0 to turn off rtc slave, which is only required before DCDC running 857 uint32_t or_xpd_rtc_reg : 1; //!< default:1 rtc_init:0 handover control to digital -- if_xpd_rtc_reg 858 uint32_t or_xpd_dig_reg : 1; //!< default:1 rtc_init:0 handover control to digital -- if_xpd_dig_reg 859 uint32_t or_pd_rtc_reg_slp : 1; //!< default:0 rtc_init:1 configure this i2c to control rtc_sleep_regulator on off, no coressponding digital control signal 860 uint32_t or_pd_dig_reg_slp : 1; //!< default:0 rtc_init:0 default value 0 puts dig_sleep_regulator controlled by digital -- if_xpd_dig_reg_slp 861 uint32_t or_xpd_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_xpd_dcdc 862 uint32_t or_disalbe_deep_sleep_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_enable_deep_sleep_dcdc 863 uint32_t or_disalbe_light_sleep_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_enable_light_sleep_dcdc 864 uint32_t or_enalbe_trx_mode_dcdc : 1; //!< default:1 rtc_init:0 handover control to digital -- if_enable_trx_mode_dcdc 865 uint32_t or_enx_reg_dcdc : 1; //!< default:0 rtc_init:1 handover dcdc configuration registers to digital control signals, including popenb, sstime, ccm, vset, fsw, dcmlevel, dcm2enb, ramp, ramplevel 866 uint32_t or_unlock_dcdc : 1; //!< default:0 rtc_init:0 not used in this version of silicon, can be unleashed if metal change if_vgood_lock_dcdc signal to high 867 uint32_t or_force_lock_dcdc : 1; //!< default:0 rtc_init:0 dcdc will be locked and shut-off if this register sets to 1 868 uint32_t or_enb_slow_clk : 1; //!< default:0 rtc_init:1 handover slow clock control to digital -- if_enb_slow_clk 869 uint32_t or_xpd_trx : 1; //!< default:1 rtc_init:0 handover trx control to digital -- if_xpd_trx 870 uint32_t or_en_reset_chip : 1; //!< default:0 rtc_init:1 handover reset chip control to digital -- if_reset_chip 871 uint32_t or_force_xpd_reg_slave : 1; //!< default:0 rtc_init:1 set this reg to 1 after DCDC ready, to have rtc & dig slave control independent of DCDC status 872 } pmu_config_t; 873 874 #define PMU_CONFIG_DEFAULT() {\ 875 .or_en_cont_cal = 0, \ 876 .enx_rtc_dreg = 1, \ 877 .enx_dig_dreg = 1, \ 878 .en_i2c_rtc_dreg = 0, \ 879 .en_i2c_dig_dreg = 0, \ 880 .en_i2c_rtc_dreg_slp = 0, \ 881 .en_i2c_dig_dreg_slp = 0, \ 882 .or_xpd_rtc_slave_3p3 = 0, \ 883 .or_xpd_rtc_reg = 0, \ 884 .or_xpd_dig_reg = 0, \ 885 .or_pd_rtc_reg_slp = 0, \ 886 .or_pd_dig_reg_slp = 0, \ 887 .or_xpd_dcdc = 0, \ 888 .or_disalbe_deep_sleep_dcdc = 0, \ 889 .or_disalbe_light_sleep_dcdc = 0, \ 890 .or_enalbe_trx_mode_dcdc = 0, \ 891 .or_enx_reg_dcdc = 1, \ 892 .or_unlock_dcdc = 0, \ 893 .or_force_lock_dcdc = 0, \ 894 .or_xpd_trx = 0, \ 895 .or_en_reset_chip = 1, \ 896 .or_force_xpd_reg_slave = 1\ 897 } 898 899 typedef struct { 900 uint32_t swt_idle: 1; //!< If 1, swt_idle is sleep mode ; if 0, swt_idle is active mode 901 uint32_t swt_monitor: 1; //!< If 1, swt_monitor is sleep mode ; if 0, swt_monitor is active mode 902 uint32_t swt_slp: 1; //!< If 1, swt_slp is sleep mode ; if 0, swt_slp is active mode 903 } dbias_swt_cfg_t; 904 905 #define DBIAS_SWITCH_CONFIG_DEFAULT(){\ 906 .swt_idle = 0, \ 907 .swt_monitor = 1, \ 908 .swt_slp = 1\ 909 } 910 911 typedef struct { 912 /* data */ 913 uint32_t dig_regul0_en: 1; //!< If 1, dig_regulator0 is ctl by fsm; if 0, dig_regulator0 force pd. 914 uint32_t dig_regul1_en: 1; //!< If 1, dig_regulator1 is ctl by fsm; if 0, dig_regulator1 force pd. 915 uint32_t rtc_regul0_en: 1; //!< If 1, rtc_regulator0 is ctl by fsm; if 0, rtc_regulator0 force pd. 916 } regulator_cfg_t; 917 918 #define REGULATOR_SET_DEFAULT(){\ 919 .dig_regul0_en = 1, \ 920 .dig_regul1_en = 1, \ 921 .rtc_regul0_en = 1, \ 922 } 923 924 /** 925 * Initialize RTC clock and power control related functions 926 * @param cfg configuration options as rtc_config_t 927 */ 928 void rtc_init(rtc_config_t cfg); 929 930 /** 931 * Structure describing vddsdio configuration 932 */ 933 typedef struct { 934 uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins. 935 uint32_t enable : 1; //!< Enable VDDSDIO regulator 936 uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V 937 uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator 938 uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator 939 uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator 940 } rtc_vddsdio_config_t; 941 942 /** 943 * Get current VDDSDIO configuration 944 * If VDDSDIO configuration is overridden by RTC, get values from RTC 945 * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE 946 * Otherwise, use default values and the level of MTDI bootstrapping pin. 947 * @return currently used VDDSDIO configuration 948 */ 949 rtc_vddsdio_config_t rtc_vddsdio_get_config(void); 950 951 /** 952 * Set new VDDSDIO configuration using RTC registers. 953 * If config.force == 1, this overrides configuration done using bootstrapping 954 * pins and EFUSE. 955 * 956 * @param config new VDDSDIO configuration 957 */ 958 void rtc_vddsdio_set_config(rtc_vddsdio_config_t config); 959 960 961 /* Select clock root source for esp32h2. return source clk freq_mhz 962 */ 963 uint32_t root_clk_slt(uint32_t source); 964 uint32_t root_clk_get(void); 965 966 /** 967 * Regulator config 968 */ 969 typedef struct { 970 uint32_t dig_source : 1; 971 uint32_t dig_active_dbias : 5; 972 uint32_t dig_slp_dbias : 5; 973 uint32_t rtc_source : 1; 974 uint32_t rtc_active_dbias : 5; 975 uint32_t rtc_slp_dbias : 5; 976 } regulator_config_t; 977 978 #define REGULATOR0_CONFIG_DEFAULT() {\ 979 .dig_source = 0, \ 980 .dig_active_dbias = 20, \ 981 .dig_slp_dbias = 8, \ 982 .rtc_source = 0, \ 983 .rtc_active_dbias = 20, \ 984 .rtc_slp_dbias = 8 \ 985 } 986 #define REGULATOR1_CONFIG_DEFAULT() {\ 987 .dig_source = 1, \ 988 .dig_active_dbias = 15, \ 989 .dig_slp_dbias = 8, \ 990 .rtc_source = 1, \ 991 .rtc_active_dbias = 15, \ 992 .rtc_slp_dbias = 8 \ 993 } 994 995 996 /** 997 * gpio hangup 998 */ 999 void rtc_gpio_hangup(uint32_t gpio_no); 1000 1001 #ifdef __cplusplus 1002 } 1003 #endif 1004
