1 /*
2 * Copyright (c) 2016 - 2020 Nordic Semiconductor ASA
3 * Copyright (c) 2016 Vinayak Kariappa Chettimada
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/toolchain.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <soc.h>
11
12 #include <hal/nrf_rtc.h>
13 #include <hal/nrf_timer.h>
14 #include <hal/nrf_radio.h>
15 #include <hal/nrf_ccm.h>
16 #include <hal/nrf_aar.h>
17
18 #include "util/mem.h"
19
20 #include "hal/cpu.h"
21 #include "hal/ccm.h"
22 #include "hal/radio.h"
23 #include "hal/radio_df.h"
24 #include "hal/ticker.h"
25
26 #include "ll_sw/pdu_df.h"
27 #include "lll/pdu_vendor.h"
28 #include "ll_sw/pdu.h"
29
30 #include "radio_internal.h"
31
32 /* Converts the GPIO controller in a FEM property's GPIO specification
33 * to its nRF register map pointer.
34 *
35 * Make sure to use NRF_DT_CHECK_GPIO_CTLR_IS_SOC to check the GPIO
36 * controller has the right compatible wherever you use this.
37 */
38 #define NRF_FEM_GPIO(prop) \
39 ((NRF_GPIO_Type *)DT_REG_ADDR(DT_GPIO_CTLR(FEM_NODE, prop)))
40
41 /* Converts GPIO specification to a PSEL value. */
42 #define NRF_FEM_PSEL(prop) NRF_DT_GPIOS_TO_PSEL(FEM_NODE, prop)
43
44 /* Check if GPIO flags are active low. */
45 #define ACTIVE_LOW(flags) ((flags) & GPIO_ACTIVE_LOW)
46
47 /* Check if GPIO flags contain unsupported values. */
48 #define BAD_FLAGS(flags) ((flags) & ~GPIO_ACTIVE_LOW)
49
50 /* GPIOTE OUTINIT setting for a pin's inactive level, from its
51 * devicetree flags.
52 */
53 #define OUTINIT_INACTIVE(flags) \
54 (ACTIVE_LOW(flags) ? \
55 GPIOTE_CONFIG_OUTINIT_High : \
56 GPIOTE_CONFIG_OUTINIT_Low)
57
58 #if defined(FEM_NODE)
59 BUILD_ASSERT(!HAL_RADIO_GPIO_PA_OFFSET_MISSING,
60 "fem node " DT_NODE_PATH(FEM_NODE) " has property "
61 HAL_RADIO_GPIO_PA_PROP_NAME " set, so you must also set "
62 HAL_RADIO_GPIO_PA_OFFSET_PROP_NAME);
63
64 BUILD_ASSERT(!HAL_RADIO_GPIO_LNA_OFFSET_MISSING,
65 "fem node " DT_NODE_PATH(FEM_NODE) " has property "
66 HAL_RADIO_GPIO_LNA_PROP_NAME " set, so you must also set "
67 HAL_RADIO_GPIO_LNA_OFFSET_PROP_NAME);
68 #endif /* FEM_NODE */
69
70 /*
71 * "Manual" conversions of devicetree values to register bits. We
72 * can't use the Zephyr GPIO API here, so we need this extra
73 * boilerplate.
74 */
75
76 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN)
77 #define NRF_GPIO_PA NRF_FEM_GPIO(HAL_RADIO_GPIO_PA_PROP)
78 #define NRF_GPIO_PA_PIN DT_GPIO_PIN(FEM_NODE, HAL_RADIO_GPIO_PA_PROP)
79 #define NRF_GPIO_PA_FLAGS DT_GPIO_FLAGS(FEM_NODE, HAL_RADIO_GPIO_PA_PROP)
80 #define NRF_GPIO_PA_PSEL NRF_FEM_PSEL(HAL_RADIO_GPIO_PA_PROP)
81 NRF_DT_CHECK_GPIO_CTLR_IS_SOC(FEM_NODE, HAL_RADIO_GPIO_PA_PROP,
82 HAL_RADIO_GPIO_PA_PROP_NAME);
83 BUILD_ASSERT(!BAD_FLAGS(NRF_GPIO_PA_FLAGS),
84 "fem node " DT_NODE_PATH(FEM_NODE) " has invalid GPIO flags in "
85 HAL_RADIO_GPIO_PA_PROP_NAME
86 "; only GPIO_ACTIVE_LOW or GPIO_ACTIVE_HIGH are supported");
87 #endif /* HAL_RADIO_GPIO_HAVE_PA_PIN */
88
89 #if defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
90 #define NRF_GPIO_LNA NRF_FEM_GPIO(HAL_RADIO_GPIO_LNA_PROP)
91 #define NRF_GPIO_LNA_PIN DT_GPIO_PIN(FEM_NODE, HAL_RADIO_GPIO_LNA_PROP)
92 #define NRF_GPIO_LNA_FLAGS DT_GPIO_FLAGS(FEM_NODE, HAL_RADIO_GPIO_LNA_PROP)
93 #define NRF_GPIO_LNA_PSEL NRF_FEM_PSEL(HAL_RADIO_GPIO_LNA_PROP)
94 NRF_DT_CHECK_GPIO_CTLR_IS_SOC(FEM_NODE, HAL_RADIO_GPIO_LNA_PROP,
95 HAL_RADIO_GPIO_LNA_PROP_NAME);
96 BUILD_ASSERT(!BAD_FLAGS(NRF_GPIO_LNA_FLAGS),
97 "fem node " DT_NODE_PATH(FEM_NODE) " has invalid GPIO flags in "
98 HAL_RADIO_GPIO_LNA_PROP_NAME
99 "; only GPIO_ACTIVE_LOW or GPIO_ACTIVE_HIGH are supported");
100 #endif /* HAL_RADIO_GPIO_HAVE_LNA_PIN */
101
102 #if defined(HAL_RADIO_FEM_IS_NRF21540)
103
104 #if DT_NODE_HAS_PROP(FEM_NODE, pdn_gpios)
105 #define NRF_GPIO_PDN NRF_FEM_GPIO(pdn_gpios)
106 #define NRF_GPIO_PDN_PIN DT_GPIO_PIN(FEM_NODE, pdn_gpios)
107 #define NRF_GPIO_PDN_FLAGS DT_GPIO_FLAGS(FEM_NODE, pdn_gpios)
108 #define NRF_GPIO_PDN_PSEL NRF_FEM_PSEL(pdn_gpios)
109 #define NRF_GPIO_PDN_OFFSET DT_PROP(FEM_NODE, pdn_settle_time_us)
110 NRF_DT_CHECK_GPIO_CTLR_IS_SOC(FEM_NODE, pdn_gpios, "pdn-gpios");
111 #endif /* DT_NODE_HAS_PROP(FEM_NODE, pdn_gpios) */
112
113 /* CSN is special because it comes from the spi-if property. */
114 #if defined(HAL_RADIO_FEM_NRF21540_HAS_CSN)
115 #define NRF_GPIO_CSN_CTLR DT_SPI_DEV_CS_GPIOS_CTLR(FEM_SPI_DEV_NODE)
116 #define NRF_GPIO_CSN ((NRF_GPIO_Type *)DT_REG_ADDR(NRF_GPIO_CSN_CTLR))
117 #define NRF_GPIO_CSN_PIN DT_SPI_DEV_CS_GPIOS_PIN(FEM_SPI_DEV_NODE)
118 #define NRF_GPIO_CSN_FLAGS DT_SPI_DEV_CS_GPIOS_FLAGS(FEM_SPI_DEV_NODE)
119 #define NRF_GPIO_CSN_PSEL (NRF_GPIO_CSN_PIN + \
120 (DT_PROP(NRF_GPIO_CSN_CTLR, port) << 5))
121 BUILD_ASSERT(DT_NODE_HAS_COMPAT(NRF_GPIO_CSN_CTLR, nordic_nrf_gpio),
122 "fem node " DT_NODE_PATH(FEM_NODE) " has a spi-if property, "
123 " but the chip select pin is not on the SoC. Check cs-gpios in "
124 DT_NODE_PATH(DT_BUS(FEM_SPI_DEV_NODE)));
125 #endif /* HAL_RADIO_FEM_NRF21540_HAS_CSN */
126
127 #endif /* HAL_RADIO_FEM_IS_NRF21540 */
128
129 /* CTEINLINE S0_MASK for periodic advertising PUDs. It allows to accept all types of extended
130 * advertising PDUs to have CTE included.
131 */
132 #define DF_S0_ALLOW_ALL_PER_ADV_PDU 0x0
133 /* CTEINLINE S0_MASK for data channel PDUs. It points to CP bit in S0 byte to check if is it set
134 * to 0x1. In that is true then S1 byte (CTEInfo) is considered as present in a PDU.
135 */
136 #define DF_S0_MASK_CP_BIT_IN_DATA_CHANNEL_PDU 0x20
137
138 static radio_isr_cb_t isr_cb;
139 static void *isr_cb_param;
140
isr_radio(void)141 void isr_radio(void)
142 {
143 if (radio_has_disabled()) {
144 isr_cb(isr_cb_param);
145 }
146 }
147
radio_isr_set(radio_isr_cb_t cb,void * param)148 void radio_isr_set(radio_isr_cb_t cb, void *param)
149 {
150 irq_disable(RADIO_IRQn);
151
152 isr_cb_param = param;
153 isr_cb = cb;
154
155 nrf_radio_int_enable(NRF_RADIO,
156 0 |
157 /* RADIO_INTENSET_READY_Msk |
158 * RADIO_INTENSET_ADDRESS_Msk |
159 * RADIO_INTENSET_PAYLOAD_Msk |
160 * RADIO_INTENSET_END_Msk |
161 */
162 RADIO_INTENSET_DISABLED_Msk
163 /* | RADIO_INTENSET_RSSIEND_Msk |
164 */
165 );
166
167 NVIC_ClearPendingIRQ(RADIO_IRQn);
168 irq_enable(RADIO_IRQn);
169 }
170
radio_setup(void)171 void radio_setup(void)
172 {
173 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN)
174 NRF_GPIO_PA->DIRSET = BIT(NRF_GPIO_PA_PIN);
175 if (ACTIVE_LOW(NRF_GPIO_PA_FLAGS)) {
176 NRF_GPIO_PA->OUTSET = BIT(NRF_GPIO_PA_PIN);
177 } else {
178 NRF_GPIO_PA->OUTCLR = BIT(NRF_GPIO_PA_PIN);
179 }
180 #endif /* HAL_RADIO_GPIO_HAVE_PA_PIN */
181
182 #if defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
183 NRF_GPIO_LNA->DIRSET = BIT(NRF_GPIO_LNA_PIN);
184
185 radio_gpio_lna_off();
186 #endif /* HAL_RADIO_GPIO_HAVE_LNA_PIN */
187
188 #if defined(NRF_GPIO_PDN_PIN)
189 NRF_GPIO_PDN->DIRSET = BIT(NRF_GPIO_PDN_PIN);
190 if (ACTIVE_LOW(NRF_GPIO_PDN_FLAGS)) {
191 NRF_GPIO_PDN->OUTSET = BIT(NRF_GPIO_PDN_PIN);
192 } else {
193 NRF_GPIO_PDN->OUTCLR = BIT(NRF_GPIO_PDN_PIN);
194 }
195 #endif /* NRF_GPIO_PDN_PIN */
196
197 #if defined(NRF_GPIO_CSN_PIN)
198 NRF_GPIO_CSN->DIRSET = BIT(NRF_GPIO_CSN_PIN);
199 if (ACTIVE_LOW(NRF_GPIO_CSN_FLAGS)) {
200 NRF_GPIO_CSN->OUTSET = BIT(NRF_GPIO_CSN_PIN);
201 } else {
202 NRF_GPIO_CSN->OUTCLR = BIT(NRF_GPIO_CSN_PIN);
203 }
204 #endif /* NRF_GPIO_CSN_PIN */
205
206 hal_radio_ram_prio_setup();
207 }
208
radio_reset(void)209 void radio_reset(void)
210 {
211 irq_disable(RADIO_IRQn);
212
213 /* nRF SoC generic radio reset/initializations
214 * Note: Only registers whose bits are partially modified across
215 * functions are assigned back the power-on reset values.
216 * Ignore other registers for reset which will have all bits
217 * explicitly assigned by functions in this file.
218 */
219 NRF_RADIO->PCNF1 = HAL_RADIO_RESET_VALUE_PCNF1;
220
221 #if defined(CONFIG_BT_CTLR_DF) && !defined(CONFIG_ZTEST)
222 radio_df_reset();
223 #endif /* CONFIG_BT_CTLR_DF && !CONFIG_ZTEST */
224
225 /* nRF SoC specific reset/initializations, if any */
226 hal_radio_reset();
227
228 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
229 hal_radio_sw_switch_ppi_group_setup();
230 #endif
231
232 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN) || defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
233 hal_palna_ppi_setup();
234 #endif
235 #if defined(HAL_RADIO_FEM_IS_NRF21540)
236 hal_fem_ppi_setup();
237 #endif
238 }
239
radio_stop(void)240 void radio_stop(void)
241 {
242 /* nRF SoC specific radio stop/cleanup, if any */
243 hal_radio_stop();
244
245 /* nRF SoC generic radio stop/cleanup
246 * TODO: Initialize NRF_RADIO registers used by Controller to power-on
247 * reset values.
248 * This is required in case NRF_RADIO is share/used between
249 * Bluetooth radio events by application defined radio protocols.
250 * The application too shall restore the registers it uses to the
251 * power-on reset values once it has stopped using the radio.
252 *
253 * Registers used for Bluetooth Low Energy Controller:
254 * - MODE
255 * - MODECNF0
256 * - TXPOWER
257 * - FREQUENCY
258 * - DATAWHITEIV
259 * - PCNF0
260 * - PCNF1
261 * - TXADDRESS
262 * - RXADDRESSES
263 * - PREFIX0
264 * - BASE0
265 * - PACKETPTR
266 * - CRCCNF
267 * - CRCPOLY
268 * - CRCINIT
269 * - DAB
270 * - DAP
271 * - DACNF
272 * - BCC
273 * - TIFS
274 * - SHORTS
275 *
276 * Additional registers used for Direction Finding feature:
277 * - SWITCHPATTERN
278 * - DFEMODE
279 * - CTEINLINECONF
280 * - DFECTRL1
281 * - DEFCTRL2
282 * - CLEARPATTERN
283 * - PSEL.DFEGPIO[n]
284 * - DFEPACKET.PTR
285 */
286 }
287
radio_phy_set(uint8_t phy,uint8_t flags)288 void radio_phy_set(uint8_t phy, uint8_t flags)
289 {
290 uint32_t mode;
291
292 mode = hal_radio_phy_mode_get(phy, flags);
293
294 NRF_RADIO->MODE = (mode << RADIO_MODE_MODE_Pos) & RADIO_MODE_MODE_Msk;
295
296 #if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST)
297 NRF_RADIO->MODECNF0 = ((RADIO_MODECNF0_DTX_Center <<
298 RADIO_MODECNF0_DTX_Pos) &
299 RADIO_MODECNF0_DTX_Msk) |
300 ((RADIO_MODECNF0_RU_Fast <<
301 RADIO_MODECNF0_RU_Pos) &
302 RADIO_MODECNF0_RU_Msk);
303 #else /* !CONFIG_BT_CTLR_RADIO_ENABLE_FAST */
304 #if !defined(CONFIG_SOC_SERIES_NRF51X)
305 NRF_RADIO->MODECNF0 = (RADIO_MODECNF0_DTX_Center <<
306 RADIO_MODECNF0_DTX_Pos) &
307 RADIO_MODECNF0_DTX_Msk;
308 #endif /* !CONFIG_SOC_SERIES_NRF51X */
309 #endif /* !CONFIG_BT_CTLR_RADIO_ENABLE_FAST */
310 }
311
radio_tx_power_set(int8_t power)312 void radio_tx_power_set(int8_t power)
313 {
314 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X)
315 uint32_t value;
316
317 /* NOTE: TXPOWER register only accepts upto 0dBm, hence use the HAL
318 * floor value for the TXPOWER register. Permit +3dBm by using high
319 * voltage being set for radio.
320 */
321 value = hal_radio_tx_power_floor(power);
322 NRF_RADIO->TXPOWER = value;
323 hal_radio_tx_power_high_voltage_set(power);
324
325 #else /* !CONFIG_SOC_COMPATIBLE_NRF53X */
326
327 /* NOTE: valid value range is passed by Kconfig define. */
328 NRF_RADIO->TXPOWER = (uint32_t)power;
329
330 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X */
331 }
332
radio_tx_power_max_set(void)333 void radio_tx_power_max_set(void)
334 {
335 int8_t power;
336
337 power = radio_tx_power_max_get();
338 radio_tx_power_set(power);
339 }
340
radio_tx_power_min_get(void)341 int8_t radio_tx_power_min_get(void)
342 {
343 return (int8_t)hal_radio_tx_power_min_get();
344 }
345
radio_tx_power_max_get(void)346 int8_t radio_tx_power_max_get(void)
347 {
348 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X)
349 return RADIO_TXPOWER_TXPOWER_Pos3dBm;
350
351 #else /* !CONFIG_SOC_COMPATIBLE_NRF53X */
352 return (int8_t)hal_radio_tx_power_max_get();
353
354 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X */
355 }
356
radio_tx_power_floor(int8_t power)357 int8_t radio_tx_power_floor(int8_t power)
358 {
359 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X)
360 /* NOTE: TXPOWER register only accepts upto 0dBm, +3dBm permitted by
361 * use of high voltage being set for radio when TXPOWER register is set.
362 */
363 if (power >= (int8_t)RADIO_TXPOWER_TXPOWER_Pos3dBm) {
364 return RADIO_TXPOWER_TXPOWER_Pos3dBm;
365 }
366 #endif /* CONFIG_SOC_COMPATIBLE_NRF53X */
367
368 return (int8_t)hal_radio_tx_power_floor(power);
369 }
370
radio_freq_chan_set(uint32_t chan)371 void radio_freq_chan_set(uint32_t chan)
372 {
373 NRF_RADIO->FREQUENCY = chan;
374 }
375
radio_whiten_iv_set(uint32_t iv)376 void radio_whiten_iv_set(uint32_t iv)
377 {
378 NRF_RADIO->DATAWHITEIV = iv;
379
380 NRF_RADIO->PCNF1 &= ~RADIO_PCNF1_WHITEEN_Msk;
381 NRF_RADIO->PCNF1 |= ((1UL) << RADIO_PCNF1_WHITEEN_Pos) &
382 RADIO_PCNF1_WHITEEN_Msk;
383 }
384
radio_aa_set(const uint8_t * aa)385 void radio_aa_set(const uint8_t *aa)
386 {
387 NRF_RADIO->TXADDRESS =
388 (((0UL) << RADIO_TXADDRESS_TXADDRESS_Pos) &
389 RADIO_TXADDRESS_TXADDRESS_Msk);
390 NRF_RADIO->RXADDRESSES =
391 ((RADIO_RXADDRESSES_ADDR0_Enabled) << RADIO_RXADDRESSES_ADDR0_Pos);
392 NRF_RADIO->PREFIX0 = aa[3];
393 NRF_RADIO->BASE0 = (aa[2] << 24) | (aa[1] << 16) | (aa[0] << 8);
394 }
395
radio_pkt_configure(uint8_t bits_len,uint8_t max_len,uint8_t flags)396 void radio_pkt_configure(uint8_t bits_len, uint8_t max_len, uint8_t flags)
397 {
398 const uint8_t pdu_type = RADIO_PKT_CONF_PDU_TYPE_GET(flags); /* Adv or Data channel */
399 uint8_t bits_s1;
400 uint32_t extra;
401 uint8_t phy;
402
403 #if defined(CONFIG_SOC_SERIES_NRF51X)
404 ARG_UNUSED(phy);
405
406 extra = 0U;
407
408 /* nRF51 supports only 27 byte PDU when using h/w CCM for encryption. */
409 if (!IS_ENABLED(CONFIG_BT_CTLR_DATA_LENGTH_CLEAR) &&
410 pdu_type == RADIO_PKT_CONF_PDU_TYPE_DC) {
411 bits_len = RADIO_PKT_CONF_LENGTH_5BIT;
412 }
413 bits_s1 = RADIO_PKT_CONF_LENGTH_8BIT - bits_len;
414
415 #elif defined(CONFIG_SOC_COMPATIBLE_NRF52X) || \
416 defined(CONFIG_SOC_COMPATIBLE_NRF53X)
417 extra = 0U;
418
419 phy = RADIO_PKT_CONF_PHY_GET(flags);
420 switch (phy) {
421 case PHY_1M:
422 default:
423 extra |= (RADIO_PCNF0_PLEN_8bit << RADIO_PCNF0_PLEN_Pos) &
424 RADIO_PCNF0_PLEN_Msk;
425 break;
426
427 case PHY_2M:
428 extra |= (RADIO_PCNF0_PLEN_16bit << RADIO_PCNF0_PLEN_Pos) &
429 RADIO_PCNF0_PLEN_Msk;
430 break;
431
432 #if defined(CONFIG_BT_CTLR_PHY_CODED)
433 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
434 case PHY_CODED:
435 extra |= (RADIO_PCNF0_PLEN_LongRange << RADIO_PCNF0_PLEN_Pos) &
436 RADIO_PCNF0_PLEN_Msk;
437 extra |= (2UL << RADIO_PCNF0_CILEN_Pos) & RADIO_PCNF0_CILEN_Msk;
438 extra |= (3UL << RADIO_PCNF0_TERMLEN_Pos) &
439 RADIO_PCNF0_TERMLEN_Msk;
440 break;
441 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
442 #endif /* CONFIG_BT_CTLR_PHY_CODED */
443 }
444
445 /* To use same Data Channel PDU structure with nRF5 specific overhead
446 * byte, include the S1 field in radio packet configuration.
447 */
448 if ((pdu_type == RADIO_PKT_CONF_PDU_TYPE_DC) ||
449 (pdu_type == RADIO_PKT_CONF_PDU_TYPE_BIS) ||
450 (pdu_type == RADIO_PKT_CONF_PDU_TYPE_CIS)) {
451 extra |= (RADIO_PCNF0_S1INCL_Include <<
452 RADIO_PCNF0_S1INCL_Pos) & RADIO_PCNF0_S1INCL_Msk;
453 #if defined(CONFIG_BT_CTLR_DF)
454 if (RADIO_PKT_CONF_CTE_GET(flags) == RADIO_PKT_CONF_CTE_ENABLED) {
455 bits_s1 = RADIO_PKT_CONF_S1_8BIT;
456 } else
457 #endif /* CONFIG_BT_CTLR_DF */
458 {
459 bits_s1 = 0U;
460 }
461 } else {
462 bits_s1 = 0U;
463 }
464 #endif /* CONFIG_SOC_COMPATIBLE_NRF52X */
465
466 NRF_RADIO->PCNF0 =
467 (((1UL) << RADIO_PCNF0_S0LEN_Pos) & RADIO_PCNF0_S0LEN_Msk) |
468 ((((uint32_t)bits_len) << RADIO_PCNF0_LFLEN_Pos) & RADIO_PCNF0_LFLEN_Msk) |
469 ((((uint32_t)bits_s1) << RADIO_PCNF0_S1LEN_Pos) & RADIO_PCNF0_S1LEN_Msk) | extra;
470
471 NRF_RADIO->PCNF1 &= ~(RADIO_PCNF1_MAXLEN_Msk | RADIO_PCNF1_STATLEN_Msk |
472 RADIO_PCNF1_BALEN_Msk | RADIO_PCNF1_ENDIAN_Msk);
473 NRF_RADIO->PCNF1 |=
474 ((((uint32_t)max_len) << RADIO_PCNF1_MAXLEN_Pos) & RADIO_PCNF1_MAXLEN_Msk) |
475 (((0UL) << RADIO_PCNF1_STATLEN_Pos) & RADIO_PCNF1_STATLEN_Msk) |
476 (((3UL) << RADIO_PCNF1_BALEN_Pos) & RADIO_PCNF1_BALEN_Msk) |
477 (((RADIO_PCNF1_ENDIAN_Little) << RADIO_PCNF1_ENDIAN_Pos) & RADIO_PCNF1_ENDIAN_Msk);
478 }
479
radio_pkt_rx_set(void * rx_packet)480 void radio_pkt_rx_set(void *rx_packet)
481 {
482 NRF_RADIO->PACKETPTR = (uint32_t)rx_packet;
483 }
484
radio_pkt_tx_set(void * tx_packet)485 void radio_pkt_tx_set(void *tx_packet)
486 {
487 NRF_RADIO->PACKETPTR = (uint32_t)tx_packet;
488 }
489
radio_tx_ready_delay_get(uint8_t phy,uint8_t flags)490 uint32_t radio_tx_ready_delay_get(uint8_t phy, uint8_t flags)
491 {
492 return hal_radio_tx_ready_delay_us_get(phy, flags);
493 }
494
radio_tx_chain_delay_get(uint8_t phy,uint8_t flags)495 uint32_t radio_tx_chain_delay_get(uint8_t phy, uint8_t flags)
496 {
497 return hal_radio_tx_chain_delay_us_get(phy, flags);
498 }
499
radio_rx_ready_delay_get(uint8_t phy,uint8_t flags)500 uint32_t radio_rx_ready_delay_get(uint8_t phy, uint8_t flags)
501 {
502 return hal_radio_rx_ready_delay_us_get(phy, flags);
503 }
504
radio_rx_chain_delay_get(uint8_t phy,uint8_t flags)505 uint32_t radio_rx_chain_delay_get(uint8_t phy, uint8_t flags)
506 {
507 return hal_radio_rx_chain_delay_us_get(phy, flags);
508 }
509
radio_rx_enable(void)510 void radio_rx_enable(void)
511 {
512 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
513 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X)
514 /* NOTE: Timer clear DPPI configuration is needed only for nRF53
515 * because of calls to radio_disable() and
516 * radio_switch_complete_and_disable() inside a radio event call
517 * hal_radio_sw_switch_disable(), which in the case of nRF53
518 * cancels the task subscription.
519 */
520 /* FIXME: hal_sw_switch_timer_clear_ppi_config() sets both task and
521 * event. Consider a new interface to only set the task, or
522 * change the design to not clear task subscription inside a
523 * radio event but when the radio event is done.
524 */
525 hal_sw_switch_timer_clear_ppi_config();
526 #endif /* CONFIG_SOC_COMPATIBLE_NRF53X */
527 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
528
529 nrf_radio_task_trigger(NRF_RADIO, NRF_RADIO_TASK_RXEN);
530 }
531
radio_tx_enable(void)532 void radio_tx_enable(void)
533 {
534 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
535 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X)
536 /* NOTE: Timer clear DPPI configuration is needed only for nRF53
537 * because of calls to radio_disable() and
538 * radio_switch_complete_and_disable() inside a radio event call
539 * hal_radio_sw_switch_disable(), which in the case of nRF53
540 * cancels the task subscription.
541 */
542 /* FIXME: hal_sw_switch_timer_clear_ppi_config() sets both task and
543 * event. Consider a new interface to only set the task, or
544 * change the design to not clear task subscription inside a
545 * radio event but when the radio event is done.
546 */
547 hal_sw_switch_timer_clear_ppi_config();
548 #endif /* CONFIG_SOC_COMPATIBLE_NRF53X */
549 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
550
551 nrf_radio_task_trigger(NRF_RADIO, NRF_RADIO_TASK_TXEN);
552 }
553
radio_disable(void)554 void radio_disable(void)
555 {
556 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
557 hal_radio_sw_switch_cleanup();
558 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
559
560 NRF_RADIO->SHORTS = 0;
561 nrf_radio_task_trigger(NRF_RADIO, NRF_RADIO_TASK_DISABLE);
562 }
563
radio_status_reset(void)564 void radio_status_reset(void)
565 {
566 /* NOTE: Only EVENTS_* registers read (checked) by software needs reset
567 * between Radio IRQs. In PPI use, irrespective of stored EVENT_*
568 * register value, PPI task will be triggered. Hence, other
569 * EVENT_* registers are not reset to save code and CPU time.
570 */
571 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_READY);
572 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_END);
573 #if defined(CONFIG_BT_CTLR_DF_SUPPORT) && !defined(CONFIG_ZTEST)
574 /* Clear it only for SoCs supporting DF extension */
575 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_PHYEND);
576 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_CTEPRESENT);
577 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_BCMATCH);
578 #endif /* CONFIG_BT_CTLR_DF_SUPPORT && !CONFIG_ZTEST */
579 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_DISABLED);
580 #if defined(CONFIG_BT_CTLR_PHY_CODED)
581 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
582 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_RATEBOOST);
583 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
584 #endif /* CONFIG_BT_CTLR_PHY_CODED */
585 }
586
radio_is_ready(void)587 uint32_t radio_is_ready(void)
588 {
589 return (NRF_RADIO->EVENTS_READY != 0);
590 }
591
592 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
593 static uint32_t last_pdu_end_us;
594
radio_is_done(void)595 uint32_t radio_is_done(void)
596 {
597 if (NRF_RADIO->NRF_RADIO_TXRX_END_EVENT != 0) {
598 /* On packet END event increment last packet end time value.
599 * Note: this depends on the function being called exactly once
600 * in the ISR function.
601 */
602 last_pdu_end_us += EVENT_TIMER->CC[2];
603 return 1;
604 } else {
605 return 0;
606 }
607 }
608
609 #else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
radio_is_done(void)610 uint32_t radio_is_done(void)
611 {
612 return (NRF_RADIO->NRF_RADIO_TXRX_END_EVENT != 0);
613 }
614 #endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
615
radio_has_disabled(void)616 uint32_t radio_has_disabled(void)
617 {
618 return (NRF_RADIO->EVENTS_DISABLED != 0);
619 }
620
radio_is_idle(void)621 uint32_t radio_is_idle(void)
622 {
623 return (NRF_RADIO->STATE == 0);
624 }
625
radio_crc_configure(uint32_t polynomial,uint32_t iv)626 void radio_crc_configure(uint32_t polynomial, uint32_t iv)
627 {
628 NRF_RADIO->CRCCNF =
629 (((RADIO_CRCCNF_SKIPADDR_Skip) << RADIO_CRCCNF_SKIPADDR_Pos) &
630 RADIO_CRCCNF_SKIPADDR_Msk) |
631 (((RADIO_CRCCNF_LEN_Three) << RADIO_CRCCNF_LEN_Pos) &
632 RADIO_CRCCNF_LEN_Msk);
633 NRF_RADIO->CRCPOLY = polynomial;
634 NRF_RADIO->CRCINIT = iv;
635 }
636
radio_crc_is_valid(void)637 uint32_t radio_crc_is_valid(void)
638 {
639 return (NRF_RADIO->CRCSTATUS != 0);
640 }
641
642 static uint8_t MALIGN(4) _pkt_empty[PDU_EM_LL_SIZE_MAX];
643 static uint8_t MALIGN(4) _pkt_scratch[MAX((HAL_RADIO_PDU_LEN_MAX + 3),
644 PDU_AC_LL_SIZE_MAX)];
645
radio_pkt_empty_get(void)646 void *radio_pkt_empty_get(void)
647 {
648 return _pkt_empty;
649 }
650
radio_pkt_scratch_get(void)651 void *radio_pkt_scratch_get(void)
652 {
653 return _pkt_scratch;
654 }
655
656 #if defined(CONFIG_SOC_NRF52832) && \
657 defined(CONFIG_BT_CTLR_LE_ENC) && \
658 defined(HAL_RADIO_PDU_LEN_MAX) && \
659 (!defined(CONFIG_BT_CTLR_DATA_LENGTH_MAX) || \
660 (CONFIG_BT_CTLR_DATA_LENGTH_MAX < (HAL_RADIO_PDU_LEN_MAX - 4)))
661 static uint8_t MALIGN(4) _pkt_decrypt[MAX((HAL_RADIO_PDU_LEN_MAX + 3),
662 PDU_AC_LL_SIZE_MAX)];
663
radio_pkt_decrypt_get(void)664 void *radio_pkt_decrypt_get(void)
665 {
666 return _pkt_decrypt;
667 }
668 #elif !defined(HAL_RADIO_PDU_LEN_MAX)
669 #error "Undefined HAL_RADIO_PDU_LEN_MAX."
670 #endif
671
672 #if defined(CONFIG_BT_CTLR_ADV_ISO) || defined(CONFIG_BT_CTLR_SYNC_ISO)
673 /* Dedicated Rx PDU Buffer for Control PDU independent of node_rx with BIS Data
674 * PDU buffer. Note this buffer will be used to store whole PDUs, not just the BIG control payload.
675 */
676 static uint8_t pkt_big_ctrl[offsetof(struct pdu_bis, payload) + sizeof(struct pdu_big_ctrl)];
677
radio_pkt_big_ctrl_get(void)678 void *radio_pkt_big_ctrl_get(void)
679 {
680 return pkt_big_ctrl;
681 }
682 #endif /* CONFIG_BT_CTLR_ADV_ISO || CONFIG_BT_CTLR_SYNC_ISO */
683
684 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
685 static uint8_t sw_tifs_toggle;
686 /**
687 * @brief Implementation of Radio operation software switch.
688 *
689 * In case the switch is from RX to TX or from RX to RX and CTEINLINE is enabled then PDU end event
690 * (EVENTS_PHYEND) may be delayed after actual PDU end. The delay occurs when received PDU does not
691 * include CTE. To maintain TIFS the delay must be compensated.
692 * To handle that, two timer EVENTS_COMPARE are prepared: without and without delay compensation.
693 * If EVENTS_CTEPRESENT is fired then EVENTS_COMPARE for delayed EVENTS_PHYEND event is cancelled.
694 * In other case EVENTS_COMPARE for delayed compensation will timeout first and disable group of
695 * PPIs related with the Radio operation switch.
696 * Enable of end event compensation is controller by @p end_evt_delay_en.
697 *
698 * @param dir_curr Current direction the Radio is working: SW_SWITCH_TX or SW_SWITCH_RX
699 * @param dir_next Next direction the Radio is preparing for: SW_SWITCH_TX or SW_SWITCH_RX
700 * @param phy_curr PHY the Radio is working on.
701 * @param flags_curr Flags related with current PHY, the Radio is working on.
702 * @param phy_next Next PHY the Radio is preparing for.
703 * @param flags_next Flags related with next PHY, the Radio is preparing for.
704 * @param end_evt_delay_en Enable end event delay compensation for TIFS after switch from current
705 * direction to next direction.
706 */
sw_switch(uint8_t dir_curr,uint8_t dir_next,uint8_t phy_curr,uint8_t flags_curr,uint8_t phy_next,uint8_t flags_next,enum radio_end_evt_delay_state end_evt_delay_en)707 void sw_switch(uint8_t dir_curr, uint8_t dir_next, uint8_t phy_curr, uint8_t flags_curr,
708 uint8_t phy_next, uint8_t flags_next,
709 enum radio_end_evt_delay_state end_evt_delay_en)
710 {
711 uint8_t ppi = HAL_SW_SWITCH_RADIO_ENABLE_PPI(sw_tifs_toggle);
712 uint8_t cc = SW_SWITCH_TIMER_EVTS_COMP(sw_tifs_toggle);
713 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
714 uint8_t phyend_delay_cc =
715 SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_EVTS_COMP(sw_tifs_toggle);
716 uint8_t radio_enable_ppi =
717 HAL_SW_SWITCH_RADIO_ENABLE_PHYEND_DELAY_COMPENSATION_PPI(sw_tifs_toggle);
718 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
719 uint32_t delay;
720
721 hal_radio_sw_switch_setup(sw_tifs_toggle);
722
723 /* NOTE: As constants are passed to dir_curr and dir_next, the
724 * compiler should optimize out the redundant code path
725 * during the optimization.
726 */
727 if (dir_next == SW_SWITCH_TX) {
728 /* TX */
729
730 /* Calculate delay with respect to current and next PHY.
731 */
732 if (dir_curr == SW_SWITCH_TX) {
733 delay = HAL_RADIO_NS2US_ROUND(
734 hal_radio_tx_ready_delay_ns_get(phy_next,
735 flags_next) +
736 hal_radio_tx_chain_delay_ns_get(phy_curr,
737 flags_curr));
738
739 hal_radio_b2b_txen_on_sw_switch(cc, ppi);
740 } else {
741 /* If RX PHY is LE Coded, calculate for S8 coding.
742 * Assumption being, S8 has higher delay.
743 */
744 delay = HAL_RADIO_NS2US_ROUND(
745 hal_radio_tx_ready_delay_ns_get(phy_next,
746 flags_next) +
747 hal_radio_rx_chain_delay_ns_get(phy_curr, 1));
748
749 hal_radio_txen_on_sw_switch(cc, ppi);
750 }
751
752 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
753 if (dir_curr == SW_SWITCH_RX && end_evt_delay_en == END_EVT_DELAY_ENABLED &&
754 !(phy_curr & PHY_CODED)) {
755 SW_SWITCH_TIMER->CC[phyend_delay_cc] =
756 SW_SWITCH_TIMER->CC[cc] - RADIO_EVENTS_PHYEND_DELAY_US;
757 if (delay < SW_SWITCH_TIMER->CC[cc]) {
758 nrf_timer_cc_set(SW_SWITCH_TIMER, phyend_delay_cc,
759 (SW_SWITCH_TIMER->CC[phyend_delay_cc] - delay));
760 } else {
761 nrf_timer_cc_set(SW_SWITCH_TIMER, phyend_delay_cc, 1);
762 }
763
764 hal_radio_sw_switch_phyend_delay_compensation_config_set(radio_enable_ppi,
765 phyend_delay_cc);
766 } else {
767 hal_radio_sw_switch_phyend_delay_compensation_config_clear(radio_enable_ppi,
768 phyend_delay_cc);
769 }
770 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
771
772 #if defined(CONFIG_BT_CTLR_PHY_CODED)
773 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
774 uint8_t ppi_en =
775 HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI(sw_tifs_toggle);
776 uint8_t ppi_dis =
777 HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(sw_tifs_toggle);
778
779 if (dir_curr == SW_SWITCH_RX && (phy_curr & PHY_CODED)) {
780 /* Switching to TX after RX on LE Coded PHY. */
781
782 uint8_t cc_s2 =
783 SW_SWITCH_TIMER_S2_EVTS_COMP(sw_tifs_toggle);
784
785 uint32_t delay_s2;
786
787 /* Calculate assuming reception on S2 coding scheme. */
788 delay_s2 = HAL_RADIO_NS2US_ROUND(
789 hal_radio_tx_ready_delay_ns_get(phy_next,
790 flags_next) +
791 hal_radio_rx_chain_delay_ns_get(phy_curr, 0));
792
793 SW_SWITCH_TIMER->CC[cc_s2] = SW_SWITCH_TIMER->CC[cc];
794
795 if (delay_s2 < SW_SWITCH_TIMER->CC[cc_s2]) {
796 SW_SWITCH_TIMER->CC[cc_s2] -= delay_s2;
797 } else {
798 SW_SWITCH_TIMER->CC[cc_s2] = 1;
799 }
800
801 /* Setup the Tx start for S2 using a dedicated compare,
802 * setup a PPI to disable PPI group on that compare
803 * event, and then importantly setup a capture PPI to
804 * disable the Tx start for S8 on RATEBOOST event.
805 */
806 hal_radio_sw_switch_coded_tx_config_set(ppi_en, ppi_dis,
807 cc_s2, sw_tifs_toggle);
808
809 } else {
810 /* Switching to TX after RX on LE 1M/2M PHY.
811 *
812 * NOTE: PHYEND delay compensation and switching between Coded S2 and S8 PHY
813 * may not happen at once. PHYEND delay may not happen when Code PHY
814 * is used. Both functionalities use the same EVENTS_COMPARE channels,
815 * hence when PHYEND delay is applied, coded config clear may not be
816 * called.
817 *
818 * TODO: This has to be refactored. It is temporarily implemented this way
819 * because the code is very fragile and hard to debug.
820 */
821 if (end_evt_delay_en != END_EVT_DELAY_ENABLED) {
822 hal_radio_sw_switch_coded_config_clear(ppi_en, ppi_dis, cc,
823 sw_tifs_toggle);
824 }
825
826 hal_radio_sw_switch_disable_group_clear(ppi_dis, cc, sw_tifs_toggle);
827 }
828 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
829 #endif /* CONFIG_BT_CTLR_PHY_CODED */
830 } else {
831 /* RX */
832
833 /* Calculate delay with respect to current and next PHY. */
834 if (dir_curr) {
835 delay = HAL_RADIO_NS2US_CEIL(
836 hal_radio_rx_ready_delay_ns_get(phy_next,
837 flags_next) +
838 hal_radio_tx_chain_delay_ns_get(phy_curr,
839 flags_curr)) +
840 (EVENT_CLOCK_JITTER_US << 1);
841
842 hal_radio_rxen_on_sw_switch(cc, ppi);
843 } else {
844 delay = HAL_RADIO_NS2US_CEIL(
845 hal_radio_rx_ready_delay_ns_get(phy_next,
846 flags_next) +
847 hal_radio_rx_chain_delay_ns_get(phy_curr,
848 flags_curr)) +
849 (EVENT_CLOCK_JITTER_US << 1);
850
851 hal_radio_b2b_rxen_on_sw_switch(cc, ppi);
852 }
853
854
855 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
856 hal_radio_sw_switch_phyend_delay_compensation_config_clear(radio_enable_ppi,
857 phyend_delay_cc);
858 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
859
860 #if defined(CONFIG_BT_CTLR_PHY_CODED)
861 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
862 if (1) {
863 uint8_t ppi_en = HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI(
864 sw_tifs_toggle);
865 uint8_t ppi_dis = HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(
866 sw_tifs_toggle);
867
868 hal_radio_sw_switch_coded_config_clear(ppi_en,
869 ppi_dis, cc, sw_tifs_toggle);
870 hal_radio_sw_switch_disable_group_clear(ppi_dis, cc, sw_tifs_toggle);
871 }
872 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
873 #endif /* CONFIG_BT_CTLR_PHY_CODED */
874 }
875
876 if (delay < SW_SWITCH_TIMER->CC[cc]) {
877 nrf_timer_cc_set(SW_SWITCH_TIMER, cc,
878 (SW_SWITCH_TIMER->CC[cc] - delay));
879 } else {
880 nrf_timer_cc_set(SW_SWITCH_TIMER, cc, 1);
881 }
882
883 hal_radio_nrf_ppi_channels_enable(BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
884 BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI));
885
886 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
887 /* NOTE: For single timer configuration nRF5340 shares the DPPI channel being
888 * triggered by Radio End for End time capture and sw_switch DPPI channel toggling
889 * hence always need to capture End time. Or when using single event timer since
890 * the timer is cleared on Radio End, we always need to capture the Radio End
891 * time-stamp.
892 */
893 hal_radio_end_time_capture_ppi_config();
894 #if !defined(CONFIG_SOC_COMPATIBLE_NRF53X)
895 /* The function is not called for nRF5340 single timer configuration because
896 * HAL_SW_SWITCH_TIMER_CLEAR_PPI is equal to HAL_RADIO_END_TIME_CAPTURE_PPI,
897 * so channel is already enabled.
898 */
899 hal_radio_nrf_ppi_channels_enable(BIT(HAL_RADIO_END_TIME_CAPTURE_PPI));
900 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X */
901 #endif /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
902
903 sw_tifs_toggle += 1U;
904 sw_tifs_toggle &= 1U;
905 }
906 #endif /* CONFIG_BT_CTLR_TIFS_HW */
907
radio_switch_complete_and_rx(uint8_t phy_rx)908 void radio_switch_complete_and_rx(uint8_t phy_rx)
909 {
910 #if defined(CONFIG_BT_CTLR_TIFS_HW)
911 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk |
912 RADIO_SHORTS_END_DISABLE_Msk |
913 RADIO_SHORTS_DISABLED_RXEN_Msk;
914 #else /* !CONFIG_BT_CTLR_TIFS_HW */
915 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_PDU_END_DISABLE;
916
917 /* NOTE: As Tx chain delays are negligible constant values (~1 us)
918 * across nRF5x radios, sw_switch assumes the 1M chain delay for
919 * calculations.
920 */
921 sw_switch(SW_SWITCH_TX, SW_SWITCH_RX, SW_SWITCH_PHY_1M, SW_SWITCH_FLAGS_DONTCARE, phy_rx,
922 SW_SWITCH_FLAGS_DONTCARE, END_EVT_DELAY_DISABLED);
923 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
924 }
925
radio_switch_complete_and_tx(uint8_t phy_rx,uint8_t flags_rx,uint8_t phy_tx,uint8_t flags_tx)926 void radio_switch_complete_and_tx(uint8_t phy_rx, uint8_t flags_rx,
927 uint8_t phy_tx, uint8_t flags_tx)
928 {
929 #if defined(CONFIG_BT_CTLR_TIFS_HW)
930 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk |
931 RADIO_SHORTS_END_DISABLE_Msk |
932 RADIO_SHORTS_DISABLED_TXEN_Msk;
933 #else /* !CONFIG_BT_CTLR_TIFS_HW */
934 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_PDU_END_DISABLE;
935
936 sw_switch(SW_SWITCH_RX, SW_SWITCH_TX, phy_rx, flags_rx, phy_tx, flags_tx,
937 END_EVT_DELAY_DISABLED);
938 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
939 }
940
radio_switch_complete_with_delay_compensation_and_tx(uint8_t phy_rx,uint8_t flags_rx,uint8_t phy_tx,uint8_t flags_tx,enum radio_end_evt_delay_state end_delay_en)941 void radio_switch_complete_with_delay_compensation_and_tx(
942 uint8_t phy_rx, uint8_t flags_rx, uint8_t phy_tx, uint8_t flags_tx,
943 enum radio_end_evt_delay_state end_delay_en)
944 {
945 #if defined(CONFIG_BT_CTLR_TIFS_HW)
946 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | RADIO_SHORTS_END_DISABLE_Msk |
947 RADIO_SHORTS_DISABLED_TXEN_Msk;
948 #else /* !CONFIG_BT_CTLR_TIFS_HW */
949 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_PDU_END_DISABLE;
950
951 sw_switch(SW_SWITCH_RX, SW_SWITCH_TX, phy_rx, flags_rx, phy_tx, flags_tx, end_delay_en);
952 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
953 }
954
radio_switch_complete_and_b2b_tx(uint8_t phy_curr,uint8_t flags_curr,uint8_t phy_next,uint8_t flags_next)955 void radio_switch_complete_and_b2b_tx(uint8_t phy_curr, uint8_t flags_curr,
956 uint8_t phy_next, uint8_t flags_next)
957 {
958 #if defined(CONFIG_BT_CTLR_TIFS_HW)
959 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk |
960 RADIO_SHORTS_END_DISABLE_Msk |
961 RADIO_SHORTS_DISABLED_TXEN_Msk;
962 #else /* !CONFIG_BT_CTLR_TIFS_HW */
963 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_PDU_END_DISABLE;
964
965 sw_switch(SW_SWITCH_TX, SW_SWITCH_TX, phy_curr, flags_curr, phy_next, flags_next,
966 END_EVT_DELAY_DISABLED);
967 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
968 }
969
radio_switch_complete_and_b2b_rx(uint8_t phy_curr,uint8_t flags_curr,uint8_t phy_next,uint8_t flags_next)970 void radio_switch_complete_and_b2b_rx(uint8_t phy_curr, uint8_t flags_curr,
971 uint8_t phy_next, uint8_t flags_next)
972 {
973 #if defined(CONFIG_BT_CTLR_TIFS_HW)
974 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk |
975 RADIO_SHORTS_END_DISABLE_Msk |
976 RADIO_SHORTS_DISABLED_RXEN_Msk;
977 #else /* !CONFIG_BT_CTLR_TIFS_HW */
978 NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_PDU_END_DISABLE;
979
980 sw_switch(SW_SWITCH_RX, SW_SWITCH_RX, phy_curr, flags_curr, phy_next, flags_next,
981 END_EVT_DELAY_DISABLED);
982 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
983 }
984
radio_switch_complete_and_b2b_tx_disable(void)985 void radio_switch_complete_and_b2b_tx_disable(void)
986 {
987 #if defined(CONFIG_BT_CTLR_TIFS_HW)
988 NRF_RADIO->SHORTS = (RADIO_SHORTS_READY_START_Msk | RADIO_SHORTS_END_DISABLE_Msk);
989 #else /* CONFIG_BT_CTLR_TIFS_HW */
990 NRF_RADIO->SHORTS = (RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_PDU_END_DISABLE);
991 hal_radio_sw_switch_b2b_tx_disable(sw_tifs_toggle);
992 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
993 }
994
radio_switch_complete_and_b2b_rx_disable(void)995 void radio_switch_complete_and_b2b_rx_disable(void)
996 {
997 #if defined(CONFIG_BT_CTLR_TIFS_HW)
998 NRF_RADIO->SHORTS = (RADIO_SHORTS_READY_START_Msk | RADIO_SHORTS_END_DISABLE_Msk);
999 #else /* CONFIG_BT_CTLR_TIFS_HW */
1000 NRF_RADIO->SHORTS = (RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_PDU_END_DISABLE);
1001 hal_radio_sw_switch_b2b_rx_disable(sw_tifs_toggle);
1002 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1003 }
1004
radio_switch_complete_and_disable(void)1005 void radio_switch_complete_and_disable(void)
1006 {
1007 #if defined(CONFIG_BT_CTLR_TIFS_HW)
1008 NRF_RADIO->SHORTS = (RADIO_SHORTS_READY_START_Msk | RADIO_SHORTS_END_DISABLE_Msk);
1009 #else /* CONFIG_BT_CTLR_TIFS_HW */
1010 NRF_RADIO->SHORTS = (RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_PDU_END_DISABLE);
1011 hal_radio_sw_switch_disable();
1012 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1013 }
1014
radio_phy_flags_rx_get(void)1015 uint8_t radio_phy_flags_rx_get(void)
1016 {
1017 #if defined(CONFIG_BT_CTLR_PHY_CODED)
1018 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
1019 return (NRF_RADIO->EVENTS_RATEBOOST) ? 0U : 1U;
1020 #else /* !CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1021 return 0;
1022 #endif /* !CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1023 #else /* !CONFIG_BT_CTLR_PHY_CODED */
1024 return 0;
1025 #endif /* !CONFIG_BT_CTLR_PHY_CODED */
1026 }
1027
radio_rssi_measure(void)1028 void radio_rssi_measure(void)
1029 {
1030 NRF_RADIO->SHORTS |=
1031 (RADIO_SHORTS_ADDRESS_RSSISTART_Msk |
1032 RADIO_SHORTS_DISABLED_RSSISTOP_Msk);
1033 }
1034
radio_rssi_get(void)1035 uint32_t radio_rssi_get(void)
1036 {
1037 return NRF_RADIO->RSSISAMPLE;
1038 }
1039
radio_rssi_status_reset(void)1040 void radio_rssi_status_reset(void)
1041 {
1042 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_RSSIEND);
1043 }
1044
radio_rssi_is_ready(void)1045 uint32_t radio_rssi_is_ready(void)
1046 {
1047 return (NRF_RADIO->EVENTS_RSSIEND != 0);
1048 }
1049
radio_filter_configure(uint8_t bitmask_enable,uint8_t bitmask_addr_type,uint8_t * bdaddr)1050 void radio_filter_configure(uint8_t bitmask_enable, uint8_t bitmask_addr_type,
1051 uint8_t *bdaddr)
1052 {
1053 uint8_t index;
1054
1055 for (index = 0U; index < 8; index++) {
1056 NRF_RADIO->DAB[index] = ((uint32_t)bdaddr[3] << 24) |
1057 ((uint32_t)bdaddr[2] << 16) |
1058 ((uint32_t)bdaddr[1] << 8) |
1059 bdaddr[0];
1060 NRF_RADIO->DAP[index] = ((uint32_t)bdaddr[5] << 8) | bdaddr[4];
1061 bdaddr += 6;
1062 }
1063
1064 NRF_RADIO->DACNF = ((uint32_t)bitmask_addr_type << 8) | bitmask_enable;
1065 }
1066
radio_filter_disable(void)1067 void radio_filter_disable(void)
1068 {
1069 NRF_RADIO->DACNF &= ~(0x000000FF);
1070 }
1071
radio_filter_status_reset(void)1072 void radio_filter_status_reset(void)
1073 {
1074 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_DEVMATCH);
1075 }
1076
radio_filter_has_match(void)1077 uint32_t radio_filter_has_match(void)
1078 {
1079 return (NRF_RADIO->EVENTS_DEVMATCH != 0);
1080 }
1081
radio_filter_match_get(void)1082 uint32_t radio_filter_match_get(void)
1083 {
1084 return NRF_RADIO->DAI;
1085 }
1086
radio_bc_configure(uint32_t n)1087 void radio_bc_configure(uint32_t n)
1088 {
1089 NRF_RADIO->BCC = n;
1090 NRF_RADIO->SHORTS |= RADIO_SHORTS_ADDRESS_BCSTART_Msk;
1091 }
1092
radio_bc_status_reset(void)1093 void radio_bc_status_reset(void)
1094 {
1095 nrf_radio_event_clear(NRF_RADIO, NRF_RADIO_EVENT_BCMATCH);
1096 }
1097
radio_bc_has_match(void)1098 uint32_t radio_bc_has_match(void)
1099 {
1100 return (NRF_RADIO->EVENTS_BCMATCH != 0);
1101 }
1102
radio_tmr_status_reset(void)1103 void radio_tmr_status_reset(void)
1104 {
1105 nrf_rtc_event_disable(NRF_RTC0, RTC_EVTENCLR_COMPARE2_Msk);
1106
1107 hal_trigger_crypt_ppi_disable();
1108
1109 hal_radio_nrf_ppi_channels_disable(
1110 BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI) |
1111 BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI) |
1112 BIT(HAL_EVENT_TIMER_START_PPI) |
1113 BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) |
1114 BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) |
1115 BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI) |
1116 BIT(HAL_RADIO_END_TIME_CAPTURE_PPI) |
1117 #if defined(DPPI_PRESENT)
1118 BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
1119 #endif /* DPPI_PRESENT */
1120 #if defined(CONFIG_BT_CTLR_PHY_CODED)
1121 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
1122 BIT(HAL_TRIGGER_RATEOVERRIDE_PPI) |
1123 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1124 BIT(HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI) |
1125 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1126 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1127 #endif /* CONFIG_BT_CTLR_PHY_CODED */
1128 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
1129 BIT(HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI) |
1130 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
1131 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
1132 BIT(HAL_TRIGGER_CRYPT_DELAY_PPI) |
1133 #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
1134 BIT(HAL_TRIGGER_CRYPT_PPI));
1135 }
1136
radio_tmr_tx_status_reset(void)1137 void radio_tmr_tx_status_reset(void)
1138 {
1139 nrf_rtc_event_disable(NRF_RTC0, RTC_EVTENCLR_COMPARE2_Msk);
1140
1141 hal_trigger_crypt_ppi_disable();
1142
1143 hal_radio_nrf_ppi_channels_disable(
1144 #if (HAL_RADIO_ENABLE_TX_ON_TICK_PPI != HAL_RADIO_ENABLE_RX_ON_TICK_PPI) && \
1145 !defined(DPPI_PRESENT)
1146 BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI) |
1147 #endif /* (HAL_RADIO_ENABLE_TX_ON_TICK_PPI !=
1148 * HAL_RADIO_ENABLE_RX_ON_TICK_PPI) && !DPPI_PRESENT
1149 */
1150 BIT(HAL_EVENT_TIMER_START_PPI) |
1151 BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) |
1152 BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) |
1153 BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI) |
1154 BIT(HAL_RADIO_END_TIME_CAPTURE_PPI) |
1155 #if defined(DPPI_PRESENT)
1156 BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
1157 #endif /* DPPI_PRESENT */
1158 #if defined(CONFIG_BT_CTLR_PHY_CODED)
1159 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
1160 BIT(HAL_TRIGGER_RATEOVERRIDE_PPI) |
1161 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1162 BIT(HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI) |
1163 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1164 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1165 #endif /* CONFIG_BT_CTLR_PHY_CODED */
1166 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
1167 BIT(HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI) |
1168 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
1169 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
1170 BIT(HAL_TRIGGER_CRYPT_DELAY_PPI) |
1171 #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
1172 BIT(HAL_TRIGGER_CRYPT_PPI));
1173 }
1174
radio_tmr_rx_status_reset(void)1175 void radio_tmr_rx_status_reset(void)
1176 {
1177 nrf_rtc_event_disable(NRF_RTC0, RTC_EVTENCLR_COMPARE2_Msk);
1178
1179 hal_trigger_crypt_ppi_disable();
1180
1181 hal_radio_nrf_ppi_channels_disable(
1182 #if (HAL_RADIO_ENABLE_TX_ON_TICK_PPI != HAL_RADIO_ENABLE_RX_ON_TICK_PPI) && \
1183 !defined(DPPI_PRESENT)
1184 BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI) |
1185 #endif /* (HAL_RADIO_ENABLE_TX_ON_TICK_PPI !=
1186 * HAL_RADIO_ENABLE_RX_ON_TICK_PPI) && !DPPI_PRESENT
1187 */
1188 BIT(HAL_EVENT_TIMER_START_PPI) |
1189 BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) |
1190 BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) |
1191 BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI) |
1192 BIT(HAL_RADIO_END_TIME_CAPTURE_PPI) |
1193 #if defined(DPPI_PRESENT)
1194 BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
1195 #endif /* DPPI_PRESENT */
1196 #if defined(CONFIG_BT_CTLR_PHY_CODED)
1197 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
1198 BIT(HAL_TRIGGER_RATEOVERRIDE_PPI) |
1199 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1200 BIT(HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI) |
1201 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1202 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1203 #endif /* CONFIG_BT_CTLR_PHY_CODED */
1204 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
1205 BIT(HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI) |
1206 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
1207 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
1208 BIT(HAL_TRIGGER_CRYPT_DELAY_PPI) |
1209 #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
1210 BIT(HAL_TRIGGER_CRYPT_PPI));
1211 }
1212
radio_tmr_tx_enable(void)1213 void radio_tmr_tx_enable(void)
1214 {
1215 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X)
1216 #else /* !CONFIG_SOC_COMPATIBLE_NRF53X */
1217 #if (HAL_RADIO_ENABLE_TX_ON_TICK_PPI == HAL_RADIO_ENABLE_RX_ON_TICK_PPI)
1218 hal_radio_enable_on_tick_ppi_config_and_enable(1U);
1219 #endif /* HAL_RADIO_ENABLE_TX_ON_TICK_PPI == HAL_RADIO_ENABLE_RX_ON_TICK_PPI */
1220 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X */
1221 }
1222
radio_tmr_rx_enable(void)1223 void radio_tmr_rx_enable(void)
1224 {
1225 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X)
1226 #else /* !CONFIG_SOC_COMPATIBLE_NRF53X */
1227 #if (HAL_RADIO_ENABLE_TX_ON_TICK_PPI == HAL_RADIO_ENABLE_RX_ON_TICK_PPI)
1228 hal_radio_enable_on_tick_ppi_config_and_enable(0U);
1229 #endif /* HAL_RADIO_ENABLE_TX_ON_TICK_PPI == HAL_RADIO_ENABLE_RX_ON_TICK_PPI */
1230 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X */
1231 }
1232
radio_tmr_tx_disable(void)1233 void radio_tmr_tx_disable(void)
1234 {
1235 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X)
1236 nrf_radio_subscribe_clear(NRF_RADIO, NRF_RADIO_TASK_TXEN);
1237 #else /* !CONFIG_SOC_COMPATIBLE_NRF53X */
1238 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X */
1239 }
1240
radio_tmr_rx_disable(void)1241 void radio_tmr_rx_disable(void)
1242 {
1243 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X)
1244 nrf_radio_subscribe_clear(NRF_RADIO, NRF_RADIO_TASK_RXEN);
1245 #else /* !CONFIG_SOC_COMPATIBLE_NRF53X */
1246 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X */
1247 }
1248
radio_tmr_tifs_set(uint32_t tifs)1249 void radio_tmr_tifs_set(uint32_t tifs)
1250 {
1251 #if defined(CONFIG_BT_CTLR_TIFS_HW)
1252 NRF_RADIO->TIFS = tifs;
1253 #else /* !CONFIG_BT_CTLR_TIFS_HW */
1254 nrf_timer_cc_set(SW_SWITCH_TIMER,
1255 SW_SWITCH_TIMER_EVTS_COMP(sw_tifs_toggle), tifs);
1256 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1257 }
1258
radio_tmr_start(uint8_t trx,uint32_t ticks_start,uint32_t remainder)1259 uint32_t radio_tmr_start(uint8_t trx, uint32_t ticks_start, uint32_t remainder)
1260 {
1261 hal_ticker_remove_jitter(&ticks_start, &remainder);
1262
1263 nrf_timer_task_trigger(EVENT_TIMER, NRF_TIMER_TASK_CLEAR);
1264 EVENT_TIMER->MODE = 0;
1265 EVENT_TIMER->PRESCALER = 4;
1266 EVENT_TIMER->BITMODE = 2; /* 24 - bit */
1267
1268 nrf_timer_cc_set(EVENT_TIMER, 0, remainder);
1269
1270 nrf_rtc_cc_set(NRF_RTC0, 2, ticks_start);
1271 nrf_rtc_event_enable(NRF_RTC0, RTC_EVTENSET_COMPARE2_Msk);
1272
1273 hal_event_timer_start_ppi_config();
1274 hal_radio_nrf_ppi_channels_enable(BIT(HAL_EVENT_TIMER_START_PPI));
1275
1276 hal_radio_enable_on_tick_ppi_config_and_enable(trx);
1277
1278 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1279 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1280 last_pdu_end_us = 0U;
1281
1282 #else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1283 nrf_timer_task_trigger(SW_SWITCH_TIMER, NRF_TIMER_TASK_CLEAR);
1284 SW_SWITCH_TIMER->MODE = 0;
1285 SW_SWITCH_TIMER->PRESCALER = 4;
1286 SW_SWITCH_TIMER->BITMODE = 0; /* 16 bit */
1287 /* FIXME: start along with EVENT_TIMER, to save power */
1288 nrf_timer_task_trigger(SW_SWITCH_TIMER, NRF_TIMER_TASK_START);
1289 #endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1290
1291 hal_sw_switch_timer_clear_ppi_config();
1292
1293 #if !defined(CONFIG_BT_CTLR_PHY_CODED) || \
1294 !defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
1295 /* Software switch group's disable PPI can be configured one time here
1296 * at timer setup when only 1M and/or 2M is supported.
1297 */
1298 hal_radio_group_task_disable_ppi_setup();
1299
1300 #else /* CONFIG_BT_CTLR_PHY_CODED && CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1301 /* Software switch group's disable PPI needs to be configured at every
1302 * sw_switch() as they depend on the actual PHYs used in TX/RX mode.
1303 */
1304 #endif /* CONFIG_BT_CTLR_PHY_CODED && CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1305 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1306
1307 return remainder;
1308 }
1309
radio_tmr_start_tick(uint8_t trx,uint32_t tick)1310 uint32_t radio_tmr_start_tick(uint8_t trx, uint32_t tick)
1311 {
1312 uint32_t remainder_us;
1313
1314 nrf_timer_task_trigger(EVENT_TIMER, NRF_TIMER_TASK_STOP);
1315 nrf_timer_task_trigger(EVENT_TIMER, NRF_TIMER_TASK_CLEAR);
1316
1317 /* Setup compare event with min. 1 us offset */
1318 remainder_us = 1;
1319 nrf_timer_cc_set(EVENT_TIMER, 0, remainder_us);
1320
1321 nrf_rtc_cc_set(NRF_RTC0, 2, tick);
1322 nrf_rtc_event_enable(NRF_RTC0, RTC_EVTENSET_COMPARE2_Msk);
1323
1324 hal_event_timer_start_ppi_config();
1325 hal_radio_nrf_ppi_channels_enable(BIT(HAL_EVENT_TIMER_START_PPI));
1326
1327 hal_radio_enable_on_tick_ppi_config_and_enable(trx);
1328
1329 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1330 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1331 last_pdu_end_us = 0U;
1332 #endif /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1333 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X)
1334 /* NOTE: Timer clear DPPI configuration is needed only for nRF53
1335 * because of calls to radio_disable() and
1336 * radio_switch_complete_and_disable() inside a radio event call
1337 * hal_radio_sw_switch_disable(), which in the case of nRF53
1338 * cancels the task subscription.
1339 */
1340 /* FIXME: hal_sw_switch_timer_clear_ppi_config() sets both task and
1341 * event. Consider a new interface to only set the task, or
1342 * change the design to not clear task subscription inside a
1343 * radio event but when the radio event is done.
1344 */
1345 hal_sw_switch_timer_clear_ppi_config();
1346 #endif /* CONFIG_SOC_COMPATIBLE_NRF53X */
1347 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1348
1349 return remainder_us;
1350 }
1351
radio_tmr_start_us(uint8_t trx,uint32_t start_us)1352 uint32_t radio_tmr_start_us(uint8_t trx, uint32_t start_us)
1353 {
1354 hal_radio_enable_on_tick_ppi_config_and_enable(trx);
1355
1356 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1357 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1358 last_pdu_end_us = 0U;
1359 #endif /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1360 #if defined(CONFIG_SOC_COMPATIBLE_NRF53X)
1361 /* NOTE: Timer clear DPPI configuration is needed only for nRF53
1362 * because of calls to radio_disable() and
1363 * radio_switch_complete_and_disable() inside a radio event call
1364 * hal_radio_sw_switch_disable(), which in the case of nRF53
1365 * cancels the task subscription.
1366 */
1367 /* FIXME: hal_sw_switch_timer_clear_ppi_config() sets both task and
1368 * event. Consider a new interface to only set the task, or
1369 * change the design to not clear task subscription inside a
1370 * radio event but when the radio event is done.
1371 */
1372 hal_sw_switch_timer_clear_ppi_config();
1373 #endif /* CONFIG_SOC_COMPATIBLE_NRF53X */
1374 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1375
1376 /* start_us could be the current count in the timer */
1377 uint32_t now_us = start_us;
1378
1379 /* Setup PPI while determining the latency in doing so */
1380 do {
1381 /* Set start to be, now plus the determined latency */
1382 start_us = (now_us << 1) - start_us;
1383
1384 /* Setup compare event with min. 1 us offset */
1385 nrf_timer_event_clear(EVENT_TIMER, NRF_TIMER_EVENT_COMPARE0);
1386 nrf_timer_cc_set(EVENT_TIMER, 0, start_us + 1U);
1387
1388 /* Capture the current time */
1389 nrf_timer_task_trigger(EVENT_TIMER,
1390 HAL_EVENT_TIMER_SAMPLE_TASK);
1391
1392 now_us = EVENT_TIMER->CC[HAL_EVENT_TIMER_SAMPLE_CC_OFFSET];
1393 } while ((now_us > start_us) && (EVENT_TIMER->EVENTS_COMPARE[0] == 0U));
1394
1395 return start_us + 1U;
1396 }
1397
radio_tmr_start_now(uint8_t trx)1398 uint32_t radio_tmr_start_now(uint8_t trx)
1399 {
1400 uint32_t start_us;
1401
1402 /* PPI/DPPI configuration will be done in radio_tmr_start_us() */
1403
1404 /* Capture the current time */
1405 nrf_timer_task_trigger(EVENT_TIMER, HAL_EVENT_TIMER_SAMPLE_TASK);
1406 start_us = EVENT_TIMER->CC[HAL_EVENT_TIMER_SAMPLE_CC_OFFSET];
1407
1408 /* Setup radio start at current time */
1409 start_us = radio_tmr_start_us(trx, start_us);
1410
1411 return start_us;
1412 }
1413
radio_tmr_start_get(void)1414 uint32_t radio_tmr_start_get(void)
1415 {
1416 return nrf_rtc_cc_get(NRF_RTC0, 2);
1417 }
1418
radio_tmr_stop(void)1419 void radio_tmr_stop(void)
1420 {
1421 nrf_timer_task_trigger(EVENT_TIMER, NRF_TIMER_TASK_STOP);
1422 nrf_timer_task_trigger(EVENT_TIMER, NRF_TIMER_TASK_SHUTDOWN);
1423
1424 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
1425 nrf_timer_task_trigger(SW_SWITCH_TIMER, NRF_TIMER_TASK_STOP);
1426 nrf_timer_task_trigger(SW_SWITCH_TIMER, NRF_TIMER_TASK_SHUTDOWN);
1427 #endif /* !CONFIG_BT_CTLR_TIFS_HW */
1428 }
1429
radio_tmr_hcto_configure(uint32_t hcto)1430 void radio_tmr_hcto_configure(uint32_t hcto)
1431 {
1432 nrf_timer_cc_set(EVENT_TIMER, 1, hcto);
1433
1434 hal_radio_recv_timeout_cancel_ppi_config();
1435 hal_radio_disable_on_hcto_ppi_config();
1436 hal_radio_nrf_ppi_channels_enable(
1437 BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) |
1438 BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI));
1439 }
1440
radio_tmr_aa_capture(void)1441 void radio_tmr_aa_capture(void)
1442 {
1443 hal_radio_ready_time_capture_ppi_config();
1444 hal_radio_recv_timeout_cancel_ppi_config();
1445 hal_radio_nrf_ppi_channels_enable(
1446 BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) |
1447 BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI));
1448 }
1449
radio_tmr_aa_get(void)1450 uint32_t radio_tmr_aa_get(void)
1451 {
1452 return EVENT_TIMER->CC[1];
1453 }
1454
1455 static uint32_t radio_tmr_aa;
1456
radio_tmr_aa_save(uint32_t aa)1457 void radio_tmr_aa_save(uint32_t aa)
1458 {
1459 radio_tmr_aa = aa;
1460 }
1461
radio_tmr_aa_restore(void)1462 uint32_t radio_tmr_aa_restore(void)
1463 {
1464 /* NOTE: we dont need to restore for now, but return the saved value. */
1465 return radio_tmr_aa;
1466 }
1467
radio_tmr_ready_get(void)1468 uint32_t radio_tmr_ready_get(void)
1469 {
1470 return EVENT_TIMER->CC[0];
1471 }
1472
1473 static uint32_t radio_tmr_ready;
1474
radio_tmr_ready_save(uint32_t ready)1475 void radio_tmr_ready_save(uint32_t ready)
1476 {
1477 radio_tmr_ready = ready;
1478 }
1479
radio_tmr_ready_restore(void)1480 uint32_t radio_tmr_ready_restore(void)
1481 {
1482 return radio_tmr_ready;
1483 }
1484
radio_tmr_end_capture(void)1485 void radio_tmr_end_capture(void)
1486 {
1487 /* NOTE: nRF5340 for single timer configuration shares the DPPI channel being triggered
1488 * by Radio End for End time capture and sw_switch DPPI channel toggling hence
1489 * always need to capture End time. Hence, the below code is present in
1490 * hal_sw_switch_timer_clear_ppi_config() and sw_switch(). There is no need to
1491 * configure the channel again in this function.
1492 */
1493 #if !defined(CONFIG_SOC_COMPATIBLE_NRF53X) || \
1494 (defined(CONFIG_SOC_COMPATIBLE_NRF53X) && !defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER))
1495 hal_radio_end_time_capture_ppi_config();
1496 hal_radio_nrf_ppi_channels_enable(BIT(HAL_RADIO_END_TIME_CAPTURE_PPI));
1497 #endif /* !CONFIG_SOC_COMPATIBLE_NRF53X ||
1498 * (CONFIG_SOC_COMPATIBLE_NRF53X && !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1499 */
1500 }
1501
radio_tmr_end_get(void)1502 uint32_t radio_tmr_end_get(void)
1503 {
1504 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1505 return last_pdu_end_us;
1506 #else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1507 return EVENT_TIMER->CC[2];
1508 #endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1509 }
1510
radio_tmr_tifs_base_get(void)1511 uint32_t radio_tmr_tifs_base_get(void)
1512 {
1513 return radio_tmr_end_get();
1514 }
1515
1516 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1517 static uint32_t tmr_sample_val;
1518 #endif /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1519
radio_tmr_sample(void)1520 void radio_tmr_sample(void)
1521 {
1522 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1523 uint32_t cc;
1524
1525 cc = EVENT_TIMER->CC[HAL_EVENT_TIMER_SAMPLE_CC_OFFSET];
1526 nrf_timer_task_trigger(EVENT_TIMER, HAL_EVENT_TIMER_SAMPLE_TASK);
1527
1528 tmr_sample_val = EVENT_TIMER->CC[HAL_EVENT_TIMER_SAMPLE_CC_OFFSET];
1529 EVENT_TIMER->CC[HAL_EVENT_TIMER_SAMPLE_CC_OFFSET] = cc;
1530
1531 #else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1532 nrf_timer_task_trigger(EVENT_TIMER, HAL_EVENT_TIMER_SAMPLE_TASK);
1533 #endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1534 }
1535
radio_tmr_sample_get(void)1536 uint32_t radio_tmr_sample_get(void)
1537 {
1538 #if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
1539 return tmr_sample_val;
1540 #else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1541 return EVENT_TIMER->CC[HAL_EVENT_TIMER_SAMPLE_CC_OFFSET];
1542 #endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
1543 }
1544
1545 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN) || \
1546 defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
1547 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN)
radio_gpio_pa_setup(void)1548 void radio_gpio_pa_setup(void)
1549 {
1550 NRF_GPIOTE->CONFIG[HAL_PALNA_GPIOTE_CHAN] =
1551 (GPIOTE_CONFIG_MODE_Task <<
1552 GPIOTE_CONFIG_MODE_Pos) |
1553 (NRF_GPIO_PA_PSEL <<
1554 GPIOTE_CONFIG_PSEL_Pos) |
1555 (GPIOTE_CONFIG_POLARITY_Toggle <<
1556 GPIOTE_CONFIG_POLARITY_Pos) |
1557 (OUTINIT_INACTIVE(NRF_GPIO_PA_FLAGS) <<
1558 GPIOTE_CONFIG_OUTINIT_Pos);
1559
1560 #if defined(HAL_RADIO_FEM_IS_NRF21540)
1561 hal_pa_ppi_setup();
1562 radio_gpio_pdn_setup();
1563 radio_gpio_csn_setup();
1564 #endif
1565 }
1566 #endif /* HAL_RADIO_GPIO_HAVE_PA_PIN */
1567
1568 #if defined(HAL_RADIO_GPIO_HAVE_LNA_PIN)
radio_gpio_lna_setup(void)1569 void radio_gpio_lna_setup(void)
1570 {
1571 NRF_GPIOTE->CONFIG[HAL_PALNA_GPIOTE_CHAN] =
1572 (GPIOTE_CONFIG_MODE_Task <<
1573 GPIOTE_CONFIG_MODE_Pos) |
1574 (NRF_GPIO_LNA_PSEL <<
1575 GPIOTE_CONFIG_PSEL_Pos) |
1576 (GPIOTE_CONFIG_POLARITY_Toggle <<
1577 GPIOTE_CONFIG_POLARITY_Pos) |
1578 (OUTINIT_INACTIVE(NRF_GPIO_LNA_FLAGS) <<
1579 GPIOTE_CONFIG_OUTINIT_Pos);
1580
1581 #if defined(HAL_RADIO_FEM_IS_NRF21540)
1582 hal_lna_ppi_setup();
1583 radio_gpio_pdn_setup();
1584 radio_gpio_csn_setup();
1585 #endif
1586 }
1587
radio_gpio_pdn_setup(void)1588 void radio_gpio_pdn_setup(void)
1589 {
1590 /* Note: the pdn-gpios property is optional. */
1591 #if defined(NRF_GPIO_PDN)
1592 NRF_GPIOTE->CONFIG[HAL_PDN_GPIOTE_CHAN] =
1593 (GPIOTE_CONFIG_MODE_Task <<
1594 GPIOTE_CONFIG_MODE_Pos) |
1595 (NRF_GPIO_PDN_PSEL <<
1596 GPIOTE_CONFIG_PSEL_Pos) |
1597 (GPIOTE_CONFIG_POLARITY_Toggle <<
1598 GPIOTE_CONFIG_POLARITY_Pos) |
1599 (OUTINIT_INACTIVE(NRF_GPIO_PDN_FLAGS) <<
1600 GPIOTE_CONFIG_OUTINIT_Pos);
1601 #endif /* NRF_GPIO_PDN_PIN */
1602 }
1603
radio_gpio_csn_setup(void)1604 void radio_gpio_csn_setup(void)
1605 {
1606 /* Note: the spi-if property is optional. */
1607 #if defined(NRF_GPIO_CSN_PIN)
1608 NRF_GPIOTE->CONFIG[HAL_CSN_GPIOTE_CHAN] =
1609 (GPIOTE_CONFIG_MODE_Task <<
1610 GPIOTE_CONFIG_MODE_Pos) |
1611 (NRF_GPIO_CSN_PSEL <<
1612 GPIOTE_CONFIG_PSEL_Pos) |
1613 (GPIOTE_CONFIG_POLARITY_Toggle <<
1614 GPIOTE_CONFIG_POLARITY_Pos) |
1615 (OUTINIT_INACTIVE(NRF_GPIO_CSN_FLAGS) <<
1616 GPIOTE_CONFIG_OUTINIT_Pos);
1617 #endif /* NRF_GPIO_CSN_PIN */
1618 }
1619
radio_gpio_lna_on(void)1620 void radio_gpio_lna_on(void)
1621 {
1622 if (ACTIVE_LOW(NRF_GPIO_LNA_FLAGS)) {
1623 NRF_GPIO_LNA->OUTCLR = BIT(NRF_GPIO_LNA_PIN);
1624 } else {
1625 NRF_GPIO_LNA->OUTSET = BIT(NRF_GPIO_LNA_PIN);
1626 }
1627 }
1628
radio_gpio_lna_off(void)1629 void radio_gpio_lna_off(void)
1630 {
1631 if (ACTIVE_LOW(NRF_GPIO_LNA_FLAGS)) {
1632 NRF_GPIO_LNA->OUTSET = BIT(NRF_GPIO_LNA_PIN);
1633 } else {
1634 NRF_GPIO_LNA->OUTCLR = BIT(NRF_GPIO_LNA_PIN);
1635 }
1636 }
1637 #endif /* HAL_RADIO_GPIO_HAVE_LNA_PIN */
1638
radio_gpio_pa_lna_enable(uint32_t trx_us)1639 void radio_gpio_pa_lna_enable(uint32_t trx_us)
1640 {
1641 nrf_timer_cc_set(EVENT_TIMER, 2, trx_us);
1642 #if defined(HAL_RADIO_FEM_IS_NRF21540) && DT_NODE_HAS_PROP(FEM_NODE, pdn_gpios)
1643 nrf_timer_cc_set(EVENT_TIMER, 3, (trx_us - NRF_GPIO_PDN_OFFSET));
1644 hal_radio_nrf_ppi_channels_enable(BIT(HAL_ENABLE_PALNA_PPI) |
1645 BIT(HAL_DISABLE_PALNA_PPI) |
1646 BIT(HAL_ENABLE_FEM_PPI) |
1647 BIT(HAL_DISABLE_FEM_PPI));
1648 #else
1649 hal_radio_nrf_ppi_channels_enable(BIT(HAL_ENABLE_PALNA_PPI) |
1650 BIT(HAL_DISABLE_PALNA_PPI));
1651 #endif
1652 }
1653
radio_gpio_pa_lna_disable(void)1654 void radio_gpio_pa_lna_disable(void)
1655 {
1656 #if defined(HAL_RADIO_FEM_IS_NRF21540)
1657 hal_radio_nrf_ppi_channels_disable(BIT(HAL_ENABLE_PALNA_PPI) |
1658 BIT(HAL_DISABLE_PALNA_PPI) |
1659 BIT(HAL_ENABLE_FEM_PPI) |
1660 BIT(HAL_DISABLE_FEM_PPI));
1661 NRF_GPIOTE->CONFIG[HAL_PALNA_GPIOTE_CHAN] = 0;
1662 NRF_GPIOTE->CONFIG[HAL_PDN_GPIOTE_CHAN] = 0;
1663 NRF_GPIOTE->CONFIG[HAL_CSN_GPIOTE_CHAN] = 0;
1664 #else
1665 hal_radio_nrf_ppi_channels_disable(BIT(HAL_ENABLE_PALNA_PPI) |
1666 BIT(HAL_DISABLE_PALNA_PPI));
1667 NRF_GPIOTE->CONFIG[HAL_PALNA_GPIOTE_CHAN] = 0;
1668 #endif
1669 }
1670 #endif /* HAL_RADIO_GPIO_HAVE_PA_PIN || HAL_RADIO_GPIO_HAVE_LNA_PIN */
1671
1672 static uint8_t MALIGN(4) _ccm_scratch[(HAL_RADIO_PDU_LEN_MAX - 4) + 16];
1673
radio_ccm_ext_rx_pkt_set(struct ccm * cnf,uint8_t phy,uint8_t pdu_type,void * pkt)1674 static void *radio_ccm_ext_rx_pkt_set(struct ccm *cnf, uint8_t phy, uint8_t pdu_type, void *pkt)
1675 {
1676 uint32_t mode;
1677
1678 NRF_CCM->ENABLE = CCM_ENABLE_ENABLE_Disabled;
1679 NRF_CCM->ENABLE = CCM_ENABLE_ENABLE_Enabled;
1680 mode = (CCM_MODE_MODE_Decryption << CCM_MODE_MODE_Pos) &
1681 CCM_MODE_MODE_Msk;
1682
1683 #if !defined(CONFIG_SOC_SERIES_NRF51X)
1684 /* Enable CCM support for 8-bit length field PDUs. */
1685 mode |= (CCM_MODE_LENGTH_Extended << CCM_MODE_LENGTH_Pos) &
1686 CCM_MODE_LENGTH_Msk;
1687
1688 /* Select CCM data rate based on current PHY in use. */
1689 switch (phy) {
1690 default:
1691 case PHY_1M:
1692 mode |= (CCM_MODE_DATARATE_1Mbit <<
1693 CCM_MODE_DATARATE_Pos) &
1694 CCM_MODE_DATARATE_Msk;
1695
1696 if (false) {
1697
1698 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
1699 } else if (pdu_type == RADIO_PKT_CONF_PDU_TYPE_DC) {
1700 /* When direction finding CTE receive feature is enabled then on-the-fly
1701 * PDU parsing for CTEInfo is always done. In such situation, the CCM
1702 * TASKS_CRYPT must be started with short delay. That give the Radio time
1703 * to store received bits in shared memory.
1704 */
1705 radio_bc_configure(CCM_TASKS_CRYPT_DELAY_BITS);
1706 radio_bc_status_reset();
1707 hal_trigger_crypt_by_bcmatch_ppi_config();
1708 hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_DELAY_PPI));
1709 #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
1710 } else {
1711 hal_trigger_crypt_ppi_config();
1712 hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_PPI));
1713 }
1714 break;
1715
1716 case PHY_2M:
1717 mode |= (CCM_MODE_DATARATE_2Mbit <<
1718 CCM_MODE_DATARATE_Pos) &
1719 CCM_MODE_DATARATE_Msk;
1720
1721 hal_trigger_crypt_ppi_config();
1722 hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_PPI));
1723
1724 break;
1725
1726 #if defined(CONFIG_BT_CTLR_PHY_CODED)
1727 #if defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED)
1728 case PHY_CODED:
1729 mode |= (CCM_MODE_DATARATE_125Kbps <<
1730 CCM_MODE_DATARATE_Pos) &
1731 CCM_MODE_DATARATE_Msk;
1732
1733 NRF_CCM->RATEOVERRIDE =
1734 (CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps <<
1735 CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) &
1736 CCM_RATEOVERRIDE_RATEOVERRIDE_Msk;
1737
1738 hal_trigger_rateoverride_ppi_config();
1739 hal_radio_nrf_ppi_channels_enable(
1740 BIT(HAL_TRIGGER_RATEOVERRIDE_PPI));
1741
1742 hal_trigger_crypt_ppi_config();
1743 hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_CRYPT_PPI));
1744
1745 break;
1746 #endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
1747 #endif /* CONFIG_BT_CTLR_PHY_CODED */
1748 }
1749 #endif /* !CONFIG_SOC_SERIES_NRF51X */
1750
1751 #if !defined(CONFIG_SOC_SERIES_NRF51X) && \
1752 !defined(CONFIG_SOC_NRF52832) && \
1753 (!defined(CONFIG_BT_CTLR_DATA_LENGTH_MAX) || \
1754 (CONFIG_BT_CTLR_DATA_LENGTH_MAX < ((HAL_RADIO_PDU_LEN_MAX) - 4U)))
1755 uint8_t max_len = (NRF_RADIO->PCNF1 & RADIO_PCNF1_MAXLEN_Msk) >>
1756 RADIO_PCNF1_MAXLEN_Pos;
1757
1758 /* MAXPACKETSIZE value 0x001B (27) - 0x00FB (251) bytes */
1759 NRF_CCM->MAXPACKETSIZE = max_len - 4U;
1760 #endif
1761
1762 #if defined(CONFIG_HAS_HW_NRF_CCM_HEADERMASK)
1763 switch (pdu_type) {
1764 case RADIO_PKT_CONF_PDU_TYPE_BIS:
1765 NRF_CCM->HEADERMASK = 0xC3; /* mask CSSN and CSTF */
1766 break;
1767 case RADIO_PKT_CONF_PDU_TYPE_CIS:
1768 NRF_CCM->HEADERMASK = 0xA3; /* mask SN, NESN, CIE and NPI */
1769 break;
1770 default:
1771 /* Using default reset value of HEADERMASK */
1772 NRF_CCM->HEADERMASK = 0xE3; /* mask SN, NESN and MD */
1773 break;
1774 }
1775 #endif /* CONFIG_HAS_HW_NRF_CCM_HEADERMASK */
1776
1777 NRF_CCM->MODE = mode;
1778 NRF_CCM->CNFPTR = (uint32_t)cnf;
1779 NRF_CCM->INPTR = (uint32_t)_pkt_scratch;
1780 NRF_CCM->OUTPTR = (uint32_t)pkt;
1781 NRF_CCM->SCRATCHPTR = (uint32_t)_ccm_scratch;
1782 NRF_CCM->SHORTS = 0;
1783 nrf_ccm_event_clear(NRF_CCM, NRF_CCM_EVENT_ENDKSGEN);
1784 nrf_ccm_event_clear(NRF_CCM, NRF_CCM_EVENT_ENDCRYPT);
1785 nrf_ccm_event_clear(NRF_CCM, NRF_CCM_EVENT_ERROR);
1786
1787 nrf_ccm_task_trigger(NRF_CCM, NRF_CCM_TASK_KSGEN);
1788
1789 return _pkt_scratch;
1790 }
1791
radio_ccm_rx_pkt_set(struct ccm * cnf,uint8_t phy,void * pkt)1792 void *radio_ccm_rx_pkt_set(struct ccm *cnf, uint8_t phy, void *pkt)
1793 {
1794 return radio_ccm_ext_rx_pkt_set(cnf, phy, RADIO_PKT_CONF_PDU_TYPE_DC, pkt);
1795 }
1796
radio_ccm_iso_rx_pkt_set(struct ccm * cnf,uint8_t phy,uint8_t pdu_type,void * pkt)1797 void *radio_ccm_iso_rx_pkt_set(struct ccm *cnf, uint8_t phy, uint8_t pdu_type, void *pkt)
1798 {
1799 return radio_ccm_ext_rx_pkt_set(cnf, phy, pdu_type, pkt);
1800 }
1801
radio_ccm_ext_tx_pkt_set(struct ccm * cnf,uint8_t pdu_type,void * pkt)1802 static void *radio_ccm_ext_tx_pkt_set(struct ccm *cnf, uint8_t pdu_type, void *pkt)
1803 {
1804 uint32_t mode;
1805
1806 NRF_CCM->ENABLE = CCM_ENABLE_ENABLE_Disabled;
1807 NRF_CCM->ENABLE = CCM_ENABLE_ENABLE_Enabled;
1808 mode = (CCM_MODE_MODE_Encryption << CCM_MODE_MODE_Pos) &
1809 CCM_MODE_MODE_Msk;
1810 #if defined(CONFIG_SOC_COMPATIBLE_NRF52X) || defined(CONFIG_SOC_COMPATIBLE_NRF53X)
1811 /* Enable CCM support for 8-bit length field PDUs. */
1812 mode |= (CCM_MODE_LENGTH_Extended << CCM_MODE_LENGTH_Pos) &
1813 CCM_MODE_LENGTH_Msk;
1814
1815 /* NOTE: use fastest data rate as tx data needs to be prepared before
1816 * radio Tx on any PHY.
1817 */
1818 mode |= (CCM_MODE_DATARATE_2Mbit << CCM_MODE_DATARATE_Pos) &
1819 CCM_MODE_DATARATE_Msk;
1820 #endif
1821
1822 #if !defined(CONFIG_SOC_SERIES_NRF51X) && \
1823 !defined(CONFIG_SOC_NRF52832) && \
1824 (!defined(CONFIG_BT_CTLR_DATA_LENGTH_MAX) || \
1825 (CONFIG_BT_CTLR_DATA_LENGTH_MAX < ((HAL_RADIO_PDU_LEN_MAX) - 4)))
1826 uint8_t max_len = (NRF_RADIO->PCNF1 & RADIO_PCNF1_MAXLEN_Msk) >>
1827 RADIO_PCNF1_MAXLEN_Pos;
1828
1829 /* MAXPACKETSIZE value 0x001B (27) - 0x00FB (251) bytes */
1830 NRF_CCM->MAXPACKETSIZE = max_len - 4U;
1831 #endif
1832
1833 #if defined(CONFIG_HAS_HW_NRF_CCM_HEADERMASK)
1834 switch (pdu_type) {
1835 case RADIO_PKT_CONF_PDU_TYPE_BIS:
1836 NRF_CCM->HEADERMASK = 0xC3; /* mask CSSN and CSTF */
1837 break;
1838 case RADIO_PKT_CONF_PDU_TYPE_CIS:
1839 NRF_CCM->HEADERMASK = 0xA3; /* mask SN, NESN, CIE and NPI */
1840 break;
1841 default:
1842 /* Using default reset value of HEADERMASK */
1843 NRF_CCM->HEADERMASK = 0xE3; /* mask SN, NESN and MD */
1844 break;
1845 }
1846 #endif /* CONFIG_HAS_HW_NRF_CCM_HEADERMASK */
1847
1848 NRF_CCM->MODE = mode;
1849 NRF_CCM->CNFPTR = (uint32_t)cnf;
1850 NRF_CCM->INPTR = (uint32_t)pkt;
1851 NRF_CCM->OUTPTR = (uint32_t)_pkt_scratch;
1852 NRF_CCM->SCRATCHPTR = (uint32_t)_ccm_scratch;
1853 NRF_CCM->SHORTS = CCM_SHORTS_ENDKSGEN_CRYPT_Msk;
1854 nrf_ccm_event_clear(NRF_CCM, NRF_CCM_EVENT_ENDKSGEN);
1855 nrf_ccm_event_clear(NRF_CCM, NRF_CCM_EVENT_ENDCRYPT);
1856 nrf_ccm_event_clear(NRF_CCM, NRF_CCM_EVENT_ERROR);
1857
1858 nrf_ccm_task_trigger(NRF_CCM, NRF_CCM_TASK_KSGEN);
1859
1860 return _pkt_scratch;
1861 }
1862
radio_ccm_tx_pkt_set(struct ccm * cnf,void * pkt)1863 void *radio_ccm_tx_pkt_set(struct ccm *cnf, void *pkt)
1864 {
1865 return radio_ccm_ext_tx_pkt_set(cnf, RADIO_PKT_CONF_PDU_TYPE_DC, pkt);
1866 }
1867
radio_ccm_iso_tx_pkt_set(struct ccm * cnf,uint8_t pdu_type,void * pkt)1868 void *radio_ccm_iso_tx_pkt_set(struct ccm *cnf, uint8_t pdu_type, void *pkt)
1869 {
1870 return radio_ccm_ext_tx_pkt_set(cnf, pdu_type, pkt);
1871 }
1872
radio_ccm_is_done(void)1873 uint32_t radio_ccm_is_done(void)
1874 {
1875 nrf_ccm_int_enable(NRF_CCM, CCM_INTENSET_ENDCRYPT_Msk);
1876 while (NRF_CCM->EVENTS_ENDCRYPT == 0) {
1877 cpu_sleep();
1878 }
1879 nrf_ccm_int_disable(NRF_CCM, CCM_INTENCLR_ENDCRYPT_Msk);
1880 NVIC_ClearPendingIRQ(nrfx_get_irq_number(NRF_CCM));
1881
1882 return (NRF_CCM->EVENTS_ERROR == 0);
1883 }
1884
radio_ccm_mic_is_valid(void)1885 uint32_t radio_ccm_mic_is_valid(void)
1886 {
1887 return (NRF_CCM->MICSTATUS != 0);
1888 }
1889
1890 #if defined(CONFIG_BT_CTLR_PRIVACY)
1891 static uint8_t MALIGN(4) _aar_scratch[3];
1892
radio_ar_configure(uint32_t nirk,void * irk,uint8_t flags)1893 void radio_ar_configure(uint32_t nirk, void *irk, uint8_t flags)
1894 {
1895 uint32_t addrptr;
1896 uint8_t bcc;
1897 uint8_t phy;
1898
1899 /* Flags provide hint on how to setup AAR:
1900 * ....Xb - legacy PDU
1901 * ...X.b - extended PDU
1902 * XXX..b = RX PHY
1903 * 00000b = default case mapped to 00101b (legacy, 1M)
1904 *
1905 * If neither legacy not extended bit is set, legacy PDU is selected for
1906 * 1M PHY and extended PDU otherwise.
1907 */
1908
1909 phy = flags >> 2;
1910
1911 /* Check if extended PDU or non-1M and not legacy PDU */
1912 if (IS_ENABLED(CONFIG_BT_CTLR_ADV_EXT) &&
1913 ((flags & BIT(1)) || (!(flags & BIT(0)) && (phy > PHY_1M)))) {
1914 addrptr = NRF_RADIO->PACKETPTR + 1;
1915 bcc = 80;
1916 } else {
1917 addrptr = NRF_RADIO->PACKETPTR - 1;
1918 bcc = 64;
1919 }
1920
1921 /* For Coded PHY adjust for CI and TERM1 */
1922 if (IS_ENABLED(CONFIG_BT_CTLR_PHY_CODED) && (phy == PHY_CODED)) {
1923 bcc += 5;
1924 }
1925
1926 NRF_AAR->ENABLE = (AAR_ENABLE_ENABLE_Enabled << AAR_ENABLE_ENABLE_Pos) &
1927 AAR_ENABLE_ENABLE_Msk;
1928 NRF_AAR->NIRK = nirk;
1929 NRF_AAR->IRKPTR = (uint32_t)irk;
1930 NRF_AAR->ADDRPTR = addrptr;
1931 NRF_AAR->SCRATCHPTR = (uint32_t)&_aar_scratch[0];
1932
1933 nrf_aar_event_clear(NRF_AAR, NRF_AAR_EVENT_END);
1934 nrf_aar_event_clear(NRF_AAR, NRF_AAR_EVENT_RESOLVED);
1935 nrf_aar_event_clear(NRF_AAR, NRF_AAR_EVENT_NOTRESOLVED);
1936
1937 radio_bc_configure(bcc);
1938 radio_bc_status_reset();
1939
1940 hal_trigger_aar_ppi_config();
1941 hal_radio_nrf_ppi_channels_enable(BIT(HAL_TRIGGER_AAR_PPI));
1942 }
1943
radio_ar_match_get(void)1944 uint32_t radio_ar_match_get(void)
1945 {
1946 return NRF_AAR->STATUS;
1947 }
1948
radio_ar_status_reset(void)1949 void radio_ar_status_reset(void)
1950 {
1951 radio_bc_status_reset();
1952
1953 NRF_AAR->ENABLE = (AAR_ENABLE_ENABLE_Disabled << AAR_ENABLE_ENABLE_Pos) &
1954 AAR_ENABLE_ENABLE_Msk;
1955
1956 hal_radio_nrf_ppi_channels_disable(BIT(HAL_TRIGGER_AAR_PPI));
1957 }
1958
radio_ar_has_match(void)1959 uint32_t radio_ar_has_match(void)
1960 {
1961 if (!radio_bc_has_match()) {
1962 return 0U;
1963 }
1964
1965 nrf_aar_int_enable(NRF_AAR, AAR_INTENSET_END_Msk);
1966
1967 while (NRF_AAR->EVENTS_END == 0U) {
1968 cpu_sleep();
1969 }
1970
1971 nrf_aar_int_disable(NRF_AAR, AAR_INTENCLR_END_Msk);
1972
1973 NVIC_ClearPendingIRQ(nrfx_get_irq_number(NRF_AAR));
1974
1975 if (NRF_AAR->EVENTS_RESOLVED && !NRF_AAR->EVENTS_NOTRESOLVED) {
1976 return 1U;
1977 }
1978
1979 return 0U;
1980 }
1981
radio_ar_resolve(const uint8_t * addr)1982 uint8_t radio_ar_resolve(const uint8_t *addr)
1983 {
1984 uint8_t retval;
1985
1986 NRF_AAR->ENABLE = (AAR_ENABLE_ENABLE_Enabled << AAR_ENABLE_ENABLE_Pos) &
1987 AAR_ENABLE_ENABLE_Msk;
1988
1989 NRF_AAR->ADDRPTR = (uint32_t)addr - 3;
1990
1991 nrf_aar_event_clear(NRF_AAR, NRF_AAR_EVENT_END);
1992 nrf_aar_event_clear(NRF_AAR, NRF_AAR_EVENT_RESOLVED);
1993 nrf_aar_event_clear(NRF_AAR, NRF_AAR_EVENT_NOTRESOLVED);
1994
1995 NVIC_ClearPendingIRQ(nrfx_get_irq_number(NRF_AAR));
1996
1997 nrf_aar_int_enable(NRF_AAR, AAR_INTENSET_END_Msk);
1998
1999 nrf_aar_task_trigger(NRF_AAR, NRF_AAR_TASK_START);
2000
2001 while (NRF_AAR->EVENTS_END == 0) {
2002 cpu_sleep();
2003 }
2004
2005 nrf_aar_int_disable(NRF_AAR, AAR_INTENCLR_END_Msk);
2006
2007 NVIC_ClearPendingIRQ(nrfx_get_irq_number(NRF_AAR));
2008
2009 retval = (NRF_AAR->EVENTS_RESOLVED && !NRF_AAR->EVENTS_NOTRESOLVED) ?
2010 1U : 0U;
2011
2012 NRF_AAR->ENABLE = (AAR_ENABLE_ENABLE_Disabled << AAR_ENABLE_ENABLE_Pos) &
2013 AAR_ENABLE_ENABLE_Msk;
2014
2015 return retval;
2016
2017 }
2018 #endif /* CONFIG_BT_CTLR_PRIVACY */
2019
2020 #if defined(CONFIG_BT_CTLR_DF_SUPPORT) && !defined(CONFIG_ZTEST)
2021 /* @brief Function configures CTE inline register to start sampling of CTE
2022 * according to information parsed from CTEInfo field of received PDU.
2023 *
2024 * @param[in] cte_info_in_s1 Informs where to expect CTEInfo field in PDU:
2025 * in S1 for data pdu, not in S1 for adv. PDU
2026 */
radio_df_cte_inline_set_enabled(bool cte_info_in_s1)2027 void radio_df_cte_inline_set_enabled(bool cte_info_in_s1)
2028 {
2029 const nrf_radio_cteinline_conf_t inline_conf = {
2030 .enable = true,
2031 /* Indicates whether CTEInfo is in S1 byte or not. */
2032 .info_in_s1 = cte_info_in_s1,
2033 /* Enable or disable switching and sampling when CRC is not OK. */
2034 #if defined(CONFIG_BT_CTLR_DF_SAMPLE_CTE_FOR_PDU_WITH_BAD_CRC)
2035 .err_handling = true,
2036 #else
2037 .err_handling = false,
2038 #endif /* CONFIG_BT_CTLR_DF_SAMPLE_CTE_FOR_PDU_WITH_BAD_CRC */
2039 /* Maximum range of CTE time. 20 * 8us according to BT spec.*/
2040 .time_range = NRF_RADIO_CTEINLINE_TIME_RANGE_20,
2041 /* Spacing between samples for 1us AoD or AoA is set to 2us. */
2042 .rx1us = NRF_RADIO_CTEINLINE_RX_MODE_2US,
2043 /* Spacing between samples for 2us AoD or AoA is set to 4us. */
2044 .rx2us = NRF_RADIO_CTEINLINE_RX_MODE_4US,
2045 /* S0 bit pattern to match all types of adv. PDUs or CP bit in conn PDU*/
2046 .s0_pattern = (cte_info_in_s1 ? DF_S0_MASK_CP_BIT_IN_DATA_CHANNEL_PDU :
2047 DF_S0_ALLOW_ALL_PER_ADV_PDU),
2048 /* S0 bit mask set to don't match any bit in SO octet or match CP bit in conn PDU */
2049 .s0_mask = (cte_info_in_s1 ? DF_S0_MASK_CP_BIT_IN_DATA_CHANNEL_PDU :
2050 DF_S0_ALLOW_ALL_PER_ADV_PDU)
2051 };
2052
2053 nrf_radio_cteinline_configure(NRF_RADIO, &inline_conf);
2054 }
2055 #endif /* CONFIG_BT_CTLR_DF_SUPPORT && !CONFIG_ZTEST */
2056
