1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_mmdvsq.h"
10
11 /*******************************************************************************
12 * Code
13 ******************************************************************************/
14
MMDVSQ_GetDivideRemainder(MMDVSQ_Type * base,int32_t dividend,int32_t divisor,bool isUnsigned)15 int32_t MMDVSQ_GetDivideRemainder(MMDVSQ_Type *base, int32_t dividend, int32_t divisor, bool isUnsigned)
16 {
17 uint32_t temp = 0;
18
19 temp = base->CSR;
20 temp &= ~(MMDVSQ_CSR_USGN_MASK | MMDVSQ_CSR_REM_MASK);
21 /* Prepare setting for calculation */
22 temp |= MMDVSQ_CSR_USGN(isUnsigned) | MMDVSQ_CSR_REM(true);
23 /* Write setting to CSR register */
24 base->CSR = temp;
25 /* Write dividend to DEND register */
26 base->DEND = dividend;
27 /* Write divisor to DSOR register and start calculation if Fast-Start is enabled */
28 base->DSOR = divisor;
29 /* Start calculation by writing 1 to SRT bit in case Fast-Start is disabled */
30 base->CSR |= MMDVSQ_CSR_SRT_MASK;
31 /* Return remainder, if divide-by-zero is enabled and occurred, reading from
32 * RES result is error terminated */
33 return base->RES;
34 }
35
MMDVSQ_GetDivideQuotient(MMDVSQ_Type * base,int32_t dividend,int32_t divisor,bool isUnsigned)36 int32_t MMDVSQ_GetDivideQuotient(MMDVSQ_Type *base, int32_t dividend, int32_t divisor, bool isUnsigned)
37 {
38 uint32_t temp = 0;
39
40 temp = base->CSR;
41 temp &= ~(MMDVSQ_CSR_USGN_MASK | MMDVSQ_CSR_REM_MASK);
42 /* Prepare setting for calculation */
43 temp |= MMDVSQ_CSR_USGN(isUnsigned) | MMDVSQ_CSR_REM(false);
44 /* Write setting mode to CSR register */
45 base->CSR = temp;
46 /* Write dividend to DEND register */
47 base->DEND = dividend;
48 /* Write divisor to DSOR register and start calculation when Fast-Start is enabled */
49 base->DSOR = divisor;
50 /* Start calculation by writing 1 to SRT bit in case Fast-Start is disabled */
51 base->CSR |= MMDVSQ_CSR_SRT_MASK;
52 /* Return quotient, if divide-by-zero is enabled and occurred, reading from
53 * RES result is error terminated */
54 return base->RES;
55 }
56
MMDVSQ_Sqrt(MMDVSQ_Type * base,uint32_t radicand)57 uint16_t MMDVSQ_Sqrt(MMDVSQ_Type *base, uint32_t radicand)
58 {
59 /* Write radicand to RCND register , and start calculation */
60 base->RCND = radicand;
61 /* Return result */
62 return base->RES;
63 }
64
