1/* 2 * Copyright (c) 2022 Renesas Electronics Corporation and/or its affiliates 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6#include <arm/armv8-m.dtsi> 7#include <mem.h> 8#include <freq.h> 9#include <zephyr/dt-bindings/gpio/gpio.h> 10#include <zephyr/dt-bindings/adc/smartbond-adc.h> 11#include <zephyr/dt-bindings/pinctrl/smartbond-pinctrl.h> 12 13/ { 14 chosen { 15 zephyr,entropy = &trng; 16 zephyr,flash-controller = &flash_controller; 17 }; 18 19 cpus: cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu@0 { 24 compatible = "arm,cortex-m33f"; 25 reg = <0>; 26 clock-frequency = <32000000>; 27 }; 28 }; 29 30 crg { 31 osc: osc { 32 rc32k: rc32k { 33 compatible = "renesas,smartbond-lp-osc"; 34 clock-frequency = <DT_FREQ_K(32)>; 35 calibration-interval = <1>; 36 #clock-cells = <0>; 37 status = "okay"; 38 }; 39 xtal32k: xtal32k { 40 compatible = "renesas,smartbond-lp-osc"; 41 clock-frequency = <32768>; 42 settle-time = <8000>; 43 #clock-cells = <0>; 44 status = "disabled"; 45 }; 46 rcx: rcx { 47 compatible = "renesas,smartbond-lp-osc"; 48 clock-frequency = <DT_FREQ_K(15)>; 49 calibration-interval = <1>; 50 #clock-cells = <0>; 51 status = "disabled"; 52 }; 53 rc32m: rc32m { 54 compatible = "fixed-clock"; 55 clock-frequency = <DT_FREQ_M(32)>; 56 #clock-cells = <0>; 57 status = "okay"; 58 }; 59 xtal32m: xtal32m { 60 compatible = "fixed-clock"; 61 clock-frequency = <DT_FREQ_M(32)>; 62 #clock-cells = <0>; 63 status = "disabled"; 64 }; 65 pll: pll { 66 compatible = "fixed-clock"; 67 clock-frequency = <DT_FREQ_M(96)>; 68 #clock-cells = <0>; 69 status = "disabled"; 70 }; 71 }; 72 divn_clk: divn_clk { 73 compatible = "fixed-clock"; 74 clock-frequency = <DT_FREQ_M(32)>; 75 #clock-cells = <0>; 76 status = "okay"; 77 }; 78 sys_clk: sys_clk { 79 compatible = "renesas,smartbond-sys-clk"; 80 status = "okay"; 81 clock-src = <&rc32m>; 82 status = "okay"; 83 }; 84 lp_clk: lp_clk { 85 compatible = "renesas,smartbond-lp-clk"; 86 clock-src = <&rc32k>; 87 status = "okay"; 88 }; 89 }; 90 91 soc { 92 sram0: memory@20000000 { 93 compatible = "mmio-sram"; 94 }; 95 96 qspif: memory@16000000 { 97 compatible = "zephyr,memory-region"; 98 reg = <0x16000000 DT_SIZE_K(32768)>; 99 zephyr,memory-region = "QSPIF"; 100 }; 101 102 flash_controller: flash-controller@38000000 { 103 compatible = "renesas,smartbond-flash-controller"; 104 reg = <0x38000000 0xb0>; 105 106 #address-cells = <1>; 107 #size-cells = <1>; 108 109 read-cs-idle-delay = <50>; 110 erase-cs-idle-delay = <50>; 111 112 flash0: flash@16000000 { 113 compatible = "soc-nv-flash"; 114 erase-block-size = <4096>; 115 write-block-size = <1>; 116 }; 117 }; 118 119 pinctrl: pin-controller@50020a00 { 120 compatible = "renesas,smartbond-pinctrl"; 121 reg = <0x50020a00 0x100>; 122 #address-cells = <1>; 123 #size-cells = <1>; 124 125 gpio0: gpio@50020a00 { 126 compatible = "renesas,smartbond-gpio"; 127 gpio-controller; 128 #gpio-cells = <2>; 129 ngpios = <32>; 130 reg = <0x50020a00 20 131 0x50020a18 128 132 0x50000070 12 133 0x50000114 36>; 134 reg-names = "data", "mode", "latch", "wkup"; 135 interrupts = <38 0>; 136 }; 137 138 gpio1: gpio@50020a04 { 139 compatible = "renesas,smartbond-gpio"; 140 gpio-controller; 141 #gpio-cells = <2>; 142 ngpios = <23>; 143 reg = <0x50020a04 20 144 0x50020a98 92 145 0x5000007c 12 146 0x50000118 36>; 147 reg-names = "data", "mode", "latch", "wkup"; 148 interrupts = <39 0>; 149 }; 150 }; 151 152 wdog: watchdog@50000700 { 153 compatible = "renesas,smartbond-watchdog"; 154 reg = <0x50000700 0x8>; 155 status = "okay"; 156 }; 157 158 timer1: timer@50010200 { 159 compatible = "renesas,smartbond-timer"; 160 reg = <0x50010200 0x300>; 161 clock-src = <&lp_clk>; 162 interrupts = <16 0>; 163 prescaler = <1>; 164 status = "disabled"; 165 }; 166 167 timer2: timer@50010300 { 168 compatible = "renesas,smartbond-timer"; 169 reg = <0x50010300 0x300>; 170 clock-src = <&divn_clk>; 171 interrupts = <17 0>; 172 prescaler = <32>; 173 status = "disabled"; 174 }; 175 176 timer3: timer@50040a00 { 177 compatible = "renesas,smartbond-timer"; 178 reg = <0x50040a00 0x300>; 179 clock-src = <&lp_clk>; 180 interrupts = <34 0>; 181 prescaler = <31>; 182 status = "disabled"; 183 }; 184 185 timer4: timer@50040b00 { 186 compatible = "renesas,smartbond-timer"; 187 reg = <0x50040b00 0x300>; 188 clock-src = <&divn_clk>; 189 interrupts = <35 0>; 190 prescaler = <32>; 191 status = "disabled"; 192 }; 193 194 uart: uart@50020000 { 195 compatible = "renesas,smartbond-uart"; 196 reg = <0x50020000 0x100>; 197 periph-clock-config = <0x01>; 198 interrupts = <5 0>; 199 status = "disabled"; 200 }; 201 202 adc: adc@50030900 { 203 compatible = "renesas,smartbond-adc"; 204 reg = <0x50030900 0x1C>; 205 interrupts = <27 0>; 206 status = "disabled"; 207 #io-channel-cells = <1>; 208 }; 209 210 211 sdadc: sdadc@50020800 { 212 compatible = "renesas,smartbond-sdadc"; 213 reg = <0x50020800 0x1C>; 214 interrupts = <28 0>; 215 clock-freq = <2>; 216 status = "disabled"; 217 #io-channel-cells = <1>; 218 }; 219 220 trng: trng@50040c00 { 221 compatible = "renesas,smartbond-trng"; 222 reg = <0x50040c00 0x0C>; 223 interrupts = <24 0>; 224 status = "okay"; 225 }; 226 227 i2c: i2c@50020600 { 228 compatible = "renesas,smartbond-i2c"; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 reg = <0x50020600 0x100>; 232 periph-clock-config = <0x0200>; 233 interrupts = <8 0>; 234 status = "disabled"; 235 }; 236 237 i2c2: i2c@50020700 { 238 compatible = "renesas,smartbond-i2c"; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 reg = <0x50020700 0x100>; 242 periph-clock-config = <0x0800>; 243 interrupts = <9 0>; 244 }; 245 246 spi: spi@50020300 { 247 compatible = "renesas,smartbond-spi"; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 reg = <0x50020300 0x100>; 251 periph-clock-config = <0x20>; 252 interrupts = <10 0>; 253 status = "disabled"; 254 }; 255 256 spi2: spi@50020400 { 257 compatible = "renesas,smartbond-spi"; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 reg = <0x50020400 0x100>; 261 periph-clock-config = <0x80>; 262 interrupts = <11 0>; 263 status = "disabled"; 264 }; 265 usbd: usb@50040000 { 266 compatible = "renesas,smartbond-usbd"; 267 reg = <0x50040000 0x1B0>; 268 dma-chan-rx = <6>; 269 dma-chan-tx = <7>; 270 dma-min-transfer-size = <65>; 271 fifo-read-threshold = <4>; 272 ep-out-buf-size = <8 64 64 64>; 273 interrupts = <15 0>, <21 0>; 274 status = "disabled"; 275 }; 276 }; 277}; 278 279&nvic { 280 arm,num-irq-priority-bits = <4>; 281}; 282
