1 /*
2 * Copyright (c) 2023 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nuvoton_npcx_fiu_qspi
8
9 #include <zephyr/drivers/clock_control.h>
10 #include <zephyr/drivers/flash/npcx_flash_api_ex.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/drivers/spi.h>
13 #include <zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h>
14 #include <soc.h>
15
16 #include "flash_npcx_fiu_qspi.h"
17
18 #include <zephyr/logging/log.h>
19 LOG_MODULE_REGISTER(npcx_fiu_qspi, CONFIG_FLASH_LOG_LEVEL);
20
21 /* Driver convenience defines */
22 #define HAL_INSTANCE(dev) \
23 ((struct fiu_reg *)((const struct npcx_qspi_fiu_config *)(dev)->config)->base)
24
25 /* Device config */
26 struct npcx_qspi_fiu_config {
27 /* Flash interface unit base address */
28 uintptr_t base;
29 /* Clock configuration */
30 struct npcx_clk_cfg clk_cfg;
31 /* Enable 2 external SPI devices for direct read on QSPI bus */
32 bool en_direct_access_2dev;
33 bool base_flash_inv;
34 };
35
36 /* Device data */
37 struct npcx_qspi_fiu_data {
38 /* mutex of qspi bus controller */
39 struct k_sem lock_sem;
40 /* Current device configuration on QSPI bus */
41 const struct npcx_qspi_cfg *cur_cfg;
42 /* Current Software controlled Chip-Select number */
43 int sw_cs;
44 /* Current QSPI bus operation */
45 uint32_t operation;
46 };
47
48 /* NPCX SPI User Mode Access (UMA) functions */
qspi_npcx_uma_cs_level(const struct device * dev,uint8_t sw_cs,bool level)49 static inline void qspi_npcx_uma_cs_level(const struct device *dev, uint8_t sw_cs, bool level)
50 {
51 struct fiu_reg *const inst = HAL_INSTANCE(dev);
52
53 /* Set chip select to high/low level */
54 if (level) {
55 inst->UMA_ECTS |= BIT(sw_cs);
56 } else {
57 inst->UMA_ECTS &= ~BIT(sw_cs);
58 }
59 }
60
qspi_npcx_uma_write_byte(const struct device * dev,uint8_t data)61 static inline void qspi_npcx_uma_write_byte(const struct device *dev, uint8_t data)
62 {
63 struct fiu_reg *const inst = HAL_INSTANCE(dev);
64
65 /* Set data to UMA_CODE and trigger UMA */
66 inst->UMA_CODE = data;
67 inst->UMA_CTS = UMA_CODE_CMD_WR_ONLY;
68 /* EXEC_DONE will be zero automatically if a UMA transaction is completed. */
69 while (IS_BIT_SET(inst->UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) {
70 continue;
71 }
72 }
73
qspi_npcx_uma_read_byte(const struct device * dev,uint8_t * data)74 static inline void qspi_npcx_uma_read_byte(const struct device *dev, uint8_t *data)
75 {
76 struct fiu_reg *const inst = HAL_INSTANCE(dev);
77
78 /* Trigger UMA and Get data from DB0 later */
79 inst->UMA_CTS = UMA_CODE_RD_BYTE(1);
80 while (IS_BIT_SET(inst->UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) {
81 continue;
82 }
83
84 *data = inst->UMA_DB0;
85 }
86
87 /* NPCX SPI Direct Read Access (DRA)/User Mode Access (UMA) configuration functions */
qspi_npcx_config_uma_mode(const struct device * dev,const struct npcx_qspi_cfg * qspi_cfg)88 static inline void qspi_npcx_config_uma_mode(const struct device *dev,
89 const struct npcx_qspi_cfg *qspi_cfg)
90 {
91 struct fiu_reg *const inst = HAL_INSTANCE(dev);
92
93 if ((qspi_cfg->flags & NPCX_QSPI_SEC_FLASH_SL) != 0) {
94 inst->UMA_ECTS |= BIT(NPCX_UMA_ECTS_SEC_CS);
95 } else {
96 inst->UMA_ECTS &= ~BIT(NPCX_UMA_ECTS_SEC_CS);
97 }
98 }
99
qspi_npcx_config_dra_4byte_mode(const struct device * dev,const struct npcx_qspi_cfg * qspi_cfg)100 static inline void qspi_npcx_config_dra_4byte_mode(const struct device *dev,
101 const struct npcx_qspi_cfg *qspi_cfg)
102 {
103 #if defined(CONFIG_FLASH_NPCX_FIU_SUPP_DRA_4B_ADDR)
104 struct fiu_reg *const inst = HAL_INSTANCE(dev);
105
106 #if defined(CONFIG_FLASH_NPCX_FIU_DRA_V1)
107 if (qspi_cfg->enter_4ba != 0) {
108 if ((qspi_cfg->flags & NPCX_QSPI_SEC_FLASH_SL) != 0) {
109 inst->SPI1_DEV |= BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS11);
110 } else {
111 inst->SPI1_DEV |= BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS10);
112 }
113 } else {
114 inst->SPI1_DEV &= ~(BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS11) |
115 BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS10));
116 }
117 #elif defined(CONFIG_FLASH_NPCX_FIU_DRA_V2)
118 if (qspi_cfg->enter_4ba != 0) {
119 SET_FIELD(inst->SPI_DEV, NPCX_SPI_DEV_NADDRB, NPCX_DEV_NUM_ADDR_4BYTE);
120 }
121 #endif
122 #endif /* CONFIG_FLASH_NPCX_FIU_SUPP_DRA_4B_ADDR */
123 }
124
qspi_npcx_config_dra_mode(const struct device * dev,const struct npcx_qspi_cfg * qspi_cfg)125 static inline void qspi_npcx_config_dra_mode(const struct device *dev,
126 const struct npcx_qspi_cfg *qspi_cfg)
127 {
128 struct fiu_reg *const inst = HAL_INSTANCE(dev);
129
130 /* Select SPI device number for DRA mode in npcx4 series */
131 if (IS_ENABLED(CONFIG_FLASH_NPCX_FIU_DRA_V2)) {
132 int spi_dev_num = (qspi_cfg->flags & NPCX_QSPI_SEC_FLASH_SL) != 0 ? 1 : 0;
133
134 SET_FIELD(inst->BURST_CFG, NPCX_BURST_CFG_SPI_DEV_SEL, spi_dev_num);
135 }
136
137 /* Enable quad mode of Direct Read Mode if needed */
138 if (qspi_cfg->qer_type != JESD216_DW15_QER_NONE) {
139 inst->RESP_CFG |= BIT(NPCX_RESP_CFG_QUAD_EN);
140 } else {
141 inst->RESP_CFG &= ~BIT(NPCX_RESP_CFG_QUAD_EN);
142 }
143
144 /* Selects the SPI read access type of Direct Read Access mode */
145 SET_FIELD(inst->SPI_FL_CFG, NPCX_SPI_FL_CFG_RD_MODE, qspi_cfg->rd_mode);
146
147 /* Enable/Disable 4 byte address mode for Direct Read Access (DRA) */
148 qspi_npcx_config_dra_4byte_mode(dev, qspi_cfg);
149 }
150
qspi_npcx_fiu_set_operation(const struct device * dev,uint32_t operation)151 static inline void qspi_npcx_fiu_set_operation(const struct device *dev, uint32_t operation)
152 {
153 if ((operation & NPCX_EX_OP_INT_FLASH_WP) != 0) {
154 npcx_pinctrl_flash_write_protect_set();
155 }
156 }
157
158 /* NPCX specific QSPI-FIU controller functions */
qspi_npcx_fiu_uma_transceive(const struct device * dev,struct npcx_uma_cfg * cfg,uint32_t flags)159 int qspi_npcx_fiu_uma_transceive(const struct device *dev, struct npcx_uma_cfg *cfg,
160 uint32_t flags)
161 {
162 struct npcx_qspi_fiu_data *const data = dev->data;
163
164 /* UMA transaction is permitted? */
165 if ((data->operation & NPCX_EX_OP_LOCK_UMA) != 0) {
166 return -EPERM;
167 }
168
169 /* Assert chip select */
170 qspi_npcx_uma_cs_level(dev, data->sw_cs, false);
171
172 /* Transmit op-code first */
173 qspi_npcx_uma_write_byte(dev, cfg->opcode);
174
175 if ((flags & NPCX_UMA_ACCESS_ADDR) != 0) {
176 /* 3-byte or 4-byte address? */
177 const int addr_start = (data->cur_cfg->enter_4ba != 0) ? 0 : 1;
178
179 for (size_t i = addr_start; i < 4; i++) {
180 LOG_DBG("addr %d, %02x", i, cfg->addr.u8[i]);
181 qspi_npcx_uma_write_byte(dev, cfg->addr.u8[i]);
182 }
183 }
184
185 if ((flags & NPCX_UMA_ACCESS_WRITE) != 0) {
186 if (cfg->tx_buf == NULL) {
187 return -EINVAL;
188 }
189 for (size_t i = 0; i < cfg->tx_count; i++) {
190 qspi_npcx_uma_write_byte(dev, cfg->tx_buf[i]);
191 }
192 }
193
194 if ((flags & NPCX_UMA_ACCESS_READ) != 0) {
195 if (cfg->rx_buf == NULL) {
196 return -EINVAL;
197 }
198 for (size_t i = 0; i < cfg->rx_count; i++) {
199 qspi_npcx_uma_read_byte(dev, cfg->rx_buf + i);
200 }
201 }
202
203 /* De-assert chip select */
204 qspi_npcx_uma_cs_level(dev, data->sw_cs, true);
205
206 return 0;
207 }
208
qspi_npcx_fiu_mutex_lock_configure(const struct device * dev,const struct npcx_qspi_cfg * cfg,const uint32_t operation)209 void qspi_npcx_fiu_mutex_lock_configure(const struct device *dev,
210 const struct npcx_qspi_cfg *cfg,
211 const uint32_t operation)
212 {
213 struct npcx_qspi_fiu_data *const data = dev->data;
214
215 k_sem_take(&data->lock_sem, K_FOREVER);
216
217 /* If the current device is different from previous one, configure it */
218 if (data->cur_cfg != cfg) {
219 data->cur_cfg = cfg;
220
221 /* Apply pin-muxing and tri-state */
222 pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
223
224 /* Configure User Mode Access (UMA) settings */
225 qspi_npcx_config_uma_mode(dev, cfg);
226
227 /* Configure for Direct Read Access (DRA) settings */
228 qspi_npcx_config_dra_mode(dev, cfg);
229
230 /* Save SW CS bit used in UMA mode */
231 data->sw_cs = find_lsb_set(cfg->flags & NPCX_QSPI_SW_CS_MASK) - 1;
232 }
233
234 /* Set QSPI bus operation */
235 if (data->operation != operation) {
236 qspi_npcx_fiu_set_operation(dev, operation);
237 data->operation = operation;
238 }
239 }
240
qspi_npcx_fiu_mutex_unlock(const struct device * dev)241 void qspi_npcx_fiu_mutex_unlock(const struct device *dev)
242 {
243 struct npcx_qspi_fiu_data *const data = dev->data;
244
245 k_sem_give(&data->lock_sem);
246 }
247
248 #if defined(CONFIG_FLASH_NPCX_FIU_DRA_V2)
qspi_npcx_fiu_set_spi_size(const struct device * dev,const struct npcx_qspi_cfg * cfg)249 void qspi_npcx_fiu_set_spi_size(const struct device *dev, const struct npcx_qspi_cfg *cfg)
250 {
251 struct fiu_reg *const inst = HAL_INSTANCE(dev);
252 uint8_t flags = cfg->flags;
253
254 if (cfg->spi_dev_sz <= NPCX_SPI_DEV_SIZE_128M) {
255 if ((flags & NPCX_QSPI_SEC_FLASH_SL) == 0) {
256 SET_FIELD(inst->BURST_CFG, NPCX_BURST_CFG_SPI_DEV_SEL, NPCX_SPI_F_CS0);
257 } else {
258 SET_FIELD(inst->BURST_CFG, NPCX_BURST_CFG_SPI_DEV_SEL, NPCX_SPI_F_CS1);
259 }
260 inst->SPI_DEV_SIZE = BIT(cfg->spi_dev_sz);
261 } else {
262 LOG_ERR("Invalid setting of low device size");
263 }
264 }
265 #endif
266
qspi_npcx_fiu_init(const struct device * dev)267 static int qspi_npcx_fiu_init(const struct device *dev)
268 {
269 const struct npcx_qspi_fiu_config *const config = dev->config;
270 struct npcx_qspi_fiu_data *const data = dev->data;
271 const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
272 int ret;
273
274 if (!device_is_ready(clk_dev)) {
275 LOG_ERR("%s device not ready", clk_dev->name);
276 return -ENODEV;
277 }
278
279 /* Turn on device clock first and get source clock freq. */
280 ret = clock_control_on(clk_dev,
281 (clock_control_subsys_t)&config->clk_cfg);
282 if (ret < 0) {
283 LOG_ERR("Turn on FIU clock fail %d", ret);
284 return ret;
285 }
286
287 /* initialize mutex for qspi controller */
288 k_sem_init(&data->lock_sem, 1, 1);
289
290 /* Enable direct access for 2 external SPI devices */
291 if (config->en_direct_access_2dev) {
292 #if defined(CONFIG_FLASH_NPCX_FIU_SUPP_DRA_2_DEV)
293 struct fiu_reg *const inst = HAL_INSTANCE(dev);
294
295 inst->FIU_EXT_CFG |= BIT(NPCX_FIU_EXT_CFG_SPI1_2DEV);
296 #if defined(CONFIG_FLASH_NPCX_FIU_SUPP_LOW_DEV_SWAP)
297 if (config->base_flash_inv) {
298 inst->FIU_EXT_CFG |= BIT(NPCX_FIU_EXT_CFG_LOW_DEV_NUM);
299 }
300 #endif
301 #endif
302 }
303
304 return 0;
305 }
306
307 #define NPCX_SPI_FIU_INIT(n) \
308 static const struct npcx_qspi_fiu_config npcx_qspi_fiu_config_##n = { \
309 .base = DT_INST_REG_ADDR(n), \
310 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(n), \
311 .en_direct_access_2dev = DT_INST_PROP(n, en_direct_access_2dev), \
312 .base_flash_inv = DT_INST_PROP(n, flash_dev_inv), \
313 }; \
314 static struct npcx_qspi_fiu_data npcx_qspi_fiu_data_##n; \
315 DEVICE_DT_INST_DEFINE(n, qspi_npcx_fiu_init, NULL, \
316 &npcx_qspi_fiu_data_##n, &npcx_qspi_fiu_config_##n, \
317 PRE_KERNEL_1, CONFIG_FLASH_INIT_PRIORITY, NULL);
318
319 DT_INST_FOREACH_STATUS_OKAY(NPCX_SPI_FIU_INIT)
320
