1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_QMI_H 9 #define _HARDWARE_STRUCTS_QMI_H 10 11 /** 12 * \file rp2350/qmi.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/qmi.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_qmi 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/qmi.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(QMI_M0_TIMING_OFFSET) // QMI_M0_TIMING 28 // Timing configuration register for memory address window 0 29 // 0xc0000000 [31:30] COOLDOWN (0x1) Chip select cooldown period 30 // 0x30000000 [29:28] PAGEBREAK (0x0) When page break is enabled, chip select will... 31 // 0x02000000 [25] SELECT_SETUP (0) Add up to one additional system clock cycle of setup... 32 // 0x01800000 [24:23] SELECT_HOLD (0x0) Add up to three additional system clock cycles of active... 33 // 0x007e0000 [22:17] MAX_SELECT (0x00) Enforce a maximum assertion duration for this window's... 34 // 0x0001f000 [16:12] MIN_DESELECT (0x00) After this window's chip select is deasserted, it... 35 // 0x00000700 [10:8] RXDELAY (0x0) Delay the read data sample timing, in units of one half... 36 // 0x000000ff [7:0] CLKDIV (0x04) Clock divisor 37 io_rw_32 timing; 38 39 _REG_(QMI_M0_RFMT_OFFSET) // QMI_M0_RFMT 40 // Read transfer format configuration for memory address window 0. 41 // 0x10000000 [28] DTR (0) Enable double transfer rate (DTR) for read commands:... 42 // 0x00070000 [18:16] DUMMY_LEN (0x0) Length of dummy phase between command suffix and data... 43 // 0x0000c000 [15:14] SUFFIX_LEN (0x0) Length of post-address command suffix, in units of 4 bits 44 // 0x00001000 [12] PREFIX_LEN (1) Length of command prefix, in units of 8 bits 45 // 0x00000300 [9:8] DATA_WIDTH (0x0) The width used for the data transfer 46 // 0x000000c0 [7:6] DUMMY_WIDTH (0x0) The width used for the dummy phase, if any 47 // 0x00000030 [5:4] SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any 48 // 0x0000000c [3:2] ADDR_WIDTH (0x0) The transfer width used for the address 49 // 0x00000003 [1:0] PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any 50 io_rw_32 rfmt; 51 52 _REG_(QMI_M0_RCMD_OFFSET) // QMI_M0_RCMD 53 // Command constants used for reads from memory address window 0. 54 // 0x0000ff00 [15:8] SUFFIX (0xa0) The command suffix bits following the address, if... 55 // 0x000000ff [7:0] PREFIX (0x03) The command prefix bits to prepend on each new transfer,... 56 io_rw_32 rcmd; 57 58 _REG_(QMI_M0_WFMT_OFFSET) // QMI_M0_WFMT 59 // Write transfer format configuration for memory address window 0. 60 // 0x10000000 [28] DTR (0) Enable double transfer rate (DTR) for write commands:... 61 // 0x00070000 [18:16] DUMMY_LEN (0x0) Length of dummy phase between command suffix and data... 62 // 0x0000c000 [15:14] SUFFIX_LEN (0x0) Length of post-address command suffix, in units of 4 bits 63 // 0x00001000 [12] PREFIX_LEN (1) Length of command prefix, in units of 8 bits 64 // 0x00000300 [9:8] DATA_WIDTH (0x0) The width used for the data transfer 65 // 0x000000c0 [7:6] DUMMY_WIDTH (0x0) The width used for the dummy phase, if any 66 // 0x00000030 [5:4] SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any 67 // 0x0000000c [3:2] ADDR_WIDTH (0x0) The transfer width used for the address 68 // 0x00000003 [1:0] PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any 69 io_rw_32 wfmt; 70 71 _REG_(QMI_M0_WCMD_OFFSET) // QMI_M0_WCMD 72 // Command constants used for writes to memory address window 0. 73 // 0x0000ff00 [15:8] SUFFIX (0xa0) The command suffix bits following the address, if... 74 // 0x000000ff [7:0] PREFIX (0x02) The command prefix bits to prepend on each new transfer,... 75 io_rw_32 wcmd; 76 } qmi_mem_hw_t; 77 78 typedef struct { 79 _REG_(QMI_DIRECT_CSR_OFFSET) // QMI_DIRECT_CSR 80 // Control and status for direct serial mode 81 // 0xc0000000 [31:30] RXDELAY (0x0) Delay the read data sample timing, in units of one half... 82 // 0x3fc00000 [29:22] CLKDIV (0x06) Clock divisor for direct serial mode 83 // 0x001c0000 [20:18] RXLEVEL (0x0) Current level of DIRECT_RX FIFO 84 // 0x00020000 [17] RXFULL (0) When 1, the DIRECT_RX FIFO is currently full 85 // 0x00010000 [16] RXEMPTY (0) When 1, the DIRECT_RX FIFO is currently empty 86 // 0x00007000 [14:12] TXLEVEL (0x0) Current level of DIRECT_TX FIFO 87 // 0x00000800 [11] TXEMPTY (0) When 1, the DIRECT_TX FIFO is currently empty 88 // 0x00000400 [10] TXFULL (0) When 1, the DIRECT_TX FIFO is currently full 89 // 0x00000080 [7] AUTO_CS1N (0) When 1, automatically assert the CS1n chip select line... 90 // 0x00000040 [6] AUTO_CS0N (0) When 1, automatically assert the CS0n chip select line... 91 // 0x00000008 [3] ASSERT_CS1N (0) When 1, assert (i 92 // 0x00000004 [2] ASSERT_CS0N (0) When 1, assert (i 93 // 0x00000002 [1] BUSY (0) Direct mode busy flag 94 // 0x00000001 [0] EN (0) Enable direct mode 95 io_rw_32 direct_csr; 96 97 _REG_(QMI_DIRECT_TX_OFFSET) // QMI_DIRECT_TX 98 // Transmit FIFO for direct mode 99 // 0x00100000 [20] NOPUSH (0) Inhibit the RX FIFO push that would correspond to this... 100 // 0x00080000 [19] OE (0) Output enable (active-high) 101 // 0x00040000 [18] DWIDTH (0) Data width 102 // 0x00030000 [17:16] IWIDTH (0x0) Configure whether this FIFO record is transferred with... 103 // 0x0000ffff [15:0] DATA (0x0000) Data pushed here will be clocked out falling edges of... 104 io_wo_32 direct_tx; 105 106 _REG_(QMI_DIRECT_RX_OFFSET) // QMI_DIRECT_RX 107 // Receive FIFO for direct mode 108 // 0x0000ffff [15:0] DIRECT_RX (0x0000) With each byte clocked out on the serial interface, one... 109 io_ro_32 direct_rx; 110 111 qmi_mem_hw_t m[2]; 112 113 // (Description copied from array index 0 register QMI_ATRANS0 applies similarly to other array indexes) 114 _REG_(QMI_ATRANS0_OFFSET) // QMI_ATRANS0 115 // Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). 116 // 0x07ff0000 [26:16] SIZE (0x400) Translation aperture size for this virtual address... 117 // 0x00000fff [11:0] BASE (0x000) Physical address base for this virtual address range, in... 118 io_rw_32 atrans[8]; 119 } qmi_hw_t; 120 121 #define qmi_hw ((qmi_hw_t *)XIP_QMI_BASE) 122 static_assert(sizeof (qmi_hw_t) == 0x0054, ""); 123 124 #endif // _HARDWARE_STRUCTS_QMI_H 125 126
