1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /* 4 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _HARDWARE_STRUCTS_PWM_H 10 #define _HARDWARE_STRUCTS_PWM_H 11 12 #include "hardware/address_mapped.h" 13 #include "hardware/regs/pwm.h" 14 15 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pwm 16 // 17 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 18 // _REG_(x) will link to the corresponding register in hardware/regs/pwm.h. 19 // 20 // Bit-field descriptions are of the form: 21 // BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION 22 23 typedef struct pwm_slice_hw { 24 _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR 25 // Control and status register 26 // 0x00000080 [7] : PH_ADV (0): Advance the phase of the counter by 1 count, while it is running 27 // 0x00000040 [6] : PH_RET (0): Retard the phase of the counter by 1 count, while it is running 28 // 0x00000030 [5:4] : DIVMODE (0) 29 // 0x00000008 [3] : B_INV (0): Invert output B 30 // 0x00000004 [2] : A_INV (0): Invert output A 31 // 0x00000002 [1] : PH_CORRECT (0): 1: Enable phase-correct modulation 32 // 0x00000001 [0] : EN (0): Enable the PWM channel 33 io_rw_32 csr; 34 35 _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV 36 // INT and FRAC form a fixed-point fractional number 37 // 0x00000ff0 [11:4] : INT (1) 38 // 0x0000000f [3:0] : FRAC (0) 39 io_rw_32 div; 40 41 _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR 42 // Direct access to the PWM counter 43 // 0x0000ffff [15:0] : CH0_CTR (0) 44 io_rw_32 ctr; 45 46 _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC 47 // Counter compare values 48 // 0xffff0000 [31:16] : B (0) 49 // 0x0000ffff [15:0] : A (0) 50 io_rw_32 cc; 51 52 _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP 53 // Counter wrap value 54 // 0x0000ffff [15:0] : CH0_TOP (0xffff) 55 io_rw_32 top; 56 } pwm_slice_hw_t; 57 58 typedef struct { 59 pwm_slice_hw_t slice[NUM_PWM_SLICES]; // 8 60 61 _REG_(PWM_EN_OFFSET) // PWM_EN 62 // This register aliases the CSR_EN bits for all channels 63 // 0x00000080 [7] : CH7 (0) 64 // 0x00000040 [6] : CH6 (0) 65 // 0x00000020 [5] : CH5 (0) 66 // 0x00000010 [4] : CH4 (0) 67 // 0x00000008 [3] : CH3 (0) 68 // 0x00000004 [2] : CH2 (0) 69 // 0x00000002 [1] : CH1 (0) 70 // 0x00000001 [0] : CH0 (0) 71 io_rw_32 en; 72 73 _REG_(PWM_INTR_OFFSET) // PWM_INTR 74 // Raw Interrupts 75 // 0x00000080 [7] : CH7 (0) 76 // 0x00000040 [6] : CH6 (0) 77 // 0x00000020 [5] : CH5 (0) 78 // 0x00000010 [4] : CH4 (0) 79 // 0x00000008 [3] : CH3 (0) 80 // 0x00000004 [2] : CH2 (0) 81 // 0x00000002 [1] : CH1 (0) 82 // 0x00000001 [0] : CH0 (0) 83 io_rw_32 intr; 84 85 _REG_(PWM_INTE_OFFSET) // PWM_INTE 86 // Interrupt Enable 87 // 0x00000080 [7] : CH7 (0) 88 // 0x00000040 [6] : CH6 (0) 89 // 0x00000020 [5] : CH5 (0) 90 // 0x00000010 [4] : CH4 (0) 91 // 0x00000008 [3] : CH3 (0) 92 // 0x00000004 [2] : CH2 (0) 93 // 0x00000002 [1] : CH1 (0) 94 // 0x00000001 [0] : CH0 (0) 95 io_rw_32 inte; 96 97 _REG_(PWM_INTF_OFFSET) // PWM_INTF 98 // Interrupt Force 99 // 0x00000080 [7] : CH7 (0) 100 // 0x00000040 [6] : CH6 (0) 101 // 0x00000020 [5] : CH5 (0) 102 // 0x00000010 [4] : CH4 (0) 103 // 0x00000008 [3] : CH3 (0) 104 // 0x00000004 [2] : CH2 (0) 105 // 0x00000002 [1] : CH1 (0) 106 // 0x00000001 [0] : CH0 (0) 107 io_rw_32 intf; 108 109 _REG_(PWM_INTS_OFFSET) // PWM_INTS 110 // Interrupt status after masking & forcing 111 // 0x00000080 [7] : CH7 (0) 112 // 0x00000040 [6] : CH6 (0) 113 // 0x00000020 [5] : CH5 (0) 114 // 0x00000010 [4] : CH4 (0) 115 // 0x00000008 [3] : CH3 (0) 116 // 0x00000004 [2] : CH2 (0) 117 // 0x00000002 [1] : CH1 (0) 118 // 0x00000001 [0] : CH0 (0) 119 io_ro_32 ints; 120 } pwm_hw_t; 121 122 #define pwm_hw ((pwm_hw_t *)PWM_BASE) 123 124 static_assert( NUM_PWM_SLICES == 8, ""); 125 126 #endif 127
