1 /******************************************************************************
2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3 * All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************/
18
19 /********************************************************************************************************
20 * @file pwm.c
21 *
22 * @brief This is the source file for B91
23 *
24 * @author Driver Group
25 *
26 *******************************************************************************************************/
27 #include "pwm.h"
28
29
30 dma_config_t pwm_tx_dma_config={
31 .dst_req_sel= DMA_REQ_PWM_TX,//tx req
32 .src_req_sel=0,
33 .dst_addr_ctrl=DMA_ADDR_FIX,
34 .src_addr_ctrl=DMA_ADDR_INCREMENT,//increment
35 .dstmode=DMA_HANDSHAKE_MODE,//handshake
36 .srcmode=DMA_NORMAL_MODE,
37 .dstwidth=DMA_CTR_WORD_WIDTH,//must word
38 .srcwidth=DMA_CTR_WORD_WIDTH,//must word
39 .src_burst_size=0,//must 0
40 .read_num_en=0,
41 .priority=0,
42 .write_num_en=0,
43 .auto_en=0,
44 };
45
46
47 /**
48 * @brief This fuction servers to set pin as pwm0
49 * @param[in] pin - selected pin
50 * @return none.
51 */
pwm_set_pin(pwm_pin_e pin)52 void pwm_set_pin(pwm_pin_e pin)
53 {
54 unsigned char val=0;
55 unsigned char start_bit = (BIT_LOW_BIT(pin & 0xff) %4 )<<1;
56 unsigned char mask =(unsigned char) ~BIT_RNG(start_bit , start_bit+1);
57
58 if(pin==PWM_PWM2_PB7){ // Pad Function Mux:0
59 val = 0;
60 BM_CLR(reg_gpio_pad_mul_sel, BIT(3));
61 }else if((pin==PWM_PWM0_PB4) || (pin==PWM_PWM4_PD7) ||(pin==PWM_PWM2_N_PE6) ||(pin==PWM_PWM3_N_PE7)){ // Pad Function Mux:1
62 val = 1<<(start_bit);
63 }else{ // Pad Function Mux:2
64 val = 2<<(start_bit);
65 reg_gpio_pad_mul_sel|=BIT(0);
66 }
67
68 reg_gpio_func_mux(pin)=(reg_gpio_func_mux(pin)& mask)|val;
69 gpio_function_dis(pin);
70 }
71
72
73 /**
74 * @brief This function servers to configure DMA channel and some configures.
75 * @param[in] chn - to select the DMA channel.
76 * @return none
77 */
pwm_set_dma_config(dma_chn_e chn)78 void pwm_set_dma_config(dma_chn_e chn)
79 {
80 dma_config(chn,&pwm_tx_dma_config);
81 }
82
83
84 /**
85 * @brief This function servers to configure DMA channel address and length.
86 * @param[in] chn - to select the DMA channel.
87 * @param[in] buf_addr - the address where DMA need to get data from SRAM.
88 * @param[in] len - the length of data in SRAM.
89 * @return none
90 */
pwm_set_dma_buf(dma_chn_e chn,unsigned int buf_addr,unsigned int len)91 void pwm_set_dma_buf(dma_chn_e chn,unsigned int buf_addr,unsigned int len)
92 {
93 dma_set_address( chn,convert_ram_addr_cpu2bus(buf_addr),reg_pwm_data_buf_adr);
94 dma_set_size(chn,len,DMA_WORD_WIDTH);
95 }
96
97
98 /**
99 * @brief This function servers to enable DMA channel.
100 * @param[in] chn - to select the DMA channel.
101 * @return none
102 */
pwm_ir_dma_mode_start(dma_chn_e chn)103 void pwm_ir_dma_mode_start(dma_chn_e chn)
104 {
105 dma_chn_en(chn);
106 }
107
108
109
110 /**
111 * @brief This function servers to configure DMA head node.
112 * @param[in] chn - to select the DMA channel.
113 * @param[in] src_addr - to configure DMA source address.
114 * @param[in] data_len - to configure DMA length.
115 * @param[in] head_of_list - to configure the address of the next node configure.
116 * @return none
117 */
pwm_set_dma_chain_llp(dma_chn_e chn,unsigned short * src_addr,unsigned int data_len,dma_chain_config_t * head_of_list)118 void pwm_set_dma_chain_llp(dma_chn_e chn,unsigned short * src_addr, unsigned int data_len,dma_chain_config_t * head_of_list)
119 {
120 dma_config(chn,&pwm_tx_dma_config);
121 dma_set_address( chn,convert_ram_addr_cpu2bus(src_addr),reg_pwm_data_buf_adr);
122 dma_set_size(chn,data_len,DMA_WORD_WIDTH);
123 reg_dma_llp(chn)=(unsigned int)convert_ram_addr_cpu2bus(head_of_list);
124 }
125
126
127 /**
128 * @brief This function servers to configure DMA cycle chain node.
129 * @param[in] chn - to select the DMA channel.
130 * @param[in] config_addr - to servers to configure the address of the current node.
131 * @param[in] llponit - to configure the address of the next node configure.
132 * @param[in] src_addr - to configure DMA source address.
133 * @param[in] data_len - to configure DMA length.
134 * @return none
135 */
pwm_set_tx_dma_add_list_element(dma_chn_e chn,dma_chain_config_t * config_addr,dma_chain_config_t * llponit,unsigned short * src_addr,unsigned int data_len)136 void pwm_set_tx_dma_add_list_element(dma_chn_e chn,dma_chain_config_t *config_addr,dma_chain_config_t *llponit ,unsigned short * src_addr,unsigned int data_len)
137 {
138 config_addr->dma_chain_ctl= reg_dma_ctrl(chn)|BIT(0);
139 config_addr->dma_chain_src_addr=(unsigned int)convert_ram_addr_cpu2bus(src_addr);
140 config_addr->dma_chain_dst_addr=reg_pwm_data_buf_adr;
141 config_addr->dma_chain_data_len=dma_cal_size(data_len,DMA_WORD_WIDTH);
142 config_addr->dma_chain_llp_ptr=(unsigned int)convert_ram_addr_cpu2bus(llponit);
143 }
144
145
