1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2022 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef _FSL_PORT_H_
9 #define _FSL_PORT_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup port
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /* Component ID definition, used by tools. */
23 #ifndef FSL_COMPONENT_ID
24 #define FSL_COMPONENT_ID "platform.drivers.port"
25 #endif
26
27 /*! @name Driver version */
28 /*@{*/
29 /*! @brief PORT driver version. */
30 #define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
31 /*@}*/
32
33 #if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
34 /*! @brief Internal resistor pull feature selection */
35 enum _port_pull
36 {
37 kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
38 kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */
39 kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */
40 };
41 #endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
42
43 #if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
44 /*! @brief Internal resistor pull value selection */
45 enum _port_pull_value
46 {
47 kPORT_LowPullResistor = 0U, /*!< Low internal pull resistor value is selected. */
48 kPORT_HighPullResistor = 1U, /*!< High internal pull resistor value is selected. */
49 };
50 #endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
51
52 #if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
53 /*! @brief Slew rate selection */
54 enum _port_slew_rate
55 {
56 kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
57 kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
58 };
59 #endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
60
61 #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
62 /*! @brief Open Drain feature enable/disable */
63 enum _port_open_drain_enable
64 {
65 kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
66 kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */
67 };
68 #endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
69
70 #if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
71 /*! @brief Passive filter feature enable/disable */
72 enum _port_passive_filter_enable
73 {
74 kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
75 kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */
76 };
77 #endif
78
79 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
80 /*! @brief Configures the drive strength. */
81 enum _port_drive_strength
82 {
83 kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */
84 kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
85 };
86 #endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
87
88 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
89 /*! @brief Configures the drive strength1. */
90 enum _port_drive_strength1
91 {
92 kPORT_NormalDriveStrength = 0U, /*!< Normal drive strength */
93 kPORT_DoubleDriveStrength = 1U, /*!< Double drive strength */
94 };
95 #endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 */
96
97 #if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER
98 /*! @brief input buffer disable/enable. */
99 enum _port_input_buffer
100 {
101 kPORT_InputBufferDisable = 0U, /*!< Digital input is disabled */
102 kPORT_InputBufferEnable = 1U, /*!< Digital input is enabled */
103 };
104 #endif /* FSL_FEATURE_PORT_HAS_INPUT_BUFFER */
105
106 #if defined(FSL_FEATURE_PORT_HAS_INVERT_INPUT) && FSL_FEATURE_PORT_HAS_INVERT_INPUT
107 /*! @brief Digital input is not inverted or it is inverted. */
108 enum _port_invet_input
109 {
110 kPORT_InputNormal = 0U, /*!< Digital input is not inverted */
111 kPORT_InputInvert = 1U, /*!< Digital input is inverted */
112 };
113 #endif /* FSL_FEATURE_PORT_HAS_INVERT_INPUT */
114
115 #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
116 /*! @brief Unlock/lock the pin control register field[15:0] */
117 enum _port_lock_register
118 {
119 kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
120 kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */
121 };
122 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
123
124 #if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
125 /*! @brief Pin mux selection */
126 typedef enum _port_mux
127 {
128 kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */
129 kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */
130 kPORT_MuxAlt0 = 0U, /*!< Chip-specific */
131 kPORT_MuxAlt1 = 1U, /*!< Chip-specific */
132 kPORT_MuxAlt2 = 2U, /*!< Chip-specific */
133 kPORT_MuxAlt3 = 3U, /*!< Chip-specific */
134 kPORT_MuxAlt4 = 4U, /*!< Chip-specific */
135 kPORT_MuxAlt5 = 5U, /*!< Chip-specific */
136 kPORT_MuxAlt6 = 6U, /*!< Chip-specific */
137 kPORT_MuxAlt7 = 7U, /*!< Chip-specific */
138 kPORT_MuxAlt8 = 8U, /*!< Chip-specific */
139 kPORT_MuxAlt9 = 9U, /*!< Chip-specific */
140 kPORT_MuxAlt10 = 10U, /*!< Chip-specific */
141 kPORT_MuxAlt11 = 11U, /*!< Chip-specific */
142 kPORT_MuxAlt12 = 12U, /*!< Chip-specific */
143 kPORT_MuxAlt13 = 13U, /*!< Chip-specific */
144 kPORT_MuxAlt14 = 14U, /*!< Chip-specific */
145 kPORT_MuxAlt15 = 15U, /*!< Chip-specific */
146 } port_mux_t;
147 #endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
148
149 #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
150 /*! @brief Configures the interrupt generation condition. */
151 typedef enum _port_interrupt
152 {
153 kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
154 #if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST || defined(DOXYGEN_OUTPUT)
155 kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */
156 kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
157 kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */
158 #endif
159 #if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG || defined(DOXYGEN_OUTPUT)
160 kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */
161 kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
162 kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */
163 #endif
164 kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */
165 kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
166 kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
167 kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */
168 kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */
169 #if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER || defined(DOXYGEN_OUTPUT)
170 kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
171 kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */
172 #endif
173 } port_interrupt_t;
174 #endif
175
176 #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
177 /*! @brief Digital filter clock source selection */
178 typedef enum _port_digital_filter_clock_source
179 {
180 kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
181 kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
182 } port_digital_filter_clock_source_t;
183
184 /*! @brief PORT digital filter feature configuration definition */
185 typedef struct _port_digital_filter_config
186 {
187 uint32_t digitalFilterWidth; /*!< Set digital filter width */
188 port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
189 } port_digital_filter_config_t;
190 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
191
192 #if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
193 /*! @brief PORT pin configuration structure */
194 typedef struct _port_pin_config
195 {
196 #if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
197 uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
198 #else
199 uint16_t : 2;
200 #endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
201
202 #if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
203 uint16_t pullValueSelect : 1; /*!< Pull value select */
204 #endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
205
206 #if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
207 uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
208 #else
209 uint16_t : 1;
210 #endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
211
212 #if !(defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE)
213 uint16_t : 1;
214 #endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
215
216 #if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
217 uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
218 #else
219 uint16_t : 1;
220 #endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
221
222 #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
223 uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
224 #else
225 uint16_t : 1;
226 #endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
227
228 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
229 uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
230 #else
231 uint16_t : 1;
232 #endif
233
234 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
235 uint16_t driveStrength1 : 1; /*!< Normal/Double drive strength enable/disable */
236 #else
237 uint16_t : 1;
238 #endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 */
239
240 #if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3)
241 uint16_t mux : 3; /*!< Pin mux Configure */
242 uint16_t : 1;
243 #elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4)
244 uint16_t mux : 4; /*!< Pin mux Configure */
245 #else
246 uint16_t : 4;
247 #endif
248
249 #if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER
250 uint16_t inputBuffer : 1; /*!< Input Buffer Configure */
251 #else
252 uint16_t : 1;
253 #endif /* FSL_FEATURE_PORT_HAS_INPUT_BUFFER */
254
255 #if defined(FSL_FEATURE_PORT_HAS_INVERT_INPUT) && FSL_FEATURE_PORT_HAS_INVERT_INPUT
256 uint16_t invertInput : 1; /*!< Invert Input Configure */
257 #else
258 uint16_t : 1;
259 #endif /* FSL_FEATURE_PORT_HAS_INVERT_INPUT */
260
261 uint16_t : 1;
262
263 #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
264 uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
265 #else
266 uint16_t : 1;
267 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
268 } port_pin_config_t;
269 #endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
270
271 #if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER
272 /*! @brief PORT version information. */
273 typedef struct _port_version_info
274 {
275 uint16_t feature; /*!< Feature Specification Number. */
276 uint8_t minor; /*!< Minor Version Number. */
277 uint8_t major; /*!< Major Version Number. */
278 } port_version_info_t;
279 #endif /* FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER */
280
281 #if defined(FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE) && FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE
282 /*! @brief PORT voltage range. */
283 typedef enum _port_voltage_range
284 {
285 kPORT_VoltageRange1Dot71V_3Dot6V = 0x0U, /*!< Port voltage range is 1.71 V - 3.6 V. */
286 kPORT_VoltageRange2Dot70V_3Dot6V = 0x1U, /*!< Port voltage range is 2.70 V - 3.6 V. */
287 } port_voltage_range_t;
288 #endif /* FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE */
289
290 /*******************************************************************************
291 * API
292 ******************************************************************************/
293
294 #if defined(__cplusplus)
295 extern "C" {
296 #endif
297
298 #if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
299 /*! @name Configuration */
300 /*@{*/
301
302 #if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER
303 /*!
304 * @brief Get PORT version information.
305 *
306 * @param base PORT peripheral base pointer
307 * @param info PORT version information
308 */
PORT_GetVersionInfo(PORT_Type * base,port_version_info_t * info)309 static inline void PORT_GetVersionInfo(PORT_Type *base, port_version_info_t *info)
310 {
311 uint32_t verid = base->VERID;
312 info->feature = (uint16_t)verid;
313 info->minor = (uint8_t)(verid >> PORT_VERID_MINOR_SHIFT);
314 info->major = (uint8_t)(verid >> PORT_VERID_MAJOR_SHIFT);
315 }
316 #endif /* FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER */
317
318 #if defined(FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE) && FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE
319 /*!
320 * @brief Get PORT version information.
321 *
322 * @note : PORTA_CONFIG[RANGE] controls the voltage ranges of Port A, B, and C. Read or write PORTB_CONFIG[RANGE] and
323 * PORTC_CONFIG[RANGE] does not take effect.
324 *
325 * @param base PORT peripheral base pointer
326 * @param range port voltage range
327 */
PORT_SecletPortVoltageRange(PORT_Type * base,port_voltage_range_t range)328 static inline void PORT_SecletPortVoltageRange(PORT_Type *base, port_voltage_range_t range)
329 {
330 base->CONFIG = (uint32_t)range;
331 }
332 #endif /* FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE */
333
334 /*!
335 * @brief Sets the port PCR register.
336 *
337 * This is an example to define an input pin or output pin PCR configuration.
338 * @code
339 * // Define a digital input pin PCR configuration
340 * port_pin_config_t config = {
341 * kPORT_PullUp,
342 * kPORT_FastSlewRate,
343 * kPORT_PassiveFilterDisable,
344 * kPORT_OpenDrainDisable,
345 * kPORT_LowDriveStrength,
346 * kPORT_MuxAsGpio,
347 * kPORT_UnLockRegister,
348 * };
349 * @endcode
350 *
351 * @param base PORT peripheral base pointer.
352 * @param pin PORT pin number.
353 * @param config PORT PCR register configuration structure.
354 */
PORT_SetPinConfig(PORT_Type * base,uint32_t pin,const port_pin_config_t * config)355 static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
356 {
357 assert(config);
358 uint32_t addr = (uint32_t)&base->PCR[pin];
359 *(volatile uint16_t *)(addr) = *((const uint16_t *)(const void *)config);
360 }
361
362 /*!
363 * @brief Sets the port PCR register for multiple pins.
364 *
365 * This is an example to define input pins or output pins PCR configuration.
366 * @code
367 * Define a digital input pin PCR configuration
368 * port_pin_config_t config = {
369 * kPORT_PullUp ,
370 * kPORT_PullEnable,
371 * kPORT_FastSlewRate,
372 * kPORT_PassiveFilterDisable,
373 * kPORT_OpenDrainDisable,
374 * kPORT_LowDriveStrength,
375 * kPORT_MuxAsGpio,
376 * kPORT_UnlockRegister,
377 * };
378 * @endcode
379 *
380 * @param base PORT peripheral base pointer.
381 * @param mask PORT pin number macro.
382 * @param config PORT PCR register configuration structure.
383 */
PORT_SetMultiplePinsConfig(PORT_Type * base,uint32_t mask,const port_pin_config_t * config)384 static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
385 {
386 assert(config);
387
388 uint16_t pcrl = *((const uint16_t *)(const void *)config);
389
390 if (0U != (mask & 0xffffU))
391 {
392 base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
393 }
394 if (0U != (mask >> 16))
395 {
396 base->GPCHR = (mask & 0xffff0000U) | pcrl;
397 }
398 }
399
400 #if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG
401 /*!
402 * @brief Sets the port interrupt configuration in PCR register for multiple pins.
403 *
404 * @param base PORT peripheral base pointer.
405 * @param mask PORT pin number macro.
406 * @param config PORT pin interrupt configuration.
407 * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
408 * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
409 * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
410 * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
411 * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
412 * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
413 * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
414 * - #kPORT_InterruptLogicZero : Interrupt when logic zero.
415 * - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
416 * - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
417 * - #kPORT_InterruptEitherEdge : Interrupt on either edge.
418 * - #kPORT_InterruptLogicOne : Interrupt when logic one.
419 * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
420 * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit)..
421 */
PORT_SetMultipleInterruptPinsConfig(PORT_Type * base,uint32_t mask,port_interrupt_t config)422 static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config)
423 {
424 assert(config);
425
426 if (0U != ((uint32_t)mask & 0xffffU))
427 {
428 base->GICLR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU);
429 }
430 mask = mask >> 16;
431 if (0U != mask)
432 {
433 base->GICHR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU);
434 }
435 }
436 #endif
437
438 /*!
439 * @brief Configures the pin muxing.
440 *
441 * @param base PORT peripheral base pointer.
442 * @param pin PORT pin number.
443 * @param mux pin muxing slot selection.
444 * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
445 * - #kPORT_MuxAsGpio : Set as GPIO.
446 * - #kPORT_MuxAlt2 : chip-specific.
447 * - #kPORT_MuxAlt3 : chip-specific.
448 * - #kPORT_MuxAlt4 : chip-specific.
449 * - #kPORT_MuxAlt5 : chip-specific.
450 * - #kPORT_MuxAlt6 : chip-specific.
451 * - #kPORT_MuxAlt7 : chip-specific.
452 * @note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
453 * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
454 * reset to zero : kPORT_PinDisabledOrAnalog).
455 * This function is recommended to use to reset the pin mux
456 *
457 */
PORT_SetPinMux(PORT_Type * base,uint32_t pin,port_mux_t mux)458 static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
459 {
460 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
461 }
462 #endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
463
464 #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
465
466 /*!
467 * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
468 *
469 * @param base PORT peripheral base pointer.
470 * @param mask PORT pin number macro.
471 * @param enable PORT digital filter configuration.
472 */
PORT_EnablePinsDigitalFilter(PORT_Type * base,uint32_t mask,bool enable)473 static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
474 {
475 if (enable == true)
476 {
477 base->DFER |= mask;
478 }
479 else
480 {
481 base->DFER &= ~mask;
482 }
483 }
484
485 /*!
486 * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
487 *
488 * @param base PORT peripheral base pointer.
489 * @param config PORT digital filter configuration structure.
490 */
PORT_SetDigitalFilterConfig(PORT_Type * base,const port_digital_filter_config_t * config)491 static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
492 {
493 assert(config);
494
495 base->DFCR = PORT_DFCR_CS(config->clockSource);
496 base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
497 }
498
499 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
500 /*@}*/
501
502 /*! @name Interrupt */
503 /*@{*/
504
505 #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
506 /*!
507 * @brief Configures the port pin interrupt/DMA request.
508 *
509 * @param base PORT peripheral base pointer.
510 * @param pin PORT pin number.
511 * @param config PORT pin interrupt configuration.
512 * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
513 * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
514 * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
515 * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
516 * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
517 * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
518 * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
519 * - #kPORT_InterruptLogicZero : Interrupt when logic zero.
520 * - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
521 * - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
522 * - #kPORT_InterruptEitherEdge : Interrupt on either edge.
523 * - #kPORT_InterruptLogicOne : Interrupt when logic one.
524 * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
525 * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).
526 */
PORT_SetPinInterruptConfig(PORT_Type * base,uint32_t pin,port_interrupt_t config)527 static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
528 {
529 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
530 }
531 #endif
532
533 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
534 /*!
535 * @brief Configures the port pin drive strength.
536 *
537 * @param base PORT peripheral base pointer.
538 * @param pin PORT pin number.
539 * @param strength PORT pin drive strength
540 * - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured.
541 * - #kPORT_HighDriveStrength = 1U - High-drive strength is configured.
542 */
PORT_SetPinDriveStrength(PORT_Type * base,uint32_t pin,uint8_t strength)543 static inline void PORT_SetPinDriveStrength(PORT_Type *base, uint32_t pin, uint8_t strength)
544 {
545 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength);
546 }
547 #endif
548
549 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1
550 /*!
551 * @brief Enables the port pin double drive strength.
552 *
553 * @param base PORT peripheral base pointer.
554 * @param pin PORT pin number.
555 * @param enable PORT pin drive strength configuration.
556 */
PORT_EnablePinDoubleDriveStrength(PORT_Type * base,uint32_t pin,bool enable)557 static inline void PORT_EnablePinDoubleDriveStrength(PORT_Type *base, uint32_t pin, bool enable)
558 {
559 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE1_MASK) | PORT_PCR_DSE1(enable);
560 }
561 #endif
562
563 #if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE
564 /*!
565 * @brief Configures the port pin pull value.
566 *
567 * @param base PORT peripheral base pointer.
568 * @param pin PORT pin number.
569 * @param value PORT pin pull value
570 * - #kPORT_LowPullResistor = 0U - Low internal pull resistor value is selected.
571 * - #kPORT_HighPullResistor = 1U - High internal pull resistor value is selected.
572 */
PORT_SetPinPullValue(PORT_Type * base,uint32_t pin,uint8_t value)573 static inline void PORT_SetPinPullValue(PORT_Type *base, uint32_t pin, uint8_t value)
574 {
575 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_PV_MASK) | PORT_PCR_PV(value);
576 }
577 #endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */
578
579 #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
580 /*!
581 * @brief Reads the whole port status flag.
582 *
583 * If a pin is configured to generate the DMA request, the corresponding flag
584 * is cleared automatically at the completion of the requested DMA transfer.
585 * Otherwise, the flag remains set until a logic one is written to that flag.
586 * If configured for a level sensitive interrupt that remains asserted, the flag
587 * is set again immediately.
588 *
589 * @param base PORT peripheral base pointer.
590 * @return Current port interrupt status flags, for example, 0x00010001 means the
591 * pin 0 and 16 have the interrupt.
592 */
PORT_GetPinsInterruptFlags(PORT_Type * base)593 static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
594 {
595 return base->ISFR;
596 }
597
598 /*!
599 * @brief Clears the multiple pin interrupt status flag.
600 *
601 * @param base PORT peripheral base pointer.
602 * @param mask PORT pin number macro.
603 */
PORT_ClearPinsInterruptFlags(PORT_Type * base,uint32_t mask)604 static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
605 {
606 base->ISFR = mask;
607 }
608 #endif
609
610 #if defined(FSL_FEATURE_PORT_SUPPORT_EFT) && FSL_FEATURE_PORT_SUPPORT_EFT
611 /*!
612 * @brief Get EFT detect flags.
613 *
614 * @param base PORT peripheral base pointer
615 * @return EFT detect flags
616 */
PORT_GetEFTDetectFlags(PORT_Type * base)617 static inline uint32_t PORT_GetEFTDetectFlags(PORT_Type *base)
618 {
619 return base->EDFR;
620 }
621
622 /*!
623 * @brief Enable EFT detect interrupts.
624 *
625 * @param base PORT peripheral base pointer
626 * @param interrupt EFT detect interrupt
627 */
PORT_EnableEFTDetectInterrupts(PORT_Type * base,uint32_t interrupt)628 static inline void PORT_EnableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt)
629 {
630 base->EDIER |= interrupt;
631 }
632
633 /*!
634 * @brief Disable EFT detect interrupts.
635 *
636 * @param base PORT peripheral base pointer
637 * @param interrupt EFT detect interrupt
638 */
PORT_DisableEFTDetectInterrupts(PORT_Type * base,uint32_t interrupt)639 static inline void PORT_DisableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt)
640 {
641 base->EDIER &= ~interrupt;
642 }
643
644 /*!
645 * @brief Clear all low EFT detector.
646 *
647 * @note : Port B and Port C pins share the same EFT detector clear control from PORTC_EDCR register. Any write to the
648 * PORTB_EDCR does not take effect.
649 * @param base PORT peripheral base pointer
650 * @param interrupt EFT detect interrupt
651 */
PORT_ClearAllLowEFTDetectors(PORT_Type * base)652 static inline void PORT_ClearAllLowEFTDetectors(PORT_Type *base)
653 {
654 base->EDCR |= PORT_EDCR_EDLC_MASK;
655 base->EDCR &= ~PORT_EDCR_EDLC_MASK;
656 }
657
658 /*!
659 * @brief Clear all high EFT detector.
660 *
661 * @param base PORT peripheral base pointer
662 * @param interrupt EFT detect interrupt
663 */
PORT_ClearAllHighEFTDetectors(PORT_Type * base)664 static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base)
665 {
666 base->EDCR |= PORT_EDCR_EDHC_MASK;
667 base->EDCR &= ~PORT_EDCR_EDHC_MASK;
668 }
669 #endif /* FSL_FEATURE_PORT_SUPPORT_EFT */
670
671 /*@}*/
672
673 #if defined(__cplusplus)
674 }
675 #endif
676
677 /*! @}*/
678
679 #endif /* _FSL_PORT_H_ */
680
