1 /* SPDX-License-Identifier: BSD-3-Clause
2  *
3  * Copyright(c) 2018 Intel Corporation. All rights reserved.
4  *
5  * Author: Rander Wang <rander.wang@linux.intel.com>
6  */
7 
8 #ifdef __SOF_LIB_CPU_H__
9 
10 #ifndef __ARCH_LIB_CPU_H__
11 #define __ARCH_LIB_CPU_H__
12 
13 #include <xtensa/config/core-isa.h>
14 
15 #if CONFIG_MULTICORE
16 
17 void cpu_power_down_core(void);
18 
19 void cpu_alloc_core_context(int id);
20 
21 int arch_cpu_enable_core(int id);
22 
23 void arch_cpu_disable_core(int id);
24 
25 int arch_cpu_is_core_enabled(int id);
26 
27 int arch_cpu_enabled_cores(void);
28 
29 #else
30 
arch_cpu_enable_core(int id)31 static inline int arch_cpu_enable_core(int id) { return 0; }
32 
arch_cpu_disable_core(int id)33 static inline void arch_cpu_disable_core(int id) { }
34 
arch_cpu_is_core_enabled(int id)35 static inline int arch_cpu_is_core_enabled(int id) { return 1; }
36 
arch_cpu_enabled_cores(void)37 static inline int arch_cpu_enabled_cores(void) { return 1; }
38 
39 #endif
40 
arch_cpu_get_id(void)41 static inline int arch_cpu_get_id(void)
42 {
43 	int prid;
44 #if XCHAL_HAVE_PRID
45 	__asm__("rsr.prid %0" : "=a"(prid));
46 #else
47 	prid = PLATFORM_PRIMARY_CORE_ID;
48 #endif
49 	return prid;
50 }
51 
52 #if !XCHAL_HAVE_THREADPTR
53 extern unsigned int _virtual_thread_start;
54 static unsigned int *virtual_thread_ptr =
55 	(unsigned int *)&_virtual_thread_start;
56 #endif
57 
cpu_write_threadptr(int threadptr)58 static inline void cpu_write_threadptr(int threadptr)
59 {
60 #if XCHAL_HAVE_THREADPTR
61 	__asm__ __volatile__(
62 		"wur.threadptr %0" : : "a" (threadptr) : "memory");
63 #else
64 	*virtual_thread_ptr = threadptr;
65 #endif
66 }
67 
cpu_read_threadptr(void)68 static inline int cpu_read_threadptr(void)
69 {
70 	int threadptr;
71 #if XCHAL_HAVE_THREADPTR
72 	__asm__ __volatile__(
73 		"rur.threadptr %0" : "=a"(threadptr));
74 #else
75 	threadptr = *virtual_thread_ptr;
76 #endif
77 	return threadptr;
78 }
79 
cpu_read_vecbase(void)80 static inline int cpu_read_vecbase(void)
81 {
82 	int vecbase;
83 
84 	__asm__ __volatile__("rsr.vecbase %0"
85 		: "=a"(vecbase));
86 	return vecbase;
87 }
88 
cpu_read_excsave2(void)89 static inline int cpu_read_excsave2(void)
90 {
91 	int excsave2;
92 
93 	__asm__ __volatile__("rsr.excsave2 %0"
94 		: "=a"(excsave2));
95 	return excsave2;
96 }
97 
cpu_read_excsave3(void)98 static inline int cpu_read_excsave3(void)
99 {
100 	int excsave3;
101 
102 	__asm__ __volatile__("rsr.excsave3 %0"
103 		: "=a"(excsave3));
104 	return excsave3;
105 }
106 
cpu_read_excsave4(void)107 static inline int cpu_read_excsave4(void)
108 {
109 	int excsave4;
110 
111 	__asm__ __volatile__("rsr.excsave4 %0"
112 		: "=a"(excsave4));
113 	return excsave4;
114 }
115 
cpu_read_excsave5(void)116 static inline int cpu_read_excsave5(void)
117 {
118 	int excsave5;
119 
120 	__asm__ __volatile__("rsr.excsave5 %0"
121 		: "=a"(excsave5));
122 	return excsave5;
123 }
124 
125 #endif /* __ARCH_LIB_CPU_H__ */
126 
127 #else
128 
129 #error "This file shouldn't be included from outside of sof/lib/cpu.h"
130 
131 #endif /* __SOF_LIB_CPU_H__ */
132