1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_POWMAN_H 9 #define _HARDWARE_STRUCTS_POWMAN_H 10 11 /** 12 * \file rp2350/powman.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/powman.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_powman 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/powman.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(POWMAN_BADPASSWD_OFFSET) // POWMAN_BADPASSWD 28 // Indicates a bad password has been used 29 // 0x00000001 [0] BADPASSWD (0) 30 io_rw_32 badpasswd; 31 32 _REG_(POWMAN_VREG_CTRL_OFFSET) // POWMAN_VREG_CTRL 33 // Voltage Regulator Control 34 // 0x00008000 [15] RST_N (1) returns the regulator to its startup settings + 35 // 0x00002000 [13] UNLOCK (0) unlocks the VREG control interface after power up + 36 // 0x00001000 [12] ISOLATE (0) isolates the VREG control interface + 37 // 0x00000100 [8] DISABLE_VOLTAGE_LIMIT (0) 0=not disabled, 1=enabled 38 // 0x00000070 [6:4] HT_TH (0x5) high temperature protection threshold + 39 io_rw_32 vreg_ctrl; 40 41 _REG_(POWMAN_VREG_STS_OFFSET) // POWMAN_VREG_STS 42 // Voltage Regulator Status 43 // 0x00000010 [4] VOUT_OK (0) output regulation status + 44 // 0x00000001 [0] STARTUP (0) startup status + 45 io_ro_32 vreg_sts; 46 47 _REG_(POWMAN_VREG_OFFSET) // POWMAN_VREG 48 // Voltage Regulator Settings 49 // 0x00008000 [15] UPDATE_IN_PROGRESS (0) regulator state is being updated + 50 // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + 51 // 0x00000002 [1] HIZ (0) high impedance mode select + 52 io_rw_32 vreg; 53 54 _REG_(POWMAN_VREG_LP_ENTRY_OFFSET) // POWMAN_VREG_LP_ENTRY 55 // Voltage Regulator Low Power Entry Settings 56 // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + 57 // 0x00000004 [2] MODE (1) selects either normal (switching) mode or low power... 58 // 0x00000002 [1] HIZ (0) high impedance mode select + 59 io_rw_32 vreg_lp_entry; 60 61 _REG_(POWMAN_VREG_LP_EXIT_OFFSET) // POWMAN_VREG_LP_EXIT 62 // Voltage Regulator Low Power Exit Settings 63 // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + 64 // 0x00000004 [2] MODE (0) selects either normal (switching) mode or low power... 65 // 0x00000002 [1] HIZ (0) high impedance mode select + 66 io_rw_32 vreg_lp_exit; 67 68 _REG_(POWMAN_BOD_CTRL_OFFSET) // POWMAN_BOD_CTRL 69 // Brown-out Detection Control 70 // 0x00001000 [12] ISOLATE (0) isolates the brown-out detection control interface + 71 io_rw_32 bod_ctrl; 72 73 _REG_(POWMAN_BOD_OFFSET) // POWMAN_BOD 74 // Brown-out Detection Settings 75 // 0x000001f0 [8:4] VSEL (0x0b) threshold select + 76 // 0x00000001 [0] EN (1) enable brown-out detection + 77 io_rw_32 bod; 78 79 _REG_(POWMAN_BOD_LP_ENTRY_OFFSET) // POWMAN_BOD_LP_ENTRY 80 // Brown-out Detection Low Power Entry Settings 81 // 0x000001f0 [8:4] VSEL (0x0b) threshold select + 82 // 0x00000001 [0] EN (0) enable brown-out detection + 83 io_rw_32 bod_lp_entry; 84 85 _REG_(POWMAN_BOD_LP_EXIT_OFFSET) // POWMAN_BOD_LP_EXIT 86 // Brown-out Detection Low Power Exit Settings 87 // 0x000001f0 [8:4] VSEL (0x0b) threshold select + 88 // 0x00000001 [0] EN (1) enable brown-out detection + 89 io_rw_32 bod_lp_exit; 90 91 _REG_(POWMAN_LPOSC_OFFSET) // POWMAN_LPOSC 92 // Low power oscillator control register 93 // 0x000003f0 [9:4] TRIM (0x20) Frequency trim - the trim step is typically 1% of the... 94 // 0x00000003 [1:0] MODE (0x3) This feature has been removed 95 io_rw_32 lposc; 96 97 _REG_(POWMAN_CHIP_RESET_OFFSET) // POWMAN_CHIP_RESET 98 // Chip reset control and status 99 // 0x10000000 [28] HAD_WATCHDOG_RESET_RSM (0) Last reset was a watchdog timeout which was configured... 100 // 0x08000000 [27] HAD_HZD_SYS_RESET_REQ (0) Last reset was a system reset from the hazard debugger + 101 // 0x04000000 [26] HAD_GLITCH_DETECT (0) Last reset was due to a power supply glitch + 102 // 0x02000000 [25] HAD_SWCORE_PD (0) Last reset was a switched core powerdown + 103 // 0x01000000 [24] HAD_WATCHDOG_RESET_SWCORE (0) Last reset was a watchdog timeout which was configured... 104 // 0x00800000 [23] HAD_WATCHDOG_RESET_POWMAN (0) Last reset was a watchdog timeout which was configured... 105 // 0x00400000 [22] HAD_WATCHDOG_RESET_POWMAN_ASYNC (0) Last reset was a watchdog timeout which was configured... 106 // 0x00200000 [21] HAD_RESCUE (0) Last reset was a rescue reset from the debugger + 107 // 0x00080000 [19] HAD_DP_RESET_REQ (0) Last reset was an reset request from the arm debugger + 108 // 0x00040000 [18] HAD_RUN_LOW (0) Last reset was from the RUN pin + 109 // 0x00020000 [17] HAD_BOR (0) Last reset was from the brown-out detection block + 110 // 0x00010000 [16] HAD_POR (0) Last reset was from the power-on reset + 111 // 0x00000010 [4] RESCUE_FLAG (0) This is set by a rescue reset from the RP-AP 112 // 0x00000001 [0] DOUBLE_TAP (0) This flag is set by double-tapping RUN 113 io_rw_32 chip_reset; 114 115 _REG_(POWMAN_WDSEL_OFFSET) // POWMAN_WDSEL 116 // Allows a watchdog reset to reset the internal state of powman in addition to the power-on state... 117 // 0x00001000 [12] RESET_RSM (0) If set to 1, a watchdog reset will run the full power-on... 118 // 0x00000100 [8] RESET_SWCORE (0) If set to 1, a watchdog reset will reset the switched... 119 // 0x00000010 [4] RESET_POWMAN (0) If set to 1, a watchdog reset will restore powman... 120 // 0x00000001 [0] RESET_POWMAN_ASYNC (0) If set to 1, a watchdog reset will restore powman... 121 io_rw_32 wdsel; 122 123 _REG_(POWMAN_SEQ_CFG_OFFSET) // POWMAN_SEQ_CFG 124 // For configuration of the power sequencer + 125 // 0x00100000 [20] USING_FAST_POWCK (1) 0 indicates the POWMAN clock is running from the low... 126 // 0x00020000 [17] USING_BOD_LP (0) Indicates the brown-out detector (BOD) mode + 127 // 0x00010000 [16] USING_VREG_LP (0) Indicates the voltage regulator (VREG) mode + 128 // 0x00001000 [12] USE_FAST_POWCK (1) selects the reference clock (clk_ref) as the source of... 129 // 0x00000100 [8] RUN_LPOSC_IN_LP (1) Set to 0 to stop the low power osc when the... 130 // 0x00000080 [7] USE_BOD_HP (1) Set to 0 to prevent automatic switching to bod high... 131 // 0x00000040 [6] USE_BOD_LP (1) Set to 0 to prevent automatic switching to bod low power... 132 // 0x00000020 [5] USE_VREG_HP (1) Set to 0 to prevent automatic switching to vreg high... 133 // 0x00000010 [4] USE_VREG_LP (1) Set to 0 to prevent automatic switching to vreg low... 134 // 0x00000002 [1] HW_PWRUP_SRAM0 (0) Specifies the power state of SRAM0 when powering up... 135 // 0x00000001 [0] HW_PWRUP_SRAM1 (0) Specifies the power state of SRAM1 when powering up... 136 io_rw_32 seq_cfg; 137 138 _REG_(POWMAN_STATE_OFFSET) // POWMAN_STATE 139 // This register controls the power state of the 4 power domains 140 // 0x00002000 [13] CHANGING (0) 141 // 0x00001000 [12] WAITING (0) 142 // 0x00000800 [11] BAD_HW_REQ (0) Bad hardware initiated state request 143 // 0x00000400 [10] BAD_SW_REQ (0) Bad software initiated state request 144 // 0x00000200 [9] PWRUP_WHILE_WAITING (0) Request ignored because of a pending pwrup request 145 // 0x00000100 [8] REQ_IGNORED (0) 146 // 0x000000f0 [7:4] REQ (0x0) 147 // 0x0000000f [3:0] CURRENT (0xf) 148 io_rw_32 state; 149 150 _REG_(POWMAN_POW_FASTDIV_OFFSET) // POWMAN_POW_FASTDIV 151 // 0x000007ff [10:0] POW_FASTDIV (0x040) divides the POWMAN clock to provide a tick for the delay... 152 io_rw_32 pow_fastdiv; 153 154 _REG_(POWMAN_POW_DELAY_OFFSET) // POWMAN_POW_DELAY 155 // power state machine delays 156 // 0x0000ff00 [15:8] SRAM_STEP (0x20) timing between the sram0 and sram1 power state machine steps + 157 // 0x000000f0 [7:4] XIP_STEP (0x1) timing between the xip power state machine steps + 158 // 0x0000000f [3:0] SWCORE_STEP (0x1) timing between the swcore power state machine steps + 159 io_rw_32 pow_delay; 160 161 // (Description copied from array index 0 register POWMAN_EXT_CTRL0 applies similarly to other array indexes) 162 _REG_(POWMAN_EXT_CTRL0_OFFSET) // POWMAN_EXT_CTRL0 163 // Configures a gpio as a power mode aware control output 164 // 0x00004000 [14] LP_EXIT_STATE (0) output level when exiting the low power state 165 // 0x00002000 [13] LP_ENTRY_STATE (0) output level when entering the low power state 166 // 0x00001000 [12] INIT_STATE (0) 167 // 0x00000100 [8] INIT (0) 168 // 0x0000003f [5:0] GPIO_SELECT (0x3f) selects from gpio 0->30 + 169 io_rw_32 ext_ctrl[2]; 170 171 _REG_(POWMAN_EXT_TIME_REF_OFFSET) // POWMAN_EXT_TIME_REF 172 // Select a GPIO to use as a time reference, the source can be used to drive the low power clock at... 173 // 0x00000010 [4] DRIVE_LPCK (0) Use the selected GPIO to drive the 32kHz low power... 174 // 0x00000003 [1:0] SOURCE_SEL (0x0) 0 -> gpio12 + 175 io_rw_32 ext_time_ref; 176 177 _REG_(POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET) // POWMAN_LPOSC_FREQ_KHZ_INT 178 // Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC 179 // 0x0000003f [5:0] LPOSC_FREQ_KHZ_INT (0x20) Integer component of the LPOSC or GPIO clock source... 180 io_rw_32 lposc_freq_khz_int; 181 182 _REG_(POWMAN_LPOSC_FREQ_KHZ_FRAC_OFFSET) // POWMAN_LPOSC_FREQ_KHZ_FRAC 183 // Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC 184 // 0x0000ffff [15:0] LPOSC_FREQ_KHZ_FRAC (0xc49c) Fractional component of the LPOSC or GPIO clock source... 185 io_rw_32 lposc_freq_khz_frac; 186 187 _REG_(POWMAN_XOSC_FREQ_KHZ_INT_OFFSET) // POWMAN_XOSC_FREQ_KHZ_INT 188 // Informs the AON Timer of the integer component of the clock frequency when running off the XOSC 189 // 0x0000ffff [15:0] XOSC_FREQ_KHZ_INT (0x2ee0) Integer component of the XOSC frequency in kHz 190 io_rw_32 xosc_freq_khz_int; 191 192 _REG_(POWMAN_XOSC_FREQ_KHZ_FRAC_OFFSET) // POWMAN_XOSC_FREQ_KHZ_FRAC 193 // Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC 194 // 0x0000ffff [15:0] XOSC_FREQ_KHZ_FRAC (0x0000) Fractional component of the XOSC frequency in kHz 195 io_rw_32 xosc_freq_khz_frac; 196 197 _REG_(POWMAN_SET_TIME_63TO48_OFFSET) // POWMAN_SET_TIME_63TO48 198 // 0x0000ffff [15:0] SET_TIME_63TO48 (0x0000) For setting the time, do not use for reading the time,... 199 io_rw_32 set_time_63to48; 200 201 _REG_(POWMAN_SET_TIME_47TO32_OFFSET) // POWMAN_SET_TIME_47TO32 202 // 0x0000ffff [15:0] SET_TIME_47TO32 (0x0000) For setting the time, do not use for reading the time,... 203 io_rw_32 set_time_47to32; 204 205 _REG_(POWMAN_SET_TIME_31TO16_OFFSET) // POWMAN_SET_TIME_31TO16 206 // 0x0000ffff [15:0] SET_TIME_31TO16 (0x0000) For setting the time, do not use for reading the time,... 207 io_rw_32 set_time_31to16; 208 209 _REG_(POWMAN_SET_TIME_15TO0_OFFSET) // POWMAN_SET_TIME_15TO0 210 // 0x0000ffff [15:0] SET_TIME_15TO0 (0x0000) For setting the time, do not use for reading the time,... 211 io_rw_32 set_time_15to0; 212 213 _REG_(POWMAN_READ_TIME_UPPER_OFFSET) // POWMAN_READ_TIME_UPPER 214 // 0xffffffff [31:0] READ_TIME_UPPER (0x00000000) For reading bits 63:32 of the timer 215 io_ro_32 read_time_upper; 216 217 _REG_(POWMAN_READ_TIME_LOWER_OFFSET) // POWMAN_READ_TIME_LOWER 218 // 0xffffffff [31:0] READ_TIME_LOWER (0x00000000) For reading bits 31:0 of the timer 219 io_ro_32 read_time_lower; 220 221 _REG_(POWMAN_ALARM_TIME_63TO48_OFFSET) // POWMAN_ALARM_TIME_63TO48 222 // 0x0000ffff [15:0] ALARM_TIME_63TO48 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 223 io_rw_32 alarm_time_63to48; 224 225 _REG_(POWMAN_ALARM_TIME_47TO32_OFFSET) // POWMAN_ALARM_TIME_47TO32 226 // 0x0000ffff [15:0] ALARM_TIME_47TO32 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 227 io_rw_32 alarm_time_47to32; 228 229 _REG_(POWMAN_ALARM_TIME_31TO16_OFFSET) // POWMAN_ALARM_TIME_31TO16 230 // 0x0000ffff [15:0] ALARM_TIME_31TO16 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 231 io_rw_32 alarm_time_31to16; 232 233 _REG_(POWMAN_ALARM_TIME_15TO0_OFFSET) // POWMAN_ALARM_TIME_15TO0 234 // 0x0000ffff [15:0] ALARM_TIME_15TO0 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 235 io_rw_32 alarm_time_15to0; 236 237 _REG_(POWMAN_TIMER_OFFSET) // POWMAN_TIMER 238 // 0x00080000 [19] USING_GPIO_1HZ (0) Timer is synchronised to a 1hz gpio source 239 // 0x00040000 [18] USING_GPIO_1KHZ (0) Timer is running from a 1khz gpio source 240 // 0x00020000 [17] USING_LPOSC (0) Timer is running from lposc 241 // 0x00010000 [16] USING_XOSC (0) Timer is running from xosc 242 // 0x00002000 [13] USE_GPIO_1HZ (0) Selects the gpio source as the reference for the sec counter 243 // 0x00000400 [10] USE_GPIO_1KHZ (0) switch to gpio as the source of the 1kHz timer tick 244 // 0x00000200 [9] USE_XOSC (0) switch to xosc as the source of the 1kHz timer tick 245 // 0x00000100 [8] USE_LPOSC (0) Switch to lposc as the source of the 1kHz timer tick 246 // 0x00000040 [6] ALARM (0) Alarm has fired 247 // 0x00000020 [5] PWRUP_ON_ALARM (0) Alarm wakes the chip from low power mode 248 // 0x00000010 [4] ALARM_ENAB (0) Enables the alarm 249 // 0x00000004 [2] CLEAR (0) Clears the timer, does not disable the timer and does... 250 // 0x00000002 [1] RUN (0) Timer enable 251 // 0x00000001 [0] NONSEC_WRITE (0) Control whether Non-secure software can write to the... 252 io_rw_32 timer; 253 254 // (Description copied from array index 0 register POWMAN_PWRUP0 applies similarly to other array indexes) 255 _REG_(POWMAN_PWRUP0_OFFSET) // POWMAN_PWRUP0 256 // 4 GPIO powerup events can be configured to wake the chip up from a low power state 257 // 0x00000400 [10] RAW_STATUS (0) Value of selected gpio pin (only if enable == 1) 258 // 0x00000200 [9] STATUS (0) Status of gpio wakeup 259 // 0x00000100 [8] MODE (0) Edge or level detect 260 // 0x00000080 [7] DIRECTION (0) 261 // 0x00000040 [6] ENABLE (0) Set to 1 to enable the wakeup source 262 // 0x0000003f [5:0] SOURCE (0x3f) 263 io_rw_32 pwrup[4]; 264 265 _REG_(POWMAN_CURRENT_PWRUP_REQ_OFFSET) // POWMAN_CURRENT_PWRUP_REQ 266 // Indicates current powerup request state + 267 // 0x0000007f [6:0] CURRENT_PWRUP_REQ (0x00) 268 io_ro_32 current_pwrup_req; 269 270 _REG_(POWMAN_LAST_SWCORE_PWRUP_OFFSET) // POWMAN_LAST_SWCORE_PWRUP 271 // Indicates which pwrup source triggered the last switched-core power up + 272 // 0x0000007f [6:0] LAST_SWCORE_PWRUP (0x00) 273 io_ro_32 last_swcore_pwrup; 274 275 _REG_(POWMAN_DBG_PWRCFG_OFFSET) // POWMAN_DBG_PWRCFG 276 // 0x00000001 [0] IGNORE (0) Ignore pwrup req from debugger 277 io_rw_32 dbg_pwrcfg; 278 279 _REG_(POWMAN_BOOTDIS_OFFSET) // POWMAN_BOOTDIS 280 // Tell the bootrom to ignore the BOOT0 281 // 0x00000002 [1] NEXT (0) This flag always ORs writes into its current contents 282 // 0x00000001 [0] NOW (0) When powman resets the RSM, the current value of... 283 io_rw_32 bootdis; 284 285 _REG_(POWMAN_DBGCONFIG_OFFSET) // POWMAN_DBGCONFIG 286 // 0x0000000f [3:0] DP_INSTID (0x0) Configure DP instance ID for SWD multidrop selection 287 io_rw_32 dbgconfig; 288 289 // (Description copied from array index 0 register POWMAN_SCRATCH0 applies similarly to other array indexes) 290 _REG_(POWMAN_SCRATCH0_OFFSET) // POWMAN_SCRATCH0 291 // Scratch register 292 // 0xffffffff [31:0] SCRATCH0 (0x00000000) 293 io_rw_32 scratch[8]; 294 295 // (Description copied from array index 0 register POWMAN_BOOT0 applies similarly to other array indexes) 296 _REG_(POWMAN_BOOT0_OFFSET) // POWMAN_BOOT0 297 // Scratch register 298 // 0xffffffff [31:0] BOOT0 (0x00000000) 299 io_rw_32 boot[4]; 300 301 _REG_(POWMAN_INTR_OFFSET) // POWMAN_INTR 302 // Raw Interrupts 303 // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state 304 // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state 305 // 0x00000002 [1] TIMER (0) 306 // 0x00000001 [0] VREG_OUTPUT_LOW (0) 307 io_rw_32 intr; 308 309 _REG_(POWMAN_INTE_OFFSET) // POWMAN_INTE 310 // Interrupt Enable 311 // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state 312 // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state 313 // 0x00000002 [1] TIMER (0) 314 // 0x00000001 [0] VREG_OUTPUT_LOW (0) 315 io_rw_32 inte; 316 317 _REG_(POWMAN_INTF_OFFSET) // POWMAN_INTF 318 // Interrupt Force 319 // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state 320 // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state 321 // 0x00000002 [1] TIMER (0) 322 // 0x00000001 [0] VREG_OUTPUT_LOW (0) 323 io_rw_32 intf; 324 325 _REG_(POWMAN_INTS_OFFSET) // POWMAN_INTS 326 // Interrupt status after masking & forcing 327 // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state 328 // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state 329 // 0x00000002 [1] TIMER (0) 330 // 0x00000001 [0] VREG_OUTPUT_LOW (0) 331 io_ro_32 ints; 332 } powman_hw_t; 333 334 #define powman_hw ((powman_hw_t *)POWMAN_BASE) 335 static_assert(sizeof (powman_hw_t) == 0x00f0, ""); 336 337 #endif // _HARDWARE_STRUCTS_POWMAN_H 338 339
