1 /* 2 * Copyright (c) 2023 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_DISK_EMMC_HOST_H_ 8 #define ZEPHYR_DRIVERS_DISK_EMMC_HOST_H_ 9 10 /* Bit map for command Register */ 11 #define EMMC_HOST_CMD_RESP_TYPE_LOC 0 12 #define EMMC_HOST_CMD_CRC_CHECK_EN_LOC 3 13 #define EMMC_HOST_CMD_IDX_CHECK_EN_LOC 4 14 #define EMMC_HOST_CMD_DATA_PRESENT_LOC 5 15 #define EMMC_HOST_CMD_TYPE_LOC 6 16 #define EMMC_HOST_CMD_INDEX_LOC 8 17 18 /* Bit map for Transfer Mode Register */ 19 #define EMMC_HOST_XFER_DMA_EN_LOC 0 20 #define EMMC_HOST_XFER_BLOCK_CNT_EN_LOC 1 21 #define EMMC_HOST_XFER_AUTO_CMD_EN_LOC 2 22 #define EMMC_HOST_XFER_DATA_DIR_LOC 4 23 #define EMMC_HOST_XFER_MULTI_BLOCK_SEL_LOC 5 24 25 #define EMMC_HOST_XFER_DMA_EN_MASK 0x01 26 #define EMMC_HOST_XFER_BLOCK_CNT_EN_MASK 0x01 27 #define EMMC_HOST_XFER_AUTO_CMD_EN_MASK 0x03 28 #define EMMC_HOST_XFER_DATA_DIR_MASK 0x01 29 #define EMMC_HOST_XFER_MULTI_BLOCK_SEL_MASK 0x01 30 31 /* Bit map for Block Size and GAP Register */ 32 #define EMMC_HOST_BLOCK_SIZE_LOC 0 33 #define EMMC_HOST_BLOCK_SIZE_MASK 0xFFF 34 #define EMMC_HOST_DMA_BUF_SIZE_LOC 12 35 #define EMMC_HOST_DMA_BUF_SIZE_MASK 0x07 36 #define EMMC_HOST_BLOCK_GAP_LOC 3 37 #define EMMC_HOST_BLOCK_GAP_MASK 0x01 38 39 #define EMMC_HOST_ADMA_BUFF_ADD_LOC 32 40 #define EMMC_HOST_ADMA_BUFF_LEN_LOC 16 41 #define EMMC_HOST_ADMA_BUFF_LINK_NEXT (0x3 << 4) 42 #define EMMC_HOST_ADMA_BUFF_LINK_LAST (0x2 << 4) 43 #define EMMC_HOST_ADMA_INTR_EN BIT(2) 44 #define EMMC_HOST_ADMA_BUFF_LAST BIT(1) 45 #define EMMC_HOST_ADMA_BUFF_VALID BIT(0) 46 47 /* Bit Map and length details for Clock Control Register */ 48 #define EMMC_HOST_CLK_SDCLCK_FREQ_SEL_LOC 8 49 #define EMMC_HOST_CLK_SDCLCK_FREQ_SEL_UPPER_LOC 6 50 51 #define EMMC_HOST_CLK_SDCLCK_FREQ_SEL_MASK 0xFF 52 #define EMMC_HOST_CLK_SDCLCK_FREQ_SEL_UPPER_MASK 0x03 53 54 /* Bit Map for Host Control 1 Register */ 55 #define EMMC_HOST_CTRL1_DAT_WIDTH_LOC 1 56 #define EMMC_HOST_CTRL1_DMA_SEL_LOC 3 57 #define EMMC_HOST_CTRL1_EXT_DAT_WIDTH_LOC 5 58 59 #define EMMC_HOST_CTRL1_DMA_SEL_MASK 0x03 60 #define EMMC_HOST_CTRL1_EXT_DAT_WIDTH_MASK 0x01 61 #define EMMC_HOST_CTRL1_DAT_WIDTH_MASK 0x01 62 63 /** Constants Software Reset register */ 64 #define EMMC_HOST_SW_RESET_REG_ALL BIT(0) 65 #define EMMC_HOST_SW_RESET_REG_CMD BIT(1) 66 #define EMMC_HOST_SW_RESET_REG_DATA BIT(2) 67 68 #define EMMC_HOST_RESPONSE_SIZE 4 69 #define EMMC_HOST_OCR_BUSY_BIT BIT(31) 70 #define EMMC_HOST_OCR_CAPACITY_MASK 0x40000000U 71 #define EMMC_HOST_DUAL_VOLTAGE_RANGE 0x40FF8080U 72 #define EMMC_HOST_BLOCK_SIZE 512 73 74 #define EMMC_HOST_RCA_SHIFT 16 75 #define EMMC_HOST_EXTCSD_SEC_COUNT 53 76 #define EMMC_HOST_EXTCSD_GENERIC_CMD6_TIME 62 77 #define EMMC_HOST_EXTCSD_BUS_WIDTH_ADDR 0xB7 78 #define EMMC_HOST_EXTCSD_HS_TIMING_ADDR 0xB9 79 #define EMMC_HOST_BUS_SPEED_HIGHSPEED 1 80 81 #define EMMC_HOST_CMD_COMPLETE_RETRY 10000 82 #define EMMC_HOST_XFR_COMPLETE_RETRY 2000000 83 84 #define EMMC_HOST_CMD1_RETRY_TIMEOUT 1000 85 #define EMMC_HOST_CMD6_TIMEOUT_MULT 10 86 87 #define EMMC_HOST_NORMAL_INTR_MASK 0x3f 88 #define EMMC_HOST_ERROR_INTR_MASK 0x13ff 89 #define EMMC_HOST_NORMAL_INTR_MASK_CLR 0x60ff 90 91 #define EMMC_HOST_POWER_CTRL_SD_BUS_POWER 0x1 92 #define EMMC_HOST_POWER_CTRL_SD_BUS_VOLT_SEL 0x5 93 94 #define EMMC_HOST_UHSMODE_SDR12 0x0 95 #define EMMC_HOST_UHSMODE_SDR25 0x1 96 #define EMMC_HOST_UHSMODE_SDR50 0x2 97 #define EMMC_HOST_UHSMODE_SDR104 0x3 98 #define EMMC_HOST_UHSMODE_DDR50 0x4 99 #define EMMC_HOST_UHSMODE_HS400 0x5 100 101 #define EMMC_HOST_CTRL2_1P8V_SIG_EN 1 102 #define EMMC_HOST_CTRL2_1P8V_SIG_LOC 3 103 #define EMMC_HOST_CTRL2_UHS_MODE_SEL_LOC 0 104 #define EMMC_HOST_CTRL2_UHS_MODE_SEL_MASK 0x07 105 106 /* Event/command status */ 107 #define EMMC_HOST_CMD_COMPLETE BIT(0) 108 #define EMMC_HOST_XFER_COMPLETE BIT(1) 109 #define EMMC_HOST_BLOCK_GAP_INTR BIT(2) 110 #define EMMC_HOST_DMA_INTR BIT(3) 111 #define EMMC_HOST_BUF_WR_READY BIT(4) 112 #define EMMC_HOST_BUF_RD_READY BIT(5) 113 114 #define EMMC_HOST_CMD_TIMEOUT_ERR BIT(0) 115 #define EMMC_HOST_CMD_CRC_ERR BIT(1) 116 #define EMMC_HOST_CMD_END_BIT_ERR BIT(2) 117 #define EMMC_HOST_CMD_IDX_ERR BIT(3) 118 #define EMMC_HOST_DATA_TIMEOUT_ERR BIT(4) 119 #define EMMC_HOST_DATA_CRC_ERR BIT(5) 120 #define EMMC_HOST_DATA_END_BIT_ERR BIT(6) 121 #define EMMC_HOST_CUR_LMT_ERR BIT(7) 122 #define EMMC_HOST_DMA_TXFR_ERR BIT(12) 123 #define EMMC_HOST_ERR_STATUS 0xFFF 124 125 /** PState register bits */ 126 #define EMMC_HOST_PSTATE_CMD_INHIBIT BIT(0) 127 #define EMMC_HOST_PSTATE_DAT_INHIBIT BIT(1) 128 #define EMMC_HOST_PSTATE_DAT_LINE_ACTIVE BIT(2) 129 130 #define EMMC_HOST_PSTATE_WR_DMA_ACTIVE BIT(8) 131 #define EMMC_HOST_PSTATE_RD_DMA_ACTIVE BIT(9) 132 133 #define EMMC_HOST_PSTATE_BUF_READ_EN BIT(11) 134 #define EMMC_HOST_PSTATE_BUF_WRITE_EN BIT(10) 135 136 #define EMMC_HOST_PSTATE_CARD_INSERTED BIT(16) 137 138 #define EMMC_HOST_MAX_TIMEOUT 0xe 139 #define EMMC_HOST_MSEC_DELAY 1000 140 141 /** Constants for Clock Control register */ 142 #define EMMC_HOST_INTERNAL_CLOCK_EN BIT(0) 143 #define EMMC_HOST_INTERNAL_CLOCK_STABLE BIT(1) 144 #define EMMC_HOST_SD_CLOCK_EN BIT(2) 145 146 /** Clock frequency */ 147 #define EMMC_HOST_CLK_FREQ_400K 0.4 148 #define EMMC_HOST_CLK_FREQ_25M 25 149 #define EMMC_HOST_CLK_FREQ_50M 50 150 #define EMMC_HOST_CLK_FREQ_100M 100 151 #define EMMC_HOST_CLK_FREQ_200M 200 152 153 #define EMMC_HOST_TUNING_SUCCESS BIT(7) 154 #define EMMC_HOST_START_TUNING BIT(6) 155 156 #define EMMC_HOST_VOL_3_3_V_SUPPORT BIT(24) 157 #define EMMC_HOST_VOL_3_3_V_SELECT (7 << 1) 158 #define EMMC_HOST_VOL_3_0_V_SUPPORT BIT(25) 159 #define EMMC_HOST_VOL_3_0_V_SELECT (6 << 1) 160 #define EMMC_HOST_VOL_1_8_V_SUPPORT BIT(26) 161 #define EMMC_HOST_VOL_1_8_V_SELECT (5 << 1) 162 163 #define EMMC_HOST_CMD_WAIT_TIMEOUT_US 3000 164 #define EMMC_HOST_CMD_CMPLETE_TIMEOUT_US 9000 165 #define EMMC_HOST_XFR_CMPLETE_TIMEOUT_US 1000 166 #define EMMC_HOST_SDMA_BOUNDARY 0x0 167 #define EMMC_HOST_RCA_ADDRESS 0x2 168 169 #define EMMC_HOST_RESP_MASK (0xFF000000U) 170 171 #define EMMC_HOST_SET_RESP(resp0, resp1) (resp0 >> 1) | ((resp1 & 1) << 30) 172 173 #define SET_BITS(reg, pos, bit_width, val) \ 174 reg &= ~(bit_width << pos); \ 175 reg |= ((val & bit_width) << pos) 176 177 /* get value from certain bit 178 */ 179 #define GET_BITS(reg_name, start, width) ((reg_name) & (((1 << (width)) - 1) << (start))) 180 181 #define ERR_INTR_STATUS_EVENT(reg_bits) reg_bits << 16 182 183 #define ADDRESS_32BIT_MASK 0xFFFFFFFF 184 185 struct emmc_reg { 186 volatile uint32_t sdma_sysaddr; /**< SDMA System Address */ 187 volatile uint16_t block_size; /**< Block Size */ 188 volatile uint16_t block_count; /**< Block Count */ 189 volatile uint32_t argument; /**< Argument */ 190 volatile uint16_t transfer_mode; /**< Transfer Mode */ 191 volatile uint16_t cmd; /**< Command */ 192 193 volatile uint32_t resp_01; /**< Response Register 0 & 1 */ 194 volatile uint16_t resp_2; /**< Response Register 2*/ 195 volatile uint16_t resp_3; /**< Response Register 3 */ 196 volatile uint16_t resp_4; /**< Response Register 4 */ 197 volatile uint16_t resp_5; /**< Response Register 5 */ 198 volatile uint16_t resp_6; /**< Response Register 6 */ 199 volatile uint16_t resp_7; /**< Response Register 7 */ 200 volatile uint32_t data_port; /**< Buffer Data Port */ 201 volatile uint32_t present_state; /**< Present State */ 202 volatile uint8_t host_ctrl1; /**< Host Control 1 */ 203 volatile uint8_t power_ctrl; /**< Power Control */ 204 volatile uint8_t block_gap_ctrl; /**< Block Gap Control */ 205 volatile uint8_t wake_up_ctrl; /**< Wakeup Control */ 206 volatile uint16_t clock_ctrl; /**< Clock Control */ 207 volatile uint8_t timeout_ctrl; /**< Timeout Control */ 208 volatile uint8_t sw_reset; /**< Software Reset */ 209 volatile uint16_t normal_int_stat; /**< Normal Interrupt Status */ 210 volatile uint16_t err_int_stat; /**< Error Interrupt Status */ 211 volatile uint16_t normal_int_stat_en; /**< Normal Interrupt Status Enable */ 212 volatile uint16_t err_int_stat_en; /**< Error Interrupt Status Enable */ 213 volatile uint16_t normal_int_signal_en; /**< Normal Interrupt Signal Enable */ 214 volatile uint16_t err_int_signal_en; /**< Error Interrupt Signal Enable */ 215 volatile uint16_t auto_cmd_err_stat; /**< Auto CMD Error Status */ 216 volatile uint16_t host_ctrl2; /**< Host Control 2 */ 217 volatile uint64_t capabilities; /**< Capabilities */ 218 219 volatile uint64_t max_current_cap; /**< Max Current Capabilities */ 220 volatile uint16_t force_err_autocmd_stat; /**< Force Event for Auto CMD Error Status*/ 221 volatile uint16_t force_err_int_stat; /**< Force Event for Error Interrupt Status */ 222 volatile uint8_t adma_err_stat; /**< ADMA Error Status */ 223 volatile uint8_t reserved[3]; 224 volatile uint32_t adma_sys_addr1; /**< ADMA System Address1 */ 225 volatile uint32_t adma_sys_addr2; /**< ADMA System Address2 */ 226 volatile uint16_t preset_val_0; /**< Preset Value 0 */ 227 volatile uint16_t preset_val_1; /**< Preset Value 1 */ 228 volatile uint16_t preset_val_2; /**< Preset Value 2 */ 229 volatile uint16_t preset_val_3; /**< Preset Value 3 */ 230 volatile uint16_t preset_val_4; /**< Preset Value 4 */ 231 volatile uint16_t preset_val_5; /**< Preset Value 5 */ 232 volatile uint16_t preset_val_6; /**< Preset Value 6 */ 233 volatile uint16_t preset_val_7; /**< Preset Value 7 */ 234 volatile uint32_t boot_timeout; /**< Boot Timeout */ 235 volatile uint16_t preset_val_8; /**< Preset Value 8 */ 236 volatile uint16_t reserved3; 237 volatile uint16_t vendor_reg; /**< Vendor Enhanced strobe */ 238 volatile uint16_t reserved4[56]; 239 volatile uint32_t reserved5[4]; 240 volatile uint16_t slot_intr_stat; /**< Slot Interrupt Status */ 241 volatile uint16_t host_cntrl_version; /**< Host Controller Version */ 242 volatile uint32_t reserved6[64]; 243 volatile uint32_t cq_ver; /**< Command Queue Version */ 244 volatile uint32_t cq_cap; /**< Command Queue Capabilities */ 245 volatile uint32_t cq_cfg; /**< Command Queue Configuration */ 246 volatile uint32_t cq_ctrl; /**< Command Queue Control */ 247 volatile uint32_t cq_intr_stat; /**< Command Queue Interrupt Status */ 248 volatile uint32_t cq_intr_stat_en; /**< Command Queue Interrupt Status Enable */ 249 volatile uint32_t cq_intr_sig_en; /**< Command Queue Interrupt Signal Enable */ 250 volatile uint32_t cq_intr_coalesc; /**< Command Queue Interrupt Coalescing */ 251 volatile uint32_t cq_tdlba; /**< Command Queue Task Desc List Base Addr */ 252 volatile uint32_t cq_tdlba_upr; /**< Command Queue Task Desc List Base Addr Upr */ 253 volatile uint32_t cq_task_db; /**< Command Queue Task DoorBell */ 254 volatile uint32_t cq_task_db_notify; /**< Command Queue Task DoorBell Notify */ 255 volatile uint32_t cq_dev_qstat; /**< Command Queue Device queue status */ 256 volatile uint32_t cq_dev_pend_task; /**< Command Queue Device pending tasks */ 257 volatile uint32_t cq_task_clr; /**< Command Queue Task Clr */ 258 volatile uint32_t reserved7; 259 volatile uint32_t cq_ssc1; /**< Command Queue Send Status Configuration 1 */ 260 volatile uint32_t cq_ssc2; /**< Command Queue Send Status Configuration 2 */ 261 volatile uint32_t cq_crdct; /**< Command response for direct command */ 262 volatile uint32_t reserved8; 263 volatile uint32_t cq_rmem; /**< Command response mode error mask */ 264 volatile uint32_t cq_terri; /**< Command Queue Task Error Information */ 265 volatile uint32_t cq_cri; /**< Command Queue Command response index */ 266 volatile uint32_t cq_cra; /**< Command Queue Command response argument */ 267 volatile uint32_t reserved9[425]; 268 }; 269 270 enum emmc_sw_reset { 271 EMMC_HOST_SW_RESET_DATA_LINE = 0, 272 EMMC_HOST_SW_RESET_CMD_LINE, 273 EMMC_HOST_SW_RESET_ALL 274 }; 275 276 enum emmc_cmd_type { 277 EMMC_HOST_CMD_NORMAL = 0, 278 EMMC_HOST_CMD_SUSPEND, 279 EMMC_HOST_CMD_RESUME, 280 EMMC_HOST_CMD_ABORT, 281 }; 282 283 enum emmc_response_type { 284 EMMC_HOST_RESP_NONE = 0, 285 EMMC_HOST_RESP_LEN_136, 286 EMMC_HOST_RESP_LEN_48, 287 EMMC_HOST_RESP_LEN_48B, 288 EMMC_HOST_INVAL_HOST_RESP_LEN, 289 }; 290 291 struct emmc_cmd_config { 292 struct sdhc_command *sdhc_cmd; 293 uint32_t cmd_idx; 294 enum emmc_cmd_type cmd_type; 295 bool data_present; 296 bool idx_check_en; 297 bool crc_check_en; 298 }; 299 300 struct resp { 301 uint64_t resp_48bit; 302 }; 303 #endif /* _EMMC_HOST_HC_H_ */ 304
