1 /*
2 * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include <stdlib.h>
9 #include <sys/param.h>
10 #include <esp_types.h>
11 #include "sdkconfig.h"
12 #include "esp_err.h"
13 #include "esp_attr.h"
14 #include "soc/soc.h"
15 #include "soc/rtc.h"
16 #include "soc/pmu_struct.h"
17 #include "hal/lp_aon_hal.h"
18 #include "esp_private/esp_pmu.h"
19 #include "pmu_param.h"
20 #include "hal/efuse_ll.h"
21 #include "hal/efuse_hal.h"
22 #include "esp_hw_log.h"
23
24 static __attribute__((unused)) const char *TAG = "pmu_sleep";
25
26 #define HP(state) (PMU_MODE_HP_ ## state)
27 #define LP(state) (PMU_MODE_LP_ ## state)
28
29 static bool s_pmu_sleep_regdma_backup_enabled;
30
get_lslp_dbg(void)31 uint32_t get_lslp_dbg(void)
32 {
33 uint32_t pmu_dbg_atten_lightsleep = PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT;
34 uint32_t blk_version = efuse_hal_blk_version();
35 if (blk_version >= 3) {
36 pmu_dbg_atten_lightsleep = efuse_ll_get_lslp_dbg();
37 } else {
38 ESP_HW_LOGD(TAG, "blk_version is less than 3, lslp dbg not burnt in efuse\n");
39 }
40
41 return pmu_dbg_atten_lightsleep;
42 }
43
get_lslp_hp_dbias(void)44 uint32_t get_lslp_hp_dbias(void)
45 {
46 uint32_t pmu_hp_dbias_lightsleep_0v6 = PMU_HP_DBIAS_LIGHTSLEEP_0V6_DEFAULT;
47 uint32_t blk_version = efuse_hal_blk_version();
48 if (blk_version >= 3) {
49 pmu_hp_dbias_lightsleep_0v6 = efuse_ll_get_lslp_hp_dbias();
50 } else {
51 ESP_HW_LOGD(TAG, "blk_version is less than 3, lslp hp dbias not burnt in efuse\n");
52 }
53
54 return pmu_hp_dbias_lightsleep_0v6;
55 }
56
get_dslp_dbg(void)57 uint32_t get_dslp_dbg(void)
58 {
59 uint32_t pmu_dbg_atten_deepsleep = PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT;
60 uint32_t blk_version = efuse_hal_blk_version();
61 if (blk_version >= 3) {
62 pmu_dbg_atten_deepsleep = efuse_ll_get_dslp_dbg() + EFUSE_BURN_OFFSET_DSLP_DBG;
63 } else {
64 ESP_HW_LOGD(TAG, "blk_version is less than 3, dslp dbg not burnt in efuse\n");
65 }
66
67 return pmu_dbg_atten_deepsleep;
68 }
69
get_dslp_lp_dbias(void)70 uint32_t get_dslp_lp_dbias(void)
71 {
72 uint32_t pmu_lp_dbias_deepsleep_0v7 = PMU_LP_DBIAS_DEEPSLEEP_0V7_DEFAULT;
73 uint32_t blk_version = efuse_hal_blk_version();
74 if (blk_version >= 3) {
75 pmu_lp_dbias_deepsleep_0v7 = efuse_ll_get_dslp_lp_dbias() + EFUSE_BURN_OFFSET_DSLP_LP_DBIAS;
76 } else {
77 ESP_HW_LOGD(TAG, "blk_version is less than 3, dslp lp dbias not burnt in efuse\n");
78 }
79
80 return pmu_lp_dbias_deepsleep_0v7;
81 }
82
pmu_sleep_enable_regdma_backup(void)83 void pmu_sleep_enable_regdma_backup(void)
84 {
85 if(!s_pmu_sleep_regdma_backup_enabled){
86 assert(PMU_instance()->hal);
87 /* entry 0, 1, 2 is used by pmu HP_SLEEP and HP_ACTIVE, HP_SLEEP
88 * and HP_MODEM or HP_MODEM and HP_ACTIVE states switching,
89 * respectively. entry 3 is reserved, not used yet! */
90 pmu_hal_hp_set_sleep_active_backup_enable(PMU_instance()->hal);
91 pmu_hal_hp_set_sleep_modem_backup_enable(PMU_instance()->hal);
92 pmu_hal_hp_set_modem_active_backup_enable(PMU_instance()->hal);
93 s_pmu_sleep_regdma_backup_enabled = true;
94 }
95 }
96
pmu_sleep_disable_regdma_backup(void)97 void pmu_sleep_disable_regdma_backup(void)
98 {
99 if(s_pmu_sleep_regdma_backup_enabled){
100 assert(PMU_instance()->hal);
101 pmu_hal_hp_set_sleep_active_backup_disable(PMU_instance()->hal);
102 pmu_hal_hp_set_sleep_modem_backup_disable(PMU_instance()->hal);
103 pmu_hal_hp_set_modem_active_backup_disable(PMU_instance()->hal);
104 s_pmu_sleep_regdma_backup_enabled = false;
105 }
106 }
107
pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags,uint32_t slowclk_period,uint32_t fastclk_period)108 uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t pd_flags, uint32_t slowclk_period, uint32_t fastclk_period)
109 {
110 const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
111
112 /* LP core hardware wait time, microsecond */
113 const int lp_wakeup_wait_time_us = rtc_time_slowclk_to_us(mc->lp.wakeup_wait_cycle, slowclk_period);
114 const int lp_clk_switch_time_us = rtc_time_slowclk_to_us(mc->lp.clk_switch_cycle, slowclk_period);
115 const int lp_clk_power_on_wait_time_us = (pd_flags & PMU_SLEEP_PD_XTAL) ? mc->lp.xtal_wait_stable_time_us \
116 : rtc_time_slowclk_to_us(mc->lp.clk_power_on_wait_cycle, slowclk_period);
117
118 const int lp_hw_wait_time_us = mc->lp.min_slp_time_us + mc->lp.analog_wait_time_us + lp_clk_power_on_wait_time_us \
119 + lp_wakeup_wait_time_us + lp_clk_switch_time_us + mc->lp.power_supply_wait_time_us \
120 + mc->lp.power_up_wait_time_us;
121
122 /* HP core hardware wait time, microsecond */
123 const int hp_digital_power_up_wait_time_us = mc->hp.power_supply_wait_time_us + mc->hp.power_up_wait_time_us;
124 const int hp_regdma_wait_time_us = MAX(mc->hp.regdma_s2m_work_time_us + mc->hp.regdma_m2a_work_time_us, mc->hp.regdma_s2a_work_time_us);
125 const int hp_clock_wait_time_us = mc->hp.xtal_wait_stable_time_us + mc->hp.pll_wait_stable_time_us;
126
127 const int hp_hw_wait_time_us = mc->hp.analog_wait_time_us + MAX(hp_digital_power_up_wait_time_us + hp_regdma_wait_time_us, hp_clock_wait_time_us);
128
129 /* When the SOC wakeup (lp timer or GPIO wakeup) and Modem wakeup (Beacon wakeup) complete, the soc
130 * wakeup will be delayed until the RF is turned on in Modem state.
131 *
132 * modem wakeup TBTT, RF on by HW
133 * | |
134 * \|/ \|/
135 * PMU_HP_ACTIVE /------
136 * PMU_HP_MODEM /------------//////////////////
137 * PMU_HP_SLEEP ----------------------//////////////////
138 * /|\ /|\ /|\ /|\ /|\ /|\
139 * |<- some hw wait ->| | | |<- M2A switch ->|
140 * | slow cycles & | soc wakeup | |
141 * | FOSC cycles |<- S2M switch ->| |
142 * | |
143 * |<-- PMU guard time, also the maximum time for the SOC -->|
144 * | wake-up delay |
145 */
146 #if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
147 const int rf_on_protect_time_us = mc->hp.regdma_rf_on_work_time_us;
148 const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us + mc->hp.clock_domain_sync_time_us;
149 #else
150 const int rf_on_protect_time_us = 0;
151 const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us;
152 #endif
153 return total_hw_wait_time_us + rf_on_protect_time_us;
154 }
155
156 #define rtc_time_us_to_fastclk(time_us, period) rtc_time_us_to_slowclk((time_us), (period))
157
pmu_sleep_param_config_default(pmu_sleep_param_config_t * param,pmu_sleep_power_config_t * power,const uint32_t pd_flags,const uint32_t adjustment,const uint32_t slowclk_period,const uint32_t fastclk_period)158 static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
159 pmu_sleep_param_config_t *param,
160 pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
161 const uint32_t pd_flags,
162 const uint32_t adjustment,
163 const uint32_t slowclk_period,
164 const uint32_t fastclk_period
165 )
166 {
167 const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
168
169 param->hp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
170 param->hp_sys.analog_wait_target_cycle = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_us, fastclk_period);
171 param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_us, fastclk_period);
172 param->hp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period);
173 param->hp_sys.pll_stable_wait_cycle = rtc_time_us_to_fastclk(mc->hp.pll_wait_stable_time_us, fastclk_period);
174
175 const int hw_wait_time_us = pmu_sleep_calculate_hw_wait_time(pd_flags, slowclk_period, fastclk_period);
176 const int modem_state_skip_time_us = mc->hp.regdma_m2a_work_time_us + mc->hp.system_dfs_up_work_time_us + mc->lp.min_slp_time_us;
177 const int modem_wakeup_wait_time_us = adjustment - hw_wait_time_us + modem_state_skip_time_us + mc->hp.regdma_rf_on_work_time_us;
178 param->hp_sys.modem_wakeup_wait_cycle = rtc_time_us_to_fastclk(modem_wakeup_wait_time_us, fastclk_period);
179
180 param->lp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period);
181 param->lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_us, slowclk_period);
182 param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_us, fastclk_period);
183 param->lp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_us, fastclk_period);
184
185 if (power->hp_sys.xtal.xpd_xtal) {
186 param->hp_lp.xtal_stable_wait_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.xtal_wait_stable_time_us, slowclk_period);
187 } else {
188 param->hp_lp.xtal_stable_wait_cycle = rtc_time_us_to_fastclk(mc->hp.xtal_wait_stable_time_us, fastclk_period);
189 }
190 return param;
191 }
192
pmu_sleep_config_default(pmu_sleep_config_t * config,uint32_t pd_flags,uint32_t adjustment,uint32_t slowclk_period,uint32_t fastclk_period,bool dslp)193 const pmu_sleep_config_t* pmu_sleep_config_default(
194 pmu_sleep_config_t *config,
195 uint32_t pd_flags,
196 uint32_t adjustment,
197 uint32_t slowclk_period,
198 uint32_t fastclk_period,
199 bool dslp
200 )
201 {
202 pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(pd_flags);
203
204 config->power = power_default;
205
206 pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags);
207 config->param = *pmu_sleep_param_config_default(¶m_default, &power_default, pd_flags, adjustment, slowclk_period, fastclk_period);
208
209 if (dslp) {
210 config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
211 pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags);
212 analog_default.lp_sys[LP(SLEEP)].analog.dbg_atten = get_dslp_dbg();
213 analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_dslp_lp_dbias();
214 config->analog = analog_default;
215 } else {
216 pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(pd_flags);
217 config->digital = digital_default;
218
219 pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags);
220 analog_default.hp_sys.analog.dbg_atten = get_lslp_dbg();
221 analog_default.hp_sys.analog.dbias = get_lslp_hp_dbias();
222 analog_default.lp_sys[LP(SLEEP)].analog.dbias = PMU_LP_DBIAS_LIGHTSLEEP_0V7_DEFAULT;
223
224 if (!(pd_flags & PMU_SLEEP_PD_XTAL)){
225 analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
226 analog_default.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
227 analog_default.hp_sys.analog.dbg_atten = PMU_DBG_ATTEN_ACTIVE_DEFAULT;
228 analog_default.hp_sys.analog.dbias = get_act_hp_dbias();
229
230 analog_default.lp_sys[LP(SLEEP)].analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
231 analog_default.lp_sys[LP(SLEEP)].analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
232 analog_default.lp_sys[LP(SLEEP)].analog.dbg_atten = PMU_DBG_ATTEN_ACTIVE_DEFAULT;
233 analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_act_lp_dbias();
234 } else if (!(pd_flags & PMU_SLEEP_PD_RC_FAST)) {
235 analog_default.hp_sys.analog.dbias = get_act_hp_dbias();
236 analog_default.lp_sys[LP(SLEEP)].analog.dbg_atten = PMU_DBG_ATTEN_LIGHTSLEEP_NODROP;
237 analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_act_lp_dbias();
238 }
239
240 config->analog = analog_default;
241 }
242 return config;
243 }
244
pmu_sleep_power_init(pmu_context_t * ctx,const pmu_sleep_power_config_t * power,bool dslp)245 static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_config_t *power, bool dslp)
246 {
247 pmu_ll_hp_set_dig_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.dig_power.val);
248 pmu_ll_hp_set_clk_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.clk_power.val);
249 pmu_ll_hp_set_xtal_xpd (ctx->hal->dev, HP(SLEEP), power->hp_sys.xtal.xpd_xtal);
250
251 pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(ACTIVE), power->lp_sys[LP(ACTIVE)].dig_power.val);
252 pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(ACTIVE), power->lp_sys[LP(ACTIVE)].clk_power.val);
253
254 pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].dig_power.val);
255 pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].clk_power.val);
256 pmu_ll_lp_set_xtal_xpd (ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].xtal.xpd_xtal);
257 }
258
pmu_sleep_digital_init(pmu_context_t * ctx,const pmu_sleep_digital_config_t * dig)259 static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_config_t *dig)
260 {
261 pmu_ll_hp_set_dig_pad_slp_sel (ctx->hal->dev, HP(SLEEP), dig->syscntl.dig_pad_slp_sel);
262 }
263
pmu_sleep_analog_init(pmu_context_t * ctx,const pmu_sleep_analog_config_t * analog,bool dslp)264 static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_config_t *analog, bool dslp)
265 {
266 assert(ctx->hal);
267 pmu_ll_hp_set_dbg_atten (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbg_atten);
268 pmu_ll_hp_set_current_power_off (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.pd_cur);
269 pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.bias_sleep);
270 pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd);
271 pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias);
272 pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b);
273
274 pmu_ll_lp_set_dbg_atten (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbg_atten);
275 pmu_ll_lp_set_current_power_off (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur);
276 pmu_ll_lp_set_bias_sleep_enable (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.bias_sleep);
277 pmu_ll_lp_set_regulator_slp_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_xpd);
278 pmu_ll_lp_set_regulator_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.xpd);
279 pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_dbias);
280 pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbias);
281 pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.drv_b);
282 }
283
pmu_sleep_param_init(pmu_context_t * ctx,const pmu_sleep_param_config_t * param,bool dslp)284 static void pmu_sleep_param_init(pmu_context_t *ctx, const pmu_sleep_param_config_t *param, bool dslp)
285 {
286 assert(ctx->hal);
287 pmu_ll_hp_set_min_sleep_cycle(ctx->hal->dev, param->hp_sys.min_slp_slow_clk_cycle);
288 pmu_ll_lp_set_min_sleep_cycle(ctx->hal->dev, param->lp_sys.min_slp_slow_clk_cycle);
289
290 pmu_ll_hp_set_analog_wait_target_cycle(ctx->hal->dev, param->hp_sys.analog_wait_target_cycle);
291 pmu_ll_lp_set_analog_wait_target_cycle(ctx->hal->dev, param->lp_sys.analog_wait_target_cycle);
292
293 pmu_hal_hp_set_digital_power_up_wait_cycle(ctx->hal, param->hp_sys.digital_power_supply_wait_cycle, param->hp_sys.digital_power_up_wait_cycle);
294 pmu_hal_lp_set_digital_power_up_wait_cycle(ctx->hal, param->lp_sys.digital_power_supply_wait_cycle, param->lp_sys.digital_power_up_wait_cycle);
295
296 pmu_ll_set_modem_wait_target_cycle(ctx->hal->dev, param->hp_sys.modem_wakeup_wait_cycle);
297 pmu_ll_set_xtal_stable_wait_cycle(ctx->hal->dev, param->hp_lp.xtal_stable_wait_slow_clk_cycle);
298 pmu_ll_set_pll_stable_wait_cycle(ctx->hal->dev, param->hp_sys.pll_stable_wait_cycle);
299 }
300
pmu_sleep_pll_already_enabled(void)301 bool pmu_sleep_pll_already_enabled(void)
302 {
303 return (pmu_ll_get_sysclk_sleep_select_state(PMU_instance()->hal->dev) != 0);
304 }
305
pmu_sleep_init(const pmu_sleep_config_t * config,bool dslp)306 void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp)
307 {
308 assert(PMU_instance());
309 pmu_sleep_power_init(PMU_instance(), &config->power, dslp);
310 if(!dslp){
311 pmu_sleep_digital_init(PMU_instance(), &config->digital);
312 }
313 pmu_sleep_analog_init(PMU_instance(), &config->analog, dslp);
314 pmu_sleep_param_init(PMU_instance(), &config->param, dslp);
315 }
316
pmu_sleep_start(uint32_t wakeup_opt,uint32_t reject_opt,uint32_t lslp_mem_inf_fpu,bool dslp)317 uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
318 {
319 assert(PMU_instance()->hal);
320
321 lp_aon_hal_inform_wakeup_type(dslp);
322
323 pmu_ll_hp_set_wakeup_enable(PMU_instance()->hal->dev, wakeup_opt);
324 pmu_ll_hp_set_reject_enable(PMU_instance()->hal->dev, reject_opt);
325
326 pmu_ll_hp_clear_wakeup_intr_status(PMU_instance()->hal->dev);
327 pmu_ll_hp_clear_reject_intr_status(PMU_instance()->hal->dev);
328 pmu_ll_hp_clear_reject_cause(PMU_instance()->hal->dev);
329
330 /* Start entry into sleep mode */
331 pmu_ll_hp_set_sleep_enable(PMU_instance()->hal->dev);
332
333 /* In pd_cpu lightsleep and deepsleep mode, we never get here */
334 while (!pmu_ll_hp_is_sleep_wakeup(PMU_instance()->hal->dev) &&
335 !pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev)) {
336 ;
337 }
338
339 return pmu_sleep_finish();
340 }
341
pmu_sleep_finish(void)342 bool pmu_sleep_finish(void)
343 {
344 // Wait eFuse memory update done.
345 while(efuse_ll_get_controller_state() != EFUSE_CONTROLLER_STATE_IDLE);
346
347 return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev);
348 }
349
pmu_sleep_enable_hp_sleep_sysclk(bool enable)350 void pmu_sleep_enable_hp_sleep_sysclk(bool enable)
351 {
352 pmu_ll_hp_set_icg_sysclk_enable(PMU_instance()->hal->dev, HP(SLEEP), enable);
353 }
354
pmu_sleep_get_wakup_retention_cost(void)355 uint32_t pmu_sleep_get_wakup_retention_cost(void)
356 {
357 const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
358 return mc->hp.regdma_s2a_work_time_us;
359 }
360
