1 /* 2 * Copyright (c) 2023 ENE Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/init.h> 8 #include <zephyr/devicetree.h> 9 #include <reg/pmu.h> 10 #include <reg/gcfg.h> 11 12 #define PMU_BASE DT_REG_ADDR(DT_NODELABEL(pmu)) 13 #define GCFG_BASE DT_REG_ADDR(DT_NODELABEL(gcfg)) 14 pmu_init(void)15static void pmu_init(void) 16 { 17 struct pmu_regs *pmu = ((struct pmu_regs *)PMU_BASE); 18 19 /* Interrupt Event Wakeup from IDLE mode Enable */ 20 pmu->PMUIDLE |= PMU_IDLE_WU_ENABLE; 21 /* GPTD wake up from STOP mode enable. */ 22 pmu->PMUSTOP |= PMU_STOP_WU_GPTD; 23 /* SWD EDI32 wake up from STOP mode enable */ 24 pmu->PMUSTOP |= (PMU_STOP_WU_EDI32 | PMU_STOP_WU_SWD); 25 } clock_init(void)26static void clock_init(void) 27 { 28 struct gcfg_regs *gcfg = ((struct gcfg_regs *)GCFG_BASE); 29 30 if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 96000000) { 31 /* AHB/APB clock select 96MHz/48MHz */ 32 gcfg->CLKCFG = GCFG_CLKCFG_96M; 33 } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 48000000) { 34 /* AHB/APB clock select 48MHz/24MHz */ 35 gcfg->CLKCFG = GCFG_CLKCFG_48M; 36 } else { 37 /* AHB/APB clock select 24MHz/12MHz */ 38 gcfg->CLKCFG = GCFG_CLKCFG_24M; 39 } 40 } 41 soc_early_init_hook(void)42void soc_early_init_hook(void) 43 { 44 clock_init(); 45 pmu_init(); 46 } 47