1 /** 2 * @file gcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup gcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_GCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_GCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup gcr 67 * @defgroup gcr_registers GCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 69 * @details Global Control Registers. 70 */ 71 72 /** 73 * @ingroup gcr_registers 74 * Structure type to access the GCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t scon; /**< <tt>\b 0x00:</tt> GCR SCON Register */ 78 __IO uint32_t rst0; /**< <tt>\b 0x04:</tt> GCR RST0 Register */ 79 __IO uint32_t clk_ctrl; /**< <tt>\b 0x08:</tt> GCR CLK_CTRL Register */ 80 __IO uint32_t pmr; /**< <tt>\b 0x0C:</tt> GCR PMR Register */ 81 __R uint32_t rsv_0x10_0x17[2]; 82 __IO uint32_t pclk_div; /**< <tt>\b 0x18:</tt> GCR PCLK_DIV Register */ 83 __R uint32_t rsv_0x1c_0x23[2]; 84 __IO uint32_t pclk_dis0; /**< <tt>\b 0x24:</tt> GCR PCLK_DIS0 Register */ 85 __IO uint32_t mem_clk; /**< <tt>\b 0x28:</tt> GCR MEM_CLK Register */ 86 __IO uint32_t mem_zero; /**< <tt>\b 0x2C:</tt> GCR MEM_ZERO Register */ 87 __R uint32_t rsv_0x30_0x3f[4]; 88 __IO uint32_t sys_stat; /**< <tt>\b 0x40:</tt> GCR SYS_STAT Register */ 89 __IO uint32_t rst1; /**< <tt>\b 0x44:</tt> GCR RST1 Register */ 90 __IO uint32_t pclk_dis1; /**< <tt>\b 0x48:</tt> GCR PCLK_DIS1 Register */ 91 __IO uint32_t event_en; /**< <tt>\b 0x4C:</tt> GCR EVENT_EN Register */ 92 __I uint32_t rev; /**< <tt>\b 0x50:</tt> GCR REV Register */ 93 __IO uint32_t sys_stat_ie; /**< <tt>\b 0x54:</tt> GCR SYS_STAT_IE Register */ 94 } mxc_gcr_regs_t; 95 96 /* Register offsets for module GCR */ 97 /** 98 * @ingroup gcr_registers 99 * @defgroup GCR_Register_Offsets Register Offsets 100 * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. 101 * @{ 102 */ 103 #define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */ 104 #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */ 105 #define MXC_R_GCR_CLK_CTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */ 106 #define MXC_R_GCR_PMR ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */ 107 #define MXC_R_GCR_PCLK_DIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */ 108 #define MXC_R_GCR_PCLK_DIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */ 109 #define MXC_R_GCR_MEM_CLK ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */ 110 #define MXC_R_GCR_MEM_ZERO ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */ 111 #define MXC_R_GCR_SYS_STAT ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */ 112 #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */ 113 #define MXC_R_GCR_PCLK_DIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */ 114 #define MXC_R_GCR_EVENT_EN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */ 115 #define MXC_R_GCR_REV ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */ 116 #define MXC_R_GCR_SYS_STAT_IE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */ 117 /**@} end of group gcr_registers */ 118 119 /** 120 * @ingroup gcr_registers 121 * @defgroup GCR_SCON GCR_SCON 122 * @brief System Control. 123 * @{ 124 */ 125 #define MXC_F_GCR_SCON_BSTAPEN_POS 0 /**< SCON_BSTAPEN Position */ 126 #define MXC_F_GCR_SCON_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SCON_BSTAPEN_POS)) /**< SCON_BSTAPEN Mask */ 127 #define MXC_V_GCR_SCON_BSTAPEN_DIS ((uint32_t)0x0UL) /**< SCON_BSTAPEN_DIS Value */ 128 #define MXC_S_GCR_SCON_BSTAPEN_DIS (MXC_V_GCR_SCON_BSTAPEN_DIS << MXC_F_GCR_SCON_BSTAPEN_POS) /**< SCON_BSTAPEN_DIS Setting */ 129 #define MXC_V_GCR_SCON_BSTAPEN_EN ((uint32_t)0x1UL) /**< SCON_BSTAPEN_EN Value */ 130 #define MXC_S_GCR_SCON_BSTAPEN_EN (MXC_V_GCR_SCON_BSTAPEN_EN << MXC_F_GCR_SCON_BSTAPEN_POS) /**< SCON_BSTAPEN_EN Setting */ 131 132 #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */ 133 #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */ 134 #define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL ((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */ 135 #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_NORMAL Setting */ 136 #define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_FLIPPED ((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_FLIPPED Value */ 137 #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_FLIPPED (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_FLIPPED << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_FLIPPED Setting */ 138 139 #define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */ 140 #define MXC_F_GCR_SCON_CCACHE_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH Mask */ 141 #define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL ((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */ 142 #define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL (MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL Setting */ 143 #define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH ((uint32_t)0x1UL) /**< SCON_CCACHE_FLUSH_FLUSH Value */ 144 #define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH (MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH Setting */ 145 146 #define MXC_F_GCR_SCON_DCACHE_FLUSH_POS 7 /**< SCON_DCACHE_FLUSH Position */ 147 #define MXC_F_GCR_SCON_DCACHE_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_DCACHE_FLUSH_POS)) /**< SCON_DCACHE_FLUSH Mask */ 148 #define MXC_V_GCR_SCON_DCACHE_FLUSH_NORMAL ((uint32_t)0x0UL) /**< SCON_DCACHE_FLUSH_NORMAL Value */ 149 #define MXC_S_GCR_SCON_DCACHE_FLUSH_NORMAL (MXC_V_GCR_SCON_DCACHE_FLUSH_NORMAL << MXC_F_GCR_SCON_DCACHE_FLUSH_POS) /**< SCON_DCACHE_FLUSH_NORMAL Setting */ 150 #define MXC_V_GCR_SCON_DCACHE_FLUSH_FLUSH ((uint32_t)0x1UL) /**< SCON_DCACHE_FLUSH_FLUSH Value */ 151 #define MXC_S_GCR_SCON_DCACHE_FLUSH_FLUSH (MXC_V_GCR_SCON_DCACHE_FLUSH_FLUSH << MXC_F_GCR_SCON_DCACHE_FLUSH_POS) /**< SCON_DCACHE_FLUSH_FLUSH Setting */ 152 153 #define MXC_F_GCR_SCON_DCACHE_DIS_POS 9 /**< SCON_DCACHE_DIS Position */ 154 #define MXC_F_GCR_SCON_DCACHE_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_DCACHE_DIS_POS)) /**< SCON_DCACHE_DIS Mask */ 155 #define MXC_V_GCR_SCON_DCACHE_DIS_ENABLED ((uint32_t)0x0UL) /**< SCON_DCACHE_DIS_ENABLED Value */ 156 #define MXC_S_GCR_SCON_DCACHE_DIS_ENABLED (MXC_V_GCR_SCON_DCACHE_DIS_ENABLED << MXC_F_GCR_SCON_DCACHE_DIS_POS) /**< SCON_DCACHE_DIS_ENABLED Setting */ 157 #define MXC_V_GCR_SCON_DCACHE_DIS_DISABLED ((uint32_t)0x1UL) /**< SCON_DCACHE_DIS_DISABLED Value */ 158 #define MXC_S_GCR_SCON_DCACHE_DIS_DISABLED (MXC_V_GCR_SCON_DCACHE_DIS_DISABLED << MXC_F_GCR_SCON_DCACHE_DIS_POS) /**< SCON_DCACHE_DIS_DISABLED Setting */ 159 160 #define MXC_F_GCR_SCON_CCHK_POS 13 /**< SCON_CCHK Position */ 161 #define MXC_F_GCR_SCON_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCHK_POS)) /**< SCON_CCHK Mask */ 162 #define MXC_V_GCR_SCON_CCHK_COMPLETE ((uint32_t)0x0UL) /**< SCON_CCHK_COMPLETE Value */ 163 #define MXC_S_GCR_SCON_CCHK_COMPLETE (MXC_V_GCR_SCON_CCHK_COMPLETE << MXC_F_GCR_SCON_CCHK_POS) /**< SCON_CCHK_COMPLETE Setting */ 164 #define MXC_V_GCR_SCON_CCHK_START ((uint32_t)0x1UL) /**< SCON_CCHK_START Value */ 165 #define MXC_S_GCR_SCON_CCHK_START (MXC_V_GCR_SCON_CCHK_START << MXC_F_GCR_SCON_CCHK_POS) /**< SCON_CCHK_START Setting */ 166 167 #define MXC_F_GCR_SCON_CHKRES_POS 15 /**< SCON_CHKRES Position */ 168 #define MXC_F_GCR_SCON_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CHKRES_POS)) /**< SCON_CHKRES Mask */ 169 #define MXC_V_GCR_SCON_CHKRES_PASS ((uint32_t)0x0UL) /**< SCON_CHKRES_PASS Value */ 170 #define MXC_S_GCR_SCON_CHKRES_PASS (MXC_V_GCR_SCON_CHKRES_PASS << MXC_F_GCR_SCON_CHKRES_POS) /**< SCON_CHKRES_PASS Setting */ 171 #define MXC_V_GCR_SCON_CHKRES_FAIL ((uint32_t)0x1UL) /**< SCON_CHKRES_FAIL Value */ 172 #define MXC_S_GCR_SCON_CHKRES_FAIL (MXC_V_GCR_SCON_CHKRES_FAIL << MXC_F_GCR_SCON_CHKRES_POS) /**< SCON_CHKRES_FAIL Setting */ 173 174 #define MXC_F_GCR_SCON_OVR_POS 16 /**< SCON_OVR Position */ 175 #define MXC_F_GCR_SCON_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SCON_OVR_POS)) /**< SCON_OVR Mask */ 176 #define MXC_V_GCR_SCON_OVR_0V9 ((uint32_t)0x0UL) /**< SCON_OVR_0V9 Value */ 177 #define MXC_S_GCR_SCON_OVR_0V9 (MXC_V_GCR_SCON_OVR_0V9 << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_0V9 Setting */ 178 #define MXC_V_GCR_SCON_OVR_1V ((uint32_t)0x1UL) /**< SCON_OVR_1V Value */ 179 #define MXC_S_GCR_SCON_OVR_1V (MXC_V_GCR_SCON_OVR_1V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_1V Setting */ 180 #define MXC_V_GCR_SCON_OVR_1V1 ((uint32_t)0x2UL) /**< SCON_OVR_1V1 Value */ 181 #define MXC_S_GCR_SCON_OVR_1V1 (MXC_V_GCR_SCON_OVR_1V1 << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_1V1 Setting */ 182 183 /**@} end of group GCR_SCON_Register */ 184 185 /** 186 * @ingroup gcr_registers 187 * @defgroup GCR_RST0 GCR_RST0 188 * @brief Reset. 189 * @{ 190 */ 191 #define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ 192 #define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ 193 194 #define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ 195 #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ 196 197 #define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ 198 #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ 199 200 #define MXC_F_GCR_RST0_GPIO1_POS 3 /**< RST0_GPIO1 Position */ 201 #define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */ 202 203 #define MXC_F_GCR_RST0_GPIO2_POS 4 /**< RST0_GPIO2 Position */ 204 #define MXC_F_GCR_RST0_GPIO2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO2_POS)) /**< RST0_GPIO2 Mask */ 205 206 #define MXC_F_GCR_RST0_TIMER0_POS 5 /**< RST0_TIMER0 Position */ 207 #define MXC_F_GCR_RST0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER0_POS)) /**< RST0_TIMER0 Mask */ 208 209 #define MXC_F_GCR_RST0_TIMER1_POS 6 /**< RST0_TIMER1 Position */ 210 #define MXC_F_GCR_RST0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER1_POS)) /**< RST0_TIMER1 Mask */ 211 212 #define MXC_F_GCR_RST0_TIMER2_POS 7 /**< RST0_TIMER2 Position */ 213 #define MXC_F_GCR_RST0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER2_POS)) /**< RST0_TIMER2 Mask */ 214 215 #define MXC_F_GCR_RST0_TIMER3_POS 8 /**< RST0_TIMER3 Position */ 216 #define MXC_F_GCR_RST0_TIMER3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER3_POS)) /**< RST0_TIMER3 Mask */ 217 218 #define MXC_F_GCR_RST0_TIMER4_POS 9 /**< RST0_TIMER4 Position */ 219 #define MXC_F_GCR_RST0_TIMER4 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER4_POS)) /**< RST0_TIMER4 Mask */ 220 221 #define MXC_F_GCR_RST0_TIMER5_POS 10 /**< RST0_TIMER5 Position */ 222 #define MXC_F_GCR_RST0_TIMER5 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER5_POS)) /**< RST0_TIMER5 Mask */ 223 224 #define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ 225 #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ 226 227 #define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ 228 #define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ 229 230 #define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */ 231 #define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */ 232 233 #define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ 234 #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ 235 236 #define MXC_F_GCR_RST0_SPI2_POS 15 /**< RST0_SPI2 Position */ 237 #define MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS)) /**< RST0_SPI2 Mask */ 238 239 #define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ 240 #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ 241 242 #define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ 243 #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ 244 245 #define MXC_F_GCR_RST0_TPU_POS 18 /**< RST0_TPU Position */ 246 #define MXC_F_GCR_RST0_TPU ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TPU_POS)) /**< RST0_TPU Mask */ 247 248 #define MXC_F_GCR_RST0_HBC_POS 21 /**< RST0_HBC Position */ 249 #define MXC_F_GCR_RST0_HBC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_HBC_POS)) /**< RST0_HBC Mask */ 250 251 #define MXC_F_GCR_RST0_TFT_POS 22 /**< RST0_TFT Position */ 252 #define MXC_F_GCR_RST0_TFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TFT_POS)) /**< RST0_TFT Mask */ 253 254 #define MXC_F_GCR_RST0_USB_POS 23 /**< RST0_USB Position */ 255 #define MXC_F_GCR_RST0_USB ((uint32_t)(0x1UL << MXC_F_GCR_RST0_USB_POS)) /**< RST0_USB Mask */ 256 257 #define MXC_F_GCR_RST0_ADC_POS 26 /**< RST0_ADC Position */ 258 #define MXC_F_GCR_RST0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_ADC_POS)) /**< RST0_ADC Mask */ 259 260 #define MXC_F_GCR_RST0_UART2_POS 28 /**< RST0_UART2 Position */ 261 #define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) /**< RST0_UART2 Mask */ 262 263 #define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ 264 #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ 265 266 #define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ 267 #define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ 268 269 #define MXC_F_GCR_RST0_SYS_POS 31 /**< RST0_SYS Position */ 270 #define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */ 271 272 /**@} end of group GCR_RST0_Register */ 273 274 /** 275 * @ingroup gcr_registers 276 * @defgroup GCR_CLK_CTRL GCR_CLK_CTRL 277 * @brief Clock Control. 278 * @{ 279 */ 280 #define MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS 6 /**< CLK_CTRL_SYSCLK_PRESCALE Position */ 281 #define MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS)) /**< CLK_CTRL_SYSCLK_PRESCALE Mask */ 282 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV1 ((uint32_t)0x0UL) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV1 Value */ 283 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV1 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV1 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV1 Setting */ 284 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV2 ((uint32_t)0x1UL) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV2 Value */ 285 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV2 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV2 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV2 Setting */ 286 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV4 ((uint32_t)0x2UL) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV4 Value */ 287 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV4 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV4 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV4 Setting */ 288 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV8 ((uint32_t)0x3UL) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV8 Value */ 289 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV8 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV8 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV8 Setting */ 290 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV16 ((uint32_t)0x4UL) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV16 Value */ 291 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV16 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV16 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV16 Setting */ 292 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV32 ((uint32_t)0x5UL) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV32 Value */ 293 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV32 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV32 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV32 Setting */ 294 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV64 ((uint32_t)0x6UL) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV64 Value */ 295 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV64 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV64 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV64 Setting */ 296 #define MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV128 ((uint32_t)0x7UL) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV128 Value */ 297 #define MXC_S_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV128 (MXC_V_GCR_CLK_CTRL_SYSCLK_PRESCALE_DIV128 << MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE_POS) /**< CLK_CTRL_SYSCLK_PRESCALE_DIV128 Setting */ 298 299 #define MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS 9 /**< CLK_CTRL_SYSOSC_SEL Position */ 300 #define MXC_F_GCR_CLK_CTRL_SYSOSC_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS)) /**< CLK_CTRL_SYSOSC_SEL Mask */ 301 #define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_CRYPTO ((uint32_t)0x0UL) /**< CLK_CTRL_SYSOSC_SEL_CRYPTO Value */ 302 #define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_CRYPTO (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_CRYPTO << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) /**< CLK_CTRL_SYSOSC_SEL_CRYPTO Setting */ 303 #define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HFXIN ((uint32_t)0x2UL) /**< CLK_CTRL_SYSOSC_SEL_HFXIN Value */ 304 #define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_HFXIN (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HFXIN << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) /**< CLK_CTRL_SYSOSC_SEL_HFXIN Setting */ 305 #define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_NANORING ((uint32_t)0x3UL) /**< CLK_CTRL_SYSOSC_SEL_NANORING Value */ 306 #define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_NANORING (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_NANORING << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) /**< CLK_CTRL_SYSOSC_SEL_NANORING Setting */ 307 #define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96 ((uint32_t)0x4UL) /**< CLK_CTRL_SYSOSC_SEL_HIRC96 Value */ 308 #define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96 (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC96 << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) /**< CLK_CTRL_SYSOSC_SEL_HIRC96 Setting */ 309 #define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8 ((uint32_t)0x5UL) /**< CLK_CTRL_SYSOSC_SEL_HIRC8 Value */ 310 #define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8 (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_HIRC8 << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) /**< CLK_CTRL_SYSOSC_SEL_HIRC8 Setting */ 311 #define MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_X32K ((uint32_t)0x6UL) /**< CLK_CTRL_SYSOSC_SEL_X32K Value */ 312 #define MXC_S_GCR_CLK_CTRL_SYSOSC_SEL_X32K (MXC_V_GCR_CLK_CTRL_SYSOSC_SEL_X32K << MXC_F_GCR_CLK_CTRL_SYSOSC_SEL_POS) /**< CLK_CTRL_SYSOSC_SEL_X32K Setting */ 313 314 #define MXC_F_GCR_CLK_CTRL_SYSOSC_RDY_POS 13 /**< CLK_CTRL_SYSOSC_RDY Position */ 315 #define MXC_F_GCR_CLK_CTRL_SYSOSC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_SYSOSC_RDY_POS)) /**< CLK_CTRL_SYSOSC_RDY Mask */ 316 #define MXC_V_GCR_CLK_CTRL_SYSOSC_RDY_BUSY ((uint32_t)0x0UL) /**< CLK_CTRL_SYSOSC_RDY_BUSY Value */ 317 #define MXC_S_GCR_CLK_CTRL_SYSOSC_RDY_BUSY (MXC_V_GCR_CLK_CTRL_SYSOSC_RDY_BUSY << MXC_F_GCR_CLK_CTRL_SYSOSC_RDY_POS) /**< CLK_CTRL_SYSOSC_RDY_BUSY Setting */ 318 #define MXC_V_GCR_CLK_CTRL_SYSOSC_RDY_READY ((uint32_t)0x1UL) /**< CLK_CTRL_SYSOSC_RDY_READY Value */ 319 #define MXC_S_GCR_CLK_CTRL_SYSOSC_RDY_READY (MXC_V_GCR_CLK_CTRL_SYSOSC_RDY_READY << MXC_F_GCR_CLK_CTRL_SYSOSC_RDY_POS) /**< CLK_CTRL_SYSOSC_RDY_READY Setting */ 320 321 #define MXC_F_GCR_CLK_CTRL_CCD_POS 15 /**< CLK_CTRL_CCD Position */ 322 #define MXC_F_GCR_CLK_CTRL_CCD ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CCD_POS)) /**< CLK_CTRL_CCD Mask */ 323 #define MXC_V_GCR_CLK_CTRL_CCD_NON_DIV ((uint32_t)0x0UL) /**< CLK_CTRL_CCD_NON_DIV Value */ 324 #define MXC_S_GCR_CLK_CTRL_CCD_NON_DIV (MXC_V_GCR_CLK_CTRL_CCD_NON_DIV << MXC_F_GCR_CLK_CTRL_CCD_POS) /**< CLK_CTRL_CCD_NON_DIV Setting */ 325 #define MXC_V_GCR_CLK_CTRL_CCD_DIV ((uint32_t)0x1UL) /**< CLK_CTRL_CCD_DIV Value */ 326 #define MXC_S_GCR_CLK_CTRL_CCD_DIV (MXC_V_GCR_CLK_CTRL_CCD_DIV << MXC_F_GCR_CLK_CTRL_CCD_POS) /**< CLK_CTRL_CCD_DIV Setting */ 327 328 #define MXC_F_GCR_CLK_CTRL_X32K_EN_POS 17 /**< CLK_CTRL_X32K_EN Position */ 329 #define MXC_F_GCR_CLK_CTRL_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_EN_POS)) /**< CLK_CTRL_X32K_EN Mask */ 330 331 #define MXC_F_GCR_CLK_CTRL_CRYPTO_EN_POS 18 /**< CLK_CTRL_CRYPTO_EN Position */ 332 #define MXC_F_GCR_CLK_CTRL_CRYPTO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CRYPTO_EN_POS)) /**< CLK_CTRL_CRYPTO_EN Mask */ 333 334 #define MXC_F_GCR_CLK_CTRL_HIRC96_EN_POS 19 /**< CLK_CTRL_HIRC96_EN Position */ 335 #define MXC_F_GCR_CLK_CTRL_HIRC96_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC96_EN_POS)) /**< CLK_CTRL_HIRC96_EN Mask */ 336 337 #define MXC_F_GCR_CLK_CTRL_HIRC8_EN_POS 20 /**< CLK_CTRL_HIRC8_EN Position */ 338 #define MXC_F_GCR_CLK_CTRL_HIRC8_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC8_EN_POS)) /**< CLK_CTRL_HIRC8_EN Mask */ 339 340 #define MXC_F_GCR_CLK_CTRL_HIRC8_VS_POS 21 /**< CLK_CTRL_HIRC8_VS Position */ 341 #define MXC_F_GCR_CLK_CTRL_HIRC8_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC8_VS_POS)) /**< CLK_CTRL_HIRC8_VS Mask */ 342 343 #define MXC_F_GCR_CLK_CTRL_X32K_RDY_POS 25 /**< CLK_CTRL_X32K_RDY Position */ 344 #define MXC_F_GCR_CLK_CTRL_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_RDY_POS)) /**< CLK_CTRL_X32K_RDY Mask */ 345 346 #define MXC_F_GCR_CLK_CTRL_CRYPTO_RDY_POS 26 /**< CLK_CTRL_CRYPTO_RDY Position */ 347 #define MXC_F_GCR_CLK_CTRL_CRYPTO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CRYPTO_RDY_POS)) /**< CLK_CTRL_CRYPTO_RDY Mask */ 348 349 #define MXC_F_GCR_CLK_CTRL_HIRC96_RDY_POS 27 /**< CLK_CTRL_HIRC96_RDY Position */ 350 #define MXC_F_GCR_CLK_CTRL_HIRC96_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC96_RDY_POS)) /**< CLK_CTRL_HIRC96_RDY Mask */ 351 352 #define MXC_F_GCR_CLK_CTRL_HIRC8_RDY_POS 28 /**< CLK_CTRL_HIRC8_RDY Position */ 353 #define MXC_F_GCR_CLK_CTRL_HIRC8_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC8_RDY_POS)) /**< CLK_CTRL_HIRC8_RDY Mask */ 354 355 #define MXC_F_GCR_CLK_CTRL_NANORING_RDY_POS 29 /**< CLK_CTRL_NANORING_RDY Position */ 356 #define MXC_F_GCR_CLK_CTRL_NANORING_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_NANORING_RDY_POS)) /**< CLK_CTRL_NANORING_RDY Mask */ 357 358 /**@} end of group GCR_CLK_CTRL_Register */ 359 360 /** 361 * @ingroup gcr_registers 362 * @defgroup GCR_PMR GCR_PMR 363 * @brief Power Management. 364 * @{ 365 */ 366 #define MXC_F_GCR_PMR_MODE_POS 0 /**< PMR_MODE Position */ 367 #define MXC_F_GCR_PMR_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PMR_MODE_POS)) /**< PMR_MODE Mask */ 368 #define MXC_V_GCR_PMR_MODE_ACTIVE ((uint32_t)0x0UL) /**< PMR_MODE_ACTIVE Value */ 369 #define MXC_S_GCR_PMR_MODE_ACTIVE (MXC_V_GCR_PMR_MODE_ACTIVE << MXC_F_GCR_PMR_MODE_POS) /**< PMR_MODE_ACTIVE Setting */ 370 #define MXC_V_GCR_PMR_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PMR_MODE_SHUTDOWN Value */ 371 #define MXC_S_GCR_PMR_MODE_SHUTDOWN (MXC_V_GCR_PMR_MODE_SHUTDOWN << MXC_F_GCR_PMR_MODE_POS) /**< PMR_MODE_SHUTDOWN Setting */ 372 #define MXC_V_GCR_PMR_MODE_BACKUP ((uint32_t)0x4UL) /**< PMR_MODE_BACKUP Value */ 373 #define MXC_S_GCR_PMR_MODE_BACKUP (MXC_V_GCR_PMR_MODE_BACKUP << MXC_F_GCR_PMR_MODE_POS) /**< PMR_MODE_BACKUP Setting */ 374 375 #define MXC_F_GCR_PMR_GPIOWKEN_POS 4 /**< PMR_GPIOWKEN Position */ 376 #define MXC_F_GCR_PMR_GPIOWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PMR_GPIOWKEN_POS)) /**< PMR_GPIOWKEN Mask */ 377 378 #define MXC_F_GCR_PMR_RTCWKEN_POS 5 /**< PMR_RTCWKEN Position */ 379 #define MXC_F_GCR_PMR_RTCWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PMR_RTCWKEN_POS)) /**< PMR_RTCWKEN Mask */ 380 381 #define MXC_F_GCR_PMR_USBWKEN_POS 6 /**< PMR_USBWKEN Position */ 382 #define MXC_F_GCR_PMR_USBWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PMR_USBWKEN_POS)) /**< PMR_USBWKEN Mask */ 383 384 #define MXC_F_GCR_PMR_CRYPTOPD_POS 15 /**< PMR_CRYPTOPD Position */ 385 #define MXC_F_GCR_PMR_CRYPTOPD ((uint32_t)(0x1UL << MXC_F_GCR_PMR_CRYPTOPD_POS)) /**< PMR_CRYPTOPD Mask */ 386 #define MXC_V_GCR_PMR_CRYPTOPD_ACTIVE ((uint32_t)0x0UL) /**< PMR_CRYPTOPD_ACTIVE Value */ 387 #define MXC_S_GCR_PMR_CRYPTOPD_ACTIVE (MXC_V_GCR_PMR_CRYPTOPD_ACTIVE << MXC_F_GCR_PMR_CRYPTOPD_POS) /**< PMR_CRYPTOPD_ACTIVE Setting */ 388 #define MXC_V_GCR_PMR_CRYPTOPD_DEEPSLEEP ((uint32_t)0x1UL) /**< PMR_CRYPTOPD_DEEPSLEEP Value */ 389 #define MXC_S_GCR_PMR_CRYPTOPD_DEEPSLEEP (MXC_V_GCR_PMR_CRYPTOPD_DEEPSLEEP << MXC_F_GCR_PMR_CRYPTOPD_POS) /**< PMR_CRYPTOPD_DEEPSLEEP Setting */ 390 391 #define MXC_F_GCR_PMR_HIRC96PD_POS 16 /**< PMR_HIRC96PD Position */ 392 #define MXC_F_GCR_PMR_HIRC96PD ((uint32_t)(0x1UL << MXC_F_GCR_PMR_HIRC96PD_POS)) /**< PMR_HIRC96PD Mask */ 393 #define MXC_V_GCR_PMR_HIRC96PD_ACTIVE ((uint32_t)0x0UL) /**< PMR_HIRC96PD_ACTIVE Value */ 394 #define MXC_S_GCR_PMR_HIRC96PD_ACTIVE (MXC_V_GCR_PMR_HIRC96PD_ACTIVE << MXC_F_GCR_PMR_HIRC96PD_POS) /**< PMR_HIRC96PD_ACTIVE Setting */ 395 #define MXC_V_GCR_PMR_HIRC96PD_DEEPSLEEP ((uint32_t)0x1UL) /**< PMR_HIRC96PD_DEEPSLEEP Value */ 396 #define MXC_S_GCR_PMR_HIRC96PD_DEEPSLEEP (MXC_V_GCR_PMR_HIRC96PD_DEEPSLEEP << MXC_F_GCR_PMR_HIRC96PD_POS) /**< PMR_HIRC96PD_DEEPSLEEP Setting */ 397 398 #define MXC_F_GCR_PMR_HIRC8PD_POS 17 /**< PMR_HIRC8PD Position */ 399 #define MXC_F_GCR_PMR_HIRC8PD ((uint32_t)(0x1UL << MXC_F_GCR_PMR_HIRC8PD_POS)) /**< PMR_HIRC8PD Mask */ 400 #define MXC_V_GCR_PMR_HIRC8PD_ACTIVE ((uint32_t)0x0UL) /**< PMR_HIRC8PD_ACTIVE Value */ 401 #define MXC_S_GCR_PMR_HIRC8PD_ACTIVE (MXC_V_GCR_PMR_HIRC8PD_ACTIVE << MXC_F_GCR_PMR_HIRC8PD_POS) /**< PMR_HIRC8PD_ACTIVE Setting */ 402 #define MXC_V_GCR_PMR_HIRC8PD_DEEPSLEEP ((uint32_t)0x1UL) /**< PMR_HIRC8PD_DEEPSLEEP Value */ 403 #define MXC_S_GCR_PMR_HIRC8PD_DEEPSLEEP (MXC_V_GCR_PMR_HIRC8PD_DEEPSLEEP << MXC_F_GCR_PMR_HIRC8PD_POS) /**< PMR_HIRC8PD_DEEPSLEEP Setting */ 404 405 /**@} end of group GCR_PMR_Register */ 406 407 /** 408 * @ingroup gcr_registers 409 * @defgroup GCR_PCLK_DIV GCR_PCLK_DIV 410 * @brief Peripheral Clock Divider. 411 * @{ 412 */ 413 #define MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS 7 /**< PCLK_DIV_SDHCFRQ Position */ 414 #define MXC_F_GCR_PCLK_DIV_SDHCFRQ ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS)) /**< PCLK_DIV_SDHCFRQ Mask */ 415 #define MXC_V_GCR_PCLK_DIV_SDHCFRQ_60M ((uint32_t)0x0UL) /**< PCLK_DIV_SDHCFRQ_60M Value */ 416 #define MXC_S_GCR_PCLK_DIV_SDHCFRQ_60M (MXC_V_GCR_PCLK_DIV_SDHCFRQ_60M << MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS) /**< PCLK_DIV_SDHCFRQ_60M Setting */ 417 #define MXC_V_GCR_PCLK_DIV_SDHCFRQ_50M ((uint32_t)0x1UL) /**< PCLK_DIV_SDHCFRQ_50M Value */ 418 #define MXC_S_GCR_PCLK_DIV_SDHCFRQ_50M (MXC_V_GCR_PCLK_DIV_SDHCFRQ_50M << MXC_F_GCR_PCLK_DIV_SDHCFRQ_POS) /**< PCLK_DIV_SDHCFRQ_50M Setting */ 419 420 #define MXC_F_GCR_PCLK_DIV_ADCFRQ_POS 10 /**< PCLK_DIV_ADCFRQ Position */ 421 #define MXC_F_GCR_PCLK_DIV_ADCFRQ ((uint32_t)(0xFUL << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS)) /**< PCLK_DIV_ADCFRQ Mask */ 422 #define MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV2 ((uint32_t)0x2UL) /**< PCLK_DIV_ADCFRQ_DIV2 Value */ 423 #define MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV2 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV2 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) /**< PCLK_DIV_ADCFRQ_DIV2 Setting */ 424 #define MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV3 ((uint32_t)0x3UL) /**< PCLK_DIV_ADCFRQ_DIV3 Value */ 425 #define MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV3 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV3 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) /**< PCLK_DIV_ADCFRQ_DIV3 Setting */ 426 #define MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV4 ((uint32_t)0x4UL) /**< PCLK_DIV_ADCFRQ_DIV4 Value */ 427 #define MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV4 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV4 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) /**< PCLK_DIV_ADCFRQ_DIV4 Setting */ 428 #define MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV5 ((uint32_t)0x5UL) /**< PCLK_DIV_ADCFRQ_DIV5 Value */ 429 #define MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV5 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV5 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) /**< PCLK_DIV_ADCFRQ_DIV5 Setting */ 430 #define MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV6 ((uint32_t)0x6UL) /**< PCLK_DIV_ADCFRQ_DIV6 Value */ 431 #define MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV6 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV6 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) /**< PCLK_DIV_ADCFRQ_DIV6 Setting */ 432 #define MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV7 ((uint32_t)0x7UL) /**< PCLK_DIV_ADCFRQ_DIV7 Value */ 433 #define MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV7 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV7 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) /**< PCLK_DIV_ADCFRQ_DIV7 Setting */ 434 #define MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV8 ((uint32_t)0x8UL) /**< PCLK_DIV_ADCFRQ_DIV8 Value */ 435 #define MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV8 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV8 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) /**< PCLK_DIV_ADCFRQ_DIV8 Setting */ 436 #define MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV9 ((uint32_t)0x9UL) /**< PCLK_DIV_ADCFRQ_DIV9 Value */ 437 #define MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV9 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV9 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) /**< PCLK_DIV_ADCFRQ_DIV9 Setting */ 438 #define MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV10 ((uint32_t)0xAUL) /**< PCLK_DIV_ADCFRQ_DIV10 Value */ 439 #define MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV10 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV10 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) /**< PCLK_DIV_ADCFRQ_DIV10 Setting */ 440 #define MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV11 ((uint32_t)0xBUL) /**< PCLK_DIV_ADCFRQ_DIV11 Value */ 441 #define MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV11 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV11 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) /**< PCLK_DIV_ADCFRQ_DIV11 Setting */ 442 #define MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV12 ((uint32_t)0xCUL) /**< PCLK_DIV_ADCFRQ_DIV12 Value */ 443 #define MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV12 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV12 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) /**< PCLK_DIV_ADCFRQ_DIV12 Setting */ 444 #define MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV13 ((uint32_t)0xDUL) /**< PCLK_DIV_ADCFRQ_DIV13 Value */ 445 #define MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV13 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV13 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) /**< PCLK_DIV_ADCFRQ_DIV13 Setting */ 446 #define MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV14 ((uint32_t)0xEUL) /**< PCLK_DIV_ADCFRQ_DIV14 Value */ 447 #define MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV14 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV14 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) /**< PCLK_DIV_ADCFRQ_DIV14 Setting */ 448 #define MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV15 ((uint32_t)0xFUL) /**< PCLK_DIV_ADCFRQ_DIV15 Value */ 449 #define MXC_S_GCR_PCLK_DIV_ADCFRQ_DIV15 (MXC_V_GCR_PCLK_DIV_ADCFRQ_DIV15 << MXC_F_GCR_PCLK_DIV_ADCFRQ_POS) /**< PCLK_DIV_ADCFRQ_DIV15 Setting */ 450 451 #define MXC_F_GCR_PCLK_DIV_AONDIV_POS 14 /**< PCLK_DIV_AONDIV Position */ 452 #define MXC_F_GCR_PCLK_DIV_AONDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLK_DIV_AONDIV_POS)) /**< PCLK_DIV_AONDIV Mask */ 453 #define MXC_V_GCR_PCLK_DIV_AONDIV_DIV4 ((uint32_t)0x0UL) /**< PCLK_DIV_AONDIV_DIV4 Value */ 454 #define MXC_S_GCR_PCLK_DIV_AONDIV_DIV4 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV4 << MXC_F_GCR_PCLK_DIV_AONDIV_POS) /**< PCLK_DIV_AONDIV_DIV4 Setting */ 455 #define MXC_V_GCR_PCLK_DIV_AONDIV_DIV8 ((uint32_t)0x1UL) /**< PCLK_DIV_AONDIV_DIV8 Value */ 456 #define MXC_S_GCR_PCLK_DIV_AONDIV_DIV8 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV8 << MXC_F_GCR_PCLK_DIV_AONDIV_POS) /**< PCLK_DIV_AONDIV_DIV8 Setting */ 457 #define MXC_V_GCR_PCLK_DIV_AONDIV_DIV16 ((uint32_t)0x2UL) /**< PCLK_DIV_AONDIV_DIV16 Value */ 458 #define MXC_S_GCR_PCLK_DIV_AONDIV_DIV16 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV16 << MXC_F_GCR_PCLK_DIV_AONDIV_POS) /**< PCLK_DIV_AONDIV_DIV16 Setting */ 459 #define MXC_V_GCR_PCLK_DIV_AONDIV_DIV32 ((uint32_t)0x3UL) /**< PCLK_DIV_AONDIV_DIV32 Value */ 460 #define MXC_S_GCR_PCLK_DIV_AONDIV_DIV32 (MXC_V_GCR_PCLK_DIV_AONDIV_DIV32 << MXC_F_GCR_PCLK_DIV_AONDIV_POS) /**< PCLK_DIV_AONDIV_DIV32 Setting */ 461 462 /**@} end of group GCR_PCLK_DIV_Register */ 463 464 /** 465 * @ingroup gcr_registers 466 * @defgroup GCR_PCLK_DIS0 GCR_PCLK_DIS0 467 * @brief Peripheral Clock Disable. 468 * @{ 469 */ 470 #define MXC_F_GCR_PCLK_DIS0_GPIO0_POS 0 /**< PCLK_DIS0_GPIO0 Position */ 471 #define MXC_F_GCR_PCLK_DIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO0_POS)) /**< PCLK_DIS0_GPIO0 Mask */ 472 #define MXC_V_GCR_PCLK_DIS0_GPIO0_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_GPIO0_EN Value */ 473 #define MXC_S_GCR_PCLK_DIS0_GPIO0_EN (MXC_V_GCR_PCLK_DIS0_GPIO0_EN << MXC_F_GCR_PCLK_DIS0_GPIO0_POS) /**< PCLK_DIS0_GPIO0_EN Setting */ 474 #define MXC_V_GCR_PCLK_DIS0_GPIO0_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_GPIO0_DIS Value */ 475 #define MXC_S_GCR_PCLK_DIS0_GPIO0_DIS (MXC_V_GCR_PCLK_DIS0_GPIO0_DIS << MXC_F_GCR_PCLK_DIS0_GPIO0_POS) /**< PCLK_DIS0_GPIO0_DIS Setting */ 476 477 #define MXC_F_GCR_PCLK_DIS0_GPIO1_POS 1 /**< PCLK_DIS0_GPIO1 Position */ 478 #define MXC_F_GCR_PCLK_DIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO1_POS)) /**< PCLK_DIS0_GPIO1 Mask */ 479 #define MXC_V_GCR_PCLK_DIS0_GPIO1_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_GPIO1_EN Value */ 480 #define MXC_S_GCR_PCLK_DIS0_GPIO1_EN (MXC_V_GCR_PCLK_DIS0_GPIO1_EN << MXC_F_GCR_PCLK_DIS0_GPIO1_POS) /**< PCLK_DIS0_GPIO1_EN Setting */ 481 #define MXC_V_GCR_PCLK_DIS0_GPIO1_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_GPIO1_DIS Value */ 482 #define MXC_S_GCR_PCLK_DIS0_GPIO1_DIS (MXC_V_GCR_PCLK_DIS0_GPIO1_DIS << MXC_F_GCR_PCLK_DIS0_GPIO1_POS) /**< PCLK_DIS0_GPIO1_DIS Setting */ 483 484 #define MXC_F_GCR_PCLK_DIS0_GPIO2_POS 2 /**< PCLK_DIS0_GPIO2 Position */ 485 #define MXC_F_GCR_PCLK_DIS0_GPIO2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO2_POS)) /**< PCLK_DIS0_GPIO2 Mask */ 486 #define MXC_V_GCR_PCLK_DIS0_GPIO2_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_GPIO2_EN Value */ 487 #define MXC_S_GCR_PCLK_DIS0_GPIO2_EN (MXC_V_GCR_PCLK_DIS0_GPIO2_EN << MXC_F_GCR_PCLK_DIS0_GPIO2_POS) /**< PCLK_DIS0_GPIO2_EN Setting */ 488 #define MXC_V_GCR_PCLK_DIS0_GPIO2_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_GPIO2_DIS Value */ 489 #define MXC_S_GCR_PCLK_DIS0_GPIO2_DIS (MXC_V_GCR_PCLK_DIS0_GPIO2_DIS << MXC_F_GCR_PCLK_DIS0_GPIO2_POS) /**< PCLK_DIS0_GPIO2_DIS Setting */ 490 491 #define MXC_F_GCR_PCLK_DIS0_USB_POS 3 /**< PCLK_DIS0_USB Position */ 492 #define MXC_F_GCR_PCLK_DIS0_USB ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_USB_POS)) /**< PCLK_DIS0_USB Mask */ 493 #define MXC_V_GCR_PCLK_DIS0_USB_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_USB_EN Value */ 494 #define MXC_S_GCR_PCLK_DIS0_USB_EN (MXC_V_GCR_PCLK_DIS0_USB_EN << MXC_F_GCR_PCLK_DIS0_USB_POS) /**< PCLK_DIS0_USB_EN Setting */ 495 #define MXC_V_GCR_PCLK_DIS0_USB_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_USB_DIS Value */ 496 #define MXC_S_GCR_PCLK_DIS0_USB_DIS (MXC_V_GCR_PCLK_DIS0_USB_DIS << MXC_F_GCR_PCLK_DIS0_USB_POS) /**< PCLK_DIS0_USB_DIS Setting */ 497 498 #define MXC_F_GCR_PCLK_DIS0_TFT_POS 4 /**< PCLK_DIS0_TFT Position */ 499 #define MXC_F_GCR_PCLK_DIS0_TFT ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TFT_POS)) /**< PCLK_DIS0_TFT Mask */ 500 #define MXC_V_GCR_PCLK_DIS0_TFT_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_TFT_EN Value */ 501 #define MXC_S_GCR_PCLK_DIS0_TFT_EN (MXC_V_GCR_PCLK_DIS0_TFT_EN << MXC_F_GCR_PCLK_DIS0_TFT_POS) /**< PCLK_DIS0_TFT_EN Setting */ 502 #define MXC_V_GCR_PCLK_DIS0_TFT_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_TFT_DIS Value */ 503 #define MXC_S_GCR_PCLK_DIS0_TFT_DIS (MXC_V_GCR_PCLK_DIS0_TFT_DIS << MXC_F_GCR_PCLK_DIS0_TFT_POS) /**< PCLK_DIS0_TFT_DIS Setting */ 504 505 #define MXC_F_GCR_PCLK_DIS0_DMA_POS 5 /**< PCLK_DIS0_DMA Position */ 506 #define MXC_F_GCR_PCLK_DIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_DMA_POS)) /**< PCLK_DIS0_DMA Mask */ 507 #define MXC_V_GCR_PCLK_DIS0_DMA_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_DMA_EN Value */ 508 #define MXC_S_GCR_PCLK_DIS0_DMA_EN (MXC_V_GCR_PCLK_DIS0_DMA_EN << MXC_F_GCR_PCLK_DIS0_DMA_POS) /**< PCLK_DIS0_DMA_EN Setting */ 509 #define MXC_V_GCR_PCLK_DIS0_DMA_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_DMA_DIS Value */ 510 #define MXC_S_GCR_PCLK_DIS0_DMA_DIS (MXC_V_GCR_PCLK_DIS0_DMA_DIS << MXC_F_GCR_PCLK_DIS0_DMA_POS) /**< PCLK_DIS0_DMA_DIS Setting */ 511 512 #define MXC_F_GCR_PCLK_DIS0_SPI0_POS 6 /**< PCLK_DIS0_SPI0 Position */ 513 #define MXC_F_GCR_PCLK_DIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI0_POS)) /**< PCLK_DIS0_SPI0 Mask */ 514 #define MXC_V_GCR_PCLK_DIS0_SPI0_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_SPI0_EN Value */ 515 #define MXC_S_GCR_PCLK_DIS0_SPI0_EN (MXC_V_GCR_PCLK_DIS0_SPI0_EN << MXC_F_GCR_PCLK_DIS0_SPI0_POS) /**< PCLK_DIS0_SPI0_EN Setting */ 516 #define MXC_V_GCR_PCLK_DIS0_SPI0_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_SPI0_DIS Value */ 517 #define MXC_S_GCR_PCLK_DIS0_SPI0_DIS (MXC_V_GCR_PCLK_DIS0_SPI0_DIS << MXC_F_GCR_PCLK_DIS0_SPI0_POS) /**< PCLK_DIS0_SPI0_DIS Setting */ 518 519 #define MXC_F_GCR_PCLK_DIS0_SPI1_POS 7 /**< PCLK_DIS0_SPI1 Position */ 520 #define MXC_F_GCR_PCLK_DIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI1_POS)) /**< PCLK_DIS0_SPI1 Mask */ 521 #define MXC_V_GCR_PCLK_DIS0_SPI1_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_SPI1_EN Value */ 522 #define MXC_S_GCR_PCLK_DIS0_SPI1_EN (MXC_V_GCR_PCLK_DIS0_SPI1_EN << MXC_F_GCR_PCLK_DIS0_SPI1_POS) /**< PCLK_DIS0_SPI1_EN Setting */ 523 #define MXC_V_GCR_PCLK_DIS0_SPI1_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_SPI1_DIS Value */ 524 #define MXC_S_GCR_PCLK_DIS0_SPI1_DIS (MXC_V_GCR_PCLK_DIS0_SPI1_DIS << MXC_F_GCR_PCLK_DIS0_SPI1_POS) /**< PCLK_DIS0_SPI1_DIS Setting */ 525 526 #define MXC_F_GCR_PCLK_DIS0_SPI2_POS 8 /**< PCLK_DIS0_SPI2 Position */ 527 #define MXC_F_GCR_PCLK_DIS0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI2_POS)) /**< PCLK_DIS0_SPI2 Mask */ 528 #define MXC_V_GCR_PCLK_DIS0_SPI2_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_SPI2_EN Value */ 529 #define MXC_S_GCR_PCLK_DIS0_SPI2_EN (MXC_V_GCR_PCLK_DIS0_SPI2_EN << MXC_F_GCR_PCLK_DIS0_SPI2_POS) /**< PCLK_DIS0_SPI2_EN Setting */ 530 #define MXC_V_GCR_PCLK_DIS0_SPI2_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_SPI2_DIS Value */ 531 #define MXC_S_GCR_PCLK_DIS0_SPI2_DIS (MXC_V_GCR_PCLK_DIS0_SPI2_DIS << MXC_F_GCR_PCLK_DIS0_SPI2_POS) /**< PCLK_DIS0_SPI2_DIS Setting */ 532 533 #define MXC_F_GCR_PCLK_DIS0_UART0_POS 9 /**< PCLK_DIS0_UART0 Position */ 534 #define MXC_F_GCR_PCLK_DIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART0_POS)) /**< PCLK_DIS0_UART0 Mask */ 535 #define MXC_V_GCR_PCLK_DIS0_UART0_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_UART0_EN Value */ 536 #define MXC_S_GCR_PCLK_DIS0_UART0_EN (MXC_V_GCR_PCLK_DIS0_UART0_EN << MXC_F_GCR_PCLK_DIS0_UART0_POS) /**< PCLK_DIS0_UART0_EN Setting */ 537 #define MXC_V_GCR_PCLK_DIS0_UART0_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_UART0_DIS Value */ 538 #define MXC_S_GCR_PCLK_DIS0_UART0_DIS (MXC_V_GCR_PCLK_DIS0_UART0_DIS << MXC_F_GCR_PCLK_DIS0_UART0_POS) /**< PCLK_DIS0_UART0_DIS Setting */ 539 540 #define MXC_F_GCR_PCLK_DIS0_UART1_POS 10 /**< PCLK_DIS0_UART1 Position */ 541 #define MXC_F_GCR_PCLK_DIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART1_POS)) /**< PCLK_DIS0_UART1 Mask */ 542 #define MXC_V_GCR_PCLK_DIS0_UART1_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_UART1_EN Value */ 543 #define MXC_S_GCR_PCLK_DIS0_UART1_EN (MXC_V_GCR_PCLK_DIS0_UART1_EN << MXC_F_GCR_PCLK_DIS0_UART1_POS) /**< PCLK_DIS0_UART1_EN Setting */ 544 #define MXC_V_GCR_PCLK_DIS0_UART1_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_UART1_DIS Value */ 545 #define MXC_S_GCR_PCLK_DIS0_UART1_DIS (MXC_V_GCR_PCLK_DIS0_UART1_DIS << MXC_F_GCR_PCLK_DIS0_UART1_POS) /**< PCLK_DIS0_UART1_DIS Setting */ 546 547 #define MXC_F_GCR_PCLK_DIS0_I2C0_POS 13 /**< PCLK_DIS0_I2C0 Position */ 548 #define MXC_F_GCR_PCLK_DIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C0_POS)) /**< PCLK_DIS0_I2C0 Mask */ 549 #define MXC_V_GCR_PCLK_DIS0_I2C0_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_I2C0_EN Value */ 550 #define MXC_S_GCR_PCLK_DIS0_I2C0_EN (MXC_V_GCR_PCLK_DIS0_I2C0_EN << MXC_F_GCR_PCLK_DIS0_I2C0_POS) /**< PCLK_DIS0_I2C0_EN Setting */ 551 #define MXC_V_GCR_PCLK_DIS0_I2C0_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_I2C0_DIS Value */ 552 #define MXC_S_GCR_PCLK_DIS0_I2C0_DIS (MXC_V_GCR_PCLK_DIS0_I2C0_DIS << MXC_F_GCR_PCLK_DIS0_I2C0_POS) /**< PCLK_DIS0_I2C0_DIS Setting */ 553 554 #define MXC_F_GCR_PCLK_DIS0_TPU_POS 14 /**< PCLK_DIS0_TPU Position */ 555 #define MXC_F_GCR_PCLK_DIS0_TPU ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TPU_POS)) /**< PCLK_DIS0_TPU Mask */ 556 #define MXC_V_GCR_PCLK_DIS0_TPU_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_TPU_EN Value */ 557 #define MXC_S_GCR_PCLK_DIS0_TPU_EN (MXC_V_GCR_PCLK_DIS0_TPU_EN << MXC_F_GCR_PCLK_DIS0_TPU_POS) /**< PCLK_DIS0_TPU_EN Setting */ 558 #define MXC_V_GCR_PCLK_DIS0_TPU_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_TPU_DIS Value */ 559 #define MXC_S_GCR_PCLK_DIS0_TPU_DIS (MXC_V_GCR_PCLK_DIS0_TPU_DIS << MXC_F_GCR_PCLK_DIS0_TPU_POS) /**< PCLK_DIS0_TPU_DIS Setting */ 560 561 #define MXC_F_GCR_PCLK_DIS0_TIMER0_POS 15 /**< PCLK_DIS0_TIMER0 Position */ 562 #define MXC_F_GCR_PCLK_DIS0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER0_POS)) /**< PCLK_DIS0_TIMER0 Mask */ 563 #define MXC_V_GCR_PCLK_DIS0_TIMER0_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_TIMER0_EN Value */ 564 #define MXC_S_GCR_PCLK_DIS0_TIMER0_EN (MXC_V_GCR_PCLK_DIS0_TIMER0_EN << MXC_F_GCR_PCLK_DIS0_TIMER0_POS) /**< PCLK_DIS0_TIMER0_EN Setting */ 565 #define MXC_V_GCR_PCLK_DIS0_TIMER0_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_TIMER0_DIS Value */ 566 #define MXC_S_GCR_PCLK_DIS0_TIMER0_DIS (MXC_V_GCR_PCLK_DIS0_TIMER0_DIS << MXC_F_GCR_PCLK_DIS0_TIMER0_POS) /**< PCLK_DIS0_TIMER0_DIS Setting */ 567 568 #define MXC_F_GCR_PCLK_DIS0_TIMER1_POS 16 /**< PCLK_DIS0_TIMER1 Position */ 569 #define MXC_F_GCR_PCLK_DIS0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER1_POS)) /**< PCLK_DIS0_TIMER1 Mask */ 570 #define MXC_V_GCR_PCLK_DIS0_TIMER1_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_TIMER1_EN Value */ 571 #define MXC_S_GCR_PCLK_DIS0_TIMER1_EN (MXC_V_GCR_PCLK_DIS0_TIMER1_EN << MXC_F_GCR_PCLK_DIS0_TIMER1_POS) /**< PCLK_DIS0_TIMER1_EN Setting */ 572 #define MXC_V_GCR_PCLK_DIS0_TIMER1_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_TIMER1_DIS Value */ 573 #define MXC_S_GCR_PCLK_DIS0_TIMER1_DIS (MXC_V_GCR_PCLK_DIS0_TIMER1_DIS << MXC_F_GCR_PCLK_DIS0_TIMER1_POS) /**< PCLK_DIS0_TIMER1_DIS Setting */ 574 575 #define MXC_F_GCR_PCLK_DIS0_TIMER2_POS 17 /**< PCLK_DIS0_TIMER2 Position */ 576 #define MXC_F_GCR_PCLK_DIS0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER2_POS)) /**< PCLK_DIS0_TIMER2 Mask */ 577 #define MXC_V_GCR_PCLK_DIS0_TIMER2_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_TIMER2_EN Value */ 578 #define MXC_S_GCR_PCLK_DIS0_TIMER2_EN (MXC_V_GCR_PCLK_DIS0_TIMER2_EN << MXC_F_GCR_PCLK_DIS0_TIMER2_POS) /**< PCLK_DIS0_TIMER2_EN Setting */ 579 #define MXC_V_GCR_PCLK_DIS0_TIMER2_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_TIMER2_DIS Value */ 580 #define MXC_S_GCR_PCLK_DIS0_TIMER2_DIS (MXC_V_GCR_PCLK_DIS0_TIMER2_DIS << MXC_F_GCR_PCLK_DIS0_TIMER2_POS) /**< PCLK_DIS0_TIMER2_DIS Setting */ 581 582 #define MXC_F_GCR_PCLK_DIS0_TIMER3_POS 18 /**< PCLK_DIS0_TIMER3 Position */ 583 #define MXC_F_GCR_PCLK_DIS0_TIMER3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER3_POS)) /**< PCLK_DIS0_TIMER3 Mask */ 584 #define MXC_V_GCR_PCLK_DIS0_TIMER3_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_TIMER3_EN Value */ 585 #define MXC_S_GCR_PCLK_DIS0_TIMER3_EN (MXC_V_GCR_PCLK_DIS0_TIMER3_EN << MXC_F_GCR_PCLK_DIS0_TIMER3_POS) /**< PCLK_DIS0_TIMER3_EN Setting */ 586 #define MXC_V_GCR_PCLK_DIS0_TIMER3_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_TIMER3_DIS Value */ 587 #define MXC_S_GCR_PCLK_DIS0_TIMER3_DIS (MXC_V_GCR_PCLK_DIS0_TIMER3_DIS << MXC_F_GCR_PCLK_DIS0_TIMER3_POS) /**< PCLK_DIS0_TIMER3_DIS Setting */ 588 589 #define MXC_F_GCR_PCLK_DIS0_TIMER4_POS 19 /**< PCLK_DIS0_TIMER4 Position */ 590 #define MXC_F_GCR_PCLK_DIS0_TIMER4 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER4_POS)) /**< PCLK_DIS0_TIMER4 Mask */ 591 #define MXC_V_GCR_PCLK_DIS0_TIMER4_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_TIMER4_EN Value */ 592 #define MXC_S_GCR_PCLK_DIS0_TIMER4_EN (MXC_V_GCR_PCLK_DIS0_TIMER4_EN << MXC_F_GCR_PCLK_DIS0_TIMER4_POS) /**< PCLK_DIS0_TIMER4_EN Setting */ 593 #define MXC_V_GCR_PCLK_DIS0_TIMER4_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_TIMER4_DIS Value */ 594 #define MXC_S_GCR_PCLK_DIS0_TIMER4_DIS (MXC_V_GCR_PCLK_DIS0_TIMER4_DIS << MXC_F_GCR_PCLK_DIS0_TIMER4_POS) /**< PCLK_DIS0_TIMER4_DIS Setting */ 595 596 #define MXC_F_GCR_PCLK_DIS0_TIMER5_POS 20 /**< PCLK_DIS0_TIMER5 Position */ 597 #define MXC_F_GCR_PCLK_DIS0_TIMER5 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER5_POS)) /**< PCLK_DIS0_TIMER5 Mask */ 598 #define MXC_V_GCR_PCLK_DIS0_TIMER5_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_TIMER5_EN Value */ 599 #define MXC_S_GCR_PCLK_DIS0_TIMER5_EN (MXC_V_GCR_PCLK_DIS0_TIMER5_EN << MXC_F_GCR_PCLK_DIS0_TIMER5_POS) /**< PCLK_DIS0_TIMER5_EN Setting */ 600 #define MXC_V_GCR_PCLK_DIS0_TIMER5_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_TIMER5_DIS Value */ 601 #define MXC_S_GCR_PCLK_DIS0_TIMER5_DIS (MXC_V_GCR_PCLK_DIS0_TIMER5_DIS << MXC_F_GCR_PCLK_DIS0_TIMER5_POS) /**< PCLK_DIS0_TIMER5_DIS Setting */ 602 603 #define MXC_F_GCR_PCLK_DIS0_ADC_POS 23 /**< PCLK_DIS0_ADC Position */ 604 #define MXC_F_GCR_PCLK_DIS0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_ADC_POS)) /**< PCLK_DIS0_ADC Mask */ 605 #define MXC_V_GCR_PCLK_DIS0_ADC_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_ADC_EN Value */ 606 #define MXC_S_GCR_PCLK_DIS0_ADC_EN (MXC_V_GCR_PCLK_DIS0_ADC_EN << MXC_F_GCR_PCLK_DIS0_ADC_POS) /**< PCLK_DIS0_ADC_EN Setting */ 607 #define MXC_V_GCR_PCLK_DIS0_ADC_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_ADC_DIS Value */ 608 #define MXC_S_GCR_PCLK_DIS0_ADC_DIS (MXC_V_GCR_PCLK_DIS0_ADC_DIS << MXC_F_GCR_PCLK_DIS0_ADC_POS) /**< PCLK_DIS0_ADC_DIS Setting */ 609 610 #define MXC_F_GCR_PCLK_DIS0_I2C1_POS 28 /**< PCLK_DIS0_I2C1 Position */ 611 #define MXC_F_GCR_PCLK_DIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C1_POS)) /**< PCLK_DIS0_I2C1 Mask */ 612 #define MXC_V_GCR_PCLK_DIS0_I2C1_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_I2C1_EN Value */ 613 #define MXC_S_GCR_PCLK_DIS0_I2C1_EN (MXC_V_GCR_PCLK_DIS0_I2C1_EN << MXC_F_GCR_PCLK_DIS0_I2C1_POS) /**< PCLK_DIS0_I2C1_EN Setting */ 614 #define MXC_V_GCR_PCLK_DIS0_I2C1_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_I2C1_DIS Value */ 615 #define MXC_S_GCR_PCLK_DIS0_I2C1_DIS (MXC_V_GCR_PCLK_DIS0_I2C1_DIS << MXC_F_GCR_PCLK_DIS0_I2C1_POS) /**< PCLK_DIS0_I2C1_DIS Setting */ 616 617 #define MXC_F_GCR_PCLK_DIS0_PT_POS 29 /**< PCLK_DIS0_PT Position */ 618 #define MXC_F_GCR_PCLK_DIS0_PT ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_PT_POS)) /**< PCLK_DIS0_PT Mask */ 619 #define MXC_V_GCR_PCLK_DIS0_PT_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_PT_EN Value */ 620 #define MXC_S_GCR_PCLK_DIS0_PT_EN (MXC_V_GCR_PCLK_DIS0_PT_EN << MXC_F_GCR_PCLK_DIS0_PT_POS) /**< PCLK_DIS0_PT_EN Setting */ 621 #define MXC_V_GCR_PCLK_DIS0_PT_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_PT_DIS Value */ 622 #define MXC_S_GCR_PCLK_DIS0_PT_DIS (MXC_V_GCR_PCLK_DIS0_PT_DIS << MXC_F_GCR_PCLK_DIS0_PT_POS) /**< PCLK_DIS0_PT_DIS Setting */ 623 624 #define MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS 30 /**< PCLK_DIS0_SPIXIPF Position */ 625 #define MXC_F_GCR_PCLK_DIS0_SPIXIPF ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS)) /**< PCLK_DIS0_SPIXIPF Mask */ 626 #define MXC_V_GCR_PCLK_DIS0_SPIXIPF_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_SPIXIPF_EN Value */ 627 #define MXC_S_GCR_PCLK_DIS0_SPIXIPF_EN (MXC_V_GCR_PCLK_DIS0_SPIXIPF_EN << MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS) /**< PCLK_DIS0_SPIXIPF_EN Setting */ 628 #define MXC_V_GCR_PCLK_DIS0_SPIXIPF_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_SPIXIPF_DIS Value */ 629 #define MXC_S_GCR_PCLK_DIS0_SPIXIPF_DIS (MXC_V_GCR_PCLK_DIS0_SPIXIPF_DIS << MXC_F_GCR_PCLK_DIS0_SPIXIPF_POS) /**< PCLK_DIS0_SPIXIPF_DIS Setting */ 630 631 #define MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS 31 /**< PCLK_DIS0_SPIXIPM Position */ 632 #define MXC_F_GCR_PCLK_DIS0_SPIXIPM ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS)) /**< PCLK_DIS0_SPIXIPM Mask */ 633 #define MXC_V_GCR_PCLK_DIS0_SPIXIPM_EN ((uint32_t)0x0UL) /**< PCLK_DIS0_SPIXIPM_EN Value */ 634 #define MXC_S_GCR_PCLK_DIS0_SPIXIPM_EN (MXC_V_GCR_PCLK_DIS0_SPIXIPM_EN << MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS) /**< PCLK_DIS0_SPIXIPM_EN Setting */ 635 #define MXC_V_GCR_PCLK_DIS0_SPIXIPM_DIS ((uint32_t)0x1UL) /**< PCLK_DIS0_SPIXIPM_DIS Value */ 636 #define MXC_S_GCR_PCLK_DIS0_SPIXIPM_DIS (MXC_V_GCR_PCLK_DIS0_SPIXIPM_DIS << MXC_F_GCR_PCLK_DIS0_SPIXIPM_POS) /**< PCLK_DIS0_SPIXIPM_DIS Setting */ 637 638 /**@} end of group GCR_PCLK_DIS0_Register */ 639 640 /** 641 * @ingroup gcr_registers 642 * @defgroup GCR_MEM_CLK GCR_MEM_CLK 643 * @brief Memory Clock Control Register. 644 * @{ 645 */ 646 #define MXC_F_GCR_MEM_CLK_FWS_POS 0 /**< MEM_CLK_FWS Position */ 647 #define MXC_F_GCR_MEM_CLK_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEM_CLK_FWS_POS)) /**< MEM_CLK_FWS Mask */ 648 649 #define MXC_F_GCR_MEM_CLK_SYSRAM0LS_POS 16 /**< MEM_CLK_SYSRAM0LS Position */ 650 #define MXC_F_GCR_MEM_CLK_SYSRAM0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM0LS_POS)) /**< MEM_CLK_SYSRAM0LS Mask */ 651 #define MXC_V_GCR_MEM_CLK_SYSRAM0LS_ACTIVE ((uint32_t)0x0UL) /**< MEM_CLK_SYSRAM0LS_ACTIVE Value */ 652 #define MXC_S_GCR_MEM_CLK_SYSRAM0LS_ACTIVE (MXC_V_GCR_MEM_CLK_SYSRAM0LS_ACTIVE << MXC_F_GCR_MEM_CLK_SYSRAM0LS_POS) /**< MEM_CLK_SYSRAM0LS_ACTIVE Setting */ 653 #define MXC_V_GCR_MEM_CLK_SYSRAM0LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEM_CLK_SYSRAM0LS_LIGHT_SLEEP Value */ 654 #define MXC_S_GCR_MEM_CLK_SYSRAM0LS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SYSRAM0LS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SYSRAM0LS_POS) /**< MEM_CLK_SYSRAM0LS_LIGHT_SLEEP Setting */ 655 656 #define MXC_F_GCR_MEM_CLK_SYSRAM1LS_POS 17 /**< MEM_CLK_SYSRAM1LS Position */ 657 #define MXC_F_GCR_MEM_CLK_SYSRAM1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM1LS_POS)) /**< MEM_CLK_SYSRAM1LS Mask */ 658 #define MXC_V_GCR_MEM_CLK_SYSRAM1LS_ACTIVE ((uint32_t)0x0UL) /**< MEM_CLK_SYSRAM1LS_ACTIVE Value */ 659 #define MXC_S_GCR_MEM_CLK_SYSRAM1LS_ACTIVE (MXC_V_GCR_MEM_CLK_SYSRAM1LS_ACTIVE << MXC_F_GCR_MEM_CLK_SYSRAM1LS_POS) /**< MEM_CLK_SYSRAM1LS_ACTIVE Setting */ 660 #define MXC_V_GCR_MEM_CLK_SYSRAM1LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEM_CLK_SYSRAM1LS_LIGHT_SLEEP Value */ 661 #define MXC_S_GCR_MEM_CLK_SYSRAM1LS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SYSRAM1LS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SYSRAM1LS_POS) /**< MEM_CLK_SYSRAM1LS_LIGHT_SLEEP Setting */ 662 663 #define MXC_F_GCR_MEM_CLK_SYSRAM2LS_POS 18 /**< MEM_CLK_SYSRAM2LS Position */ 664 #define MXC_F_GCR_MEM_CLK_SYSRAM2LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM2LS_POS)) /**< MEM_CLK_SYSRAM2LS Mask */ 665 #define MXC_V_GCR_MEM_CLK_SYSRAM2LS_ACTIVE ((uint32_t)0x0UL) /**< MEM_CLK_SYSRAM2LS_ACTIVE Value */ 666 #define MXC_S_GCR_MEM_CLK_SYSRAM2LS_ACTIVE (MXC_V_GCR_MEM_CLK_SYSRAM2LS_ACTIVE << MXC_F_GCR_MEM_CLK_SYSRAM2LS_POS) /**< MEM_CLK_SYSRAM2LS_ACTIVE Setting */ 667 #define MXC_V_GCR_MEM_CLK_SYSRAM2LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEM_CLK_SYSRAM2LS_LIGHT_SLEEP Value */ 668 #define MXC_S_GCR_MEM_CLK_SYSRAM2LS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SYSRAM2LS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SYSRAM2LS_POS) /**< MEM_CLK_SYSRAM2LS_LIGHT_SLEEP Setting */ 669 670 #define MXC_F_GCR_MEM_CLK_SYSRAM3LS_POS 19 /**< MEM_CLK_SYSRAM3LS Position */ 671 #define MXC_F_GCR_MEM_CLK_SYSRAM3LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM3LS_POS)) /**< MEM_CLK_SYSRAM3LS Mask */ 672 #define MXC_V_GCR_MEM_CLK_SYSRAM3LS_ACTIVE ((uint32_t)0x0UL) /**< MEM_CLK_SYSRAM3LS_ACTIVE Value */ 673 #define MXC_S_GCR_MEM_CLK_SYSRAM3LS_ACTIVE (MXC_V_GCR_MEM_CLK_SYSRAM3LS_ACTIVE << MXC_F_GCR_MEM_CLK_SYSRAM3LS_POS) /**< MEM_CLK_SYSRAM3LS_ACTIVE Setting */ 674 #define MXC_V_GCR_MEM_CLK_SYSRAM3LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEM_CLK_SYSRAM3LS_LIGHT_SLEEP Value */ 675 #define MXC_S_GCR_MEM_CLK_SYSRAM3LS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SYSRAM3LS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SYSRAM3LS_POS) /**< MEM_CLK_SYSRAM3LS_LIGHT_SLEEP Setting */ 676 677 #define MXC_F_GCR_MEM_CLK_SYSRAM4LS_POS 20 /**< MEM_CLK_SYSRAM4LS Position */ 678 #define MXC_F_GCR_MEM_CLK_SYSRAM4LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM4LS_POS)) /**< MEM_CLK_SYSRAM4LS Mask */ 679 #define MXC_V_GCR_MEM_CLK_SYSRAM4LS_ACTIVE ((uint32_t)0x0UL) /**< MEM_CLK_SYSRAM4LS_ACTIVE Value */ 680 #define MXC_S_GCR_MEM_CLK_SYSRAM4LS_ACTIVE (MXC_V_GCR_MEM_CLK_SYSRAM4LS_ACTIVE << MXC_F_GCR_MEM_CLK_SYSRAM4LS_POS) /**< MEM_CLK_SYSRAM4LS_ACTIVE Setting */ 681 #define MXC_V_GCR_MEM_CLK_SYSRAM4LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEM_CLK_SYSRAM4LS_LIGHT_SLEEP Value */ 682 #define MXC_S_GCR_MEM_CLK_SYSRAM4LS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SYSRAM4LS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SYSRAM4LS_POS) /**< MEM_CLK_SYSRAM4LS_LIGHT_SLEEP Setting */ 683 684 #define MXC_F_GCR_MEM_CLK_SYSRAM5LS_POS 21 /**< MEM_CLK_SYSRAM5LS Position */ 685 #define MXC_F_GCR_MEM_CLK_SYSRAM5LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM5LS_POS)) /**< MEM_CLK_SYSRAM5LS Mask */ 686 #define MXC_V_GCR_MEM_CLK_SYSRAM5LS_ACTIVE ((uint32_t)0x0UL) /**< MEM_CLK_SYSRAM5LS_ACTIVE Value */ 687 #define MXC_S_GCR_MEM_CLK_SYSRAM5LS_ACTIVE (MXC_V_GCR_MEM_CLK_SYSRAM5LS_ACTIVE << MXC_F_GCR_MEM_CLK_SYSRAM5LS_POS) /**< MEM_CLK_SYSRAM5LS_ACTIVE Setting */ 688 #define MXC_V_GCR_MEM_CLK_SYSRAM5LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEM_CLK_SYSRAM5LS_LIGHT_SLEEP Value */ 689 #define MXC_S_GCR_MEM_CLK_SYSRAM5LS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SYSRAM5LS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SYSRAM5LS_POS) /**< MEM_CLK_SYSRAM5LS_LIGHT_SLEEP Setting */ 690 691 #define MXC_F_GCR_MEM_CLK_SYSRAM6LS_POS 22 /**< MEM_CLK_SYSRAM6LS Position */ 692 #define MXC_F_GCR_MEM_CLK_SYSRAM6LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SYSRAM6LS_POS)) /**< MEM_CLK_SYSRAM6LS Mask */ 693 #define MXC_V_GCR_MEM_CLK_SYSRAM6LS_ACTIVE ((uint32_t)0x0UL) /**< MEM_CLK_SYSRAM6LS_ACTIVE Value */ 694 #define MXC_S_GCR_MEM_CLK_SYSRAM6LS_ACTIVE (MXC_V_GCR_MEM_CLK_SYSRAM6LS_ACTIVE << MXC_F_GCR_MEM_CLK_SYSRAM6LS_POS) /**< MEM_CLK_SYSRAM6LS_ACTIVE Setting */ 695 #define MXC_V_GCR_MEM_CLK_SYSRAM6LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEM_CLK_SYSRAM6LS_LIGHT_SLEEP Value */ 696 #define MXC_S_GCR_MEM_CLK_SYSRAM6LS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SYSRAM6LS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SYSRAM6LS_POS) /**< MEM_CLK_SYSRAM6LS_LIGHT_SLEEP Setting */ 697 698 #define MXC_F_GCR_MEM_CLK_ICACHELS_POS 24 /**< MEM_CLK_ICACHELS Position */ 699 #define MXC_F_GCR_MEM_CLK_ICACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ICACHELS_POS)) /**< MEM_CLK_ICACHELS Mask */ 700 #define MXC_V_GCR_MEM_CLK_ICACHELS_ACTIVE ((uint32_t)0x0UL) /**< MEM_CLK_ICACHELS_ACTIVE Value */ 701 #define MXC_S_GCR_MEM_CLK_ICACHELS_ACTIVE (MXC_V_GCR_MEM_CLK_ICACHELS_ACTIVE << MXC_F_GCR_MEM_CLK_ICACHELS_POS) /**< MEM_CLK_ICACHELS_ACTIVE Setting */ 702 #define MXC_V_GCR_MEM_CLK_ICACHELS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEM_CLK_ICACHELS_LIGHT_SLEEP Value */ 703 #define MXC_S_GCR_MEM_CLK_ICACHELS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_ICACHELS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_ICACHELS_POS) /**< MEM_CLK_ICACHELS_LIGHT_SLEEP Setting */ 704 705 #define MXC_F_GCR_MEM_CLK_ICACHEXIPLS_POS 25 /**< MEM_CLK_ICACHEXIPLS Position */ 706 #define MXC_F_GCR_MEM_CLK_ICACHEXIPLS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ICACHEXIPLS_POS)) /**< MEM_CLK_ICACHEXIPLS Mask */ 707 #define MXC_V_GCR_MEM_CLK_ICACHEXIPLS_ACTIVE ((uint32_t)0x0UL) /**< MEM_CLK_ICACHEXIPLS_ACTIVE Value */ 708 #define MXC_S_GCR_MEM_CLK_ICACHEXIPLS_ACTIVE (MXC_V_GCR_MEM_CLK_ICACHEXIPLS_ACTIVE << MXC_F_GCR_MEM_CLK_ICACHEXIPLS_POS) /**< MEM_CLK_ICACHEXIPLS_ACTIVE Setting */ 709 #define MXC_V_GCR_MEM_CLK_ICACHEXIPLS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEM_CLK_ICACHEXIPLS_LIGHT_SLEEP Value */ 710 #define MXC_S_GCR_MEM_CLK_ICACHEXIPLS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_ICACHEXIPLS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_ICACHEXIPLS_POS) /**< MEM_CLK_ICACHEXIPLS_LIGHT_SLEEP Setting */ 711 712 #define MXC_F_GCR_MEM_CLK_SCACHELS_POS 26 /**< MEM_CLK_SCACHELS Position */ 713 #define MXC_F_GCR_MEM_CLK_SCACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_SCACHELS_POS)) /**< MEM_CLK_SCACHELS Mask */ 714 #define MXC_V_GCR_MEM_CLK_SCACHELS_ACTIVE ((uint32_t)0x0UL) /**< MEM_CLK_SCACHELS_ACTIVE Value */ 715 #define MXC_S_GCR_MEM_CLK_SCACHELS_ACTIVE (MXC_V_GCR_MEM_CLK_SCACHELS_ACTIVE << MXC_F_GCR_MEM_CLK_SCACHELS_POS) /**< MEM_CLK_SCACHELS_ACTIVE Setting */ 716 #define MXC_V_GCR_MEM_CLK_SCACHELS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEM_CLK_SCACHELS_LIGHT_SLEEP Value */ 717 #define MXC_S_GCR_MEM_CLK_SCACHELS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_SCACHELS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_SCACHELS_POS) /**< MEM_CLK_SCACHELS_LIGHT_SLEEP Setting */ 718 719 #define MXC_F_GCR_MEM_CLK_CRYPTOLS_POS 27 /**< MEM_CLK_CRYPTOLS Position */ 720 #define MXC_F_GCR_MEM_CLK_CRYPTOLS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_CRYPTOLS_POS)) /**< MEM_CLK_CRYPTOLS Mask */ 721 #define MXC_V_GCR_MEM_CLK_CRYPTOLS_ACTIVE ((uint32_t)0x0UL) /**< MEM_CLK_CRYPTOLS_ACTIVE Value */ 722 #define MXC_S_GCR_MEM_CLK_CRYPTOLS_ACTIVE (MXC_V_GCR_MEM_CLK_CRYPTOLS_ACTIVE << MXC_F_GCR_MEM_CLK_CRYPTOLS_POS) /**< MEM_CLK_CRYPTOLS_ACTIVE Setting */ 723 #define MXC_V_GCR_MEM_CLK_CRYPTOLS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEM_CLK_CRYPTOLS_LIGHT_SLEEP Value */ 724 #define MXC_S_GCR_MEM_CLK_CRYPTOLS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_CRYPTOLS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_CRYPTOLS_POS) /**< MEM_CLK_CRYPTOLS_LIGHT_SLEEP Setting */ 725 726 #define MXC_F_GCR_MEM_CLK_USBLS_POS 28 /**< MEM_CLK_USBLS Position */ 727 #define MXC_F_GCR_MEM_CLK_USBLS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_USBLS_POS)) /**< MEM_CLK_USBLS Mask */ 728 #define MXC_V_GCR_MEM_CLK_USBLS_ACTIVE ((uint32_t)0x0UL) /**< MEM_CLK_USBLS_ACTIVE Value */ 729 #define MXC_S_GCR_MEM_CLK_USBLS_ACTIVE (MXC_V_GCR_MEM_CLK_USBLS_ACTIVE << MXC_F_GCR_MEM_CLK_USBLS_POS) /**< MEM_CLK_USBLS_ACTIVE Setting */ 730 #define MXC_V_GCR_MEM_CLK_USBLS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEM_CLK_USBLS_LIGHT_SLEEP Value */ 731 #define MXC_S_GCR_MEM_CLK_USBLS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_USBLS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_USBLS_POS) /**< MEM_CLK_USBLS_LIGHT_SLEEP Setting */ 732 733 #define MXC_F_GCR_MEM_CLK_ROMLS_POS 29 /**< MEM_CLK_ROMLS Position */ 734 #define MXC_F_GCR_MEM_CLK_ROMLS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CLK_ROMLS_POS)) /**< MEM_CLK_ROMLS Mask */ 735 #define MXC_V_GCR_MEM_CLK_ROMLS_ACTIVE ((uint32_t)0x0UL) /**< MEM_CLK_ROMLS_ACTIVE Value */ 736 #define MXC_S_GCR_MEM_CLK_ROMLS_ACTIVE (MXC_V_GCR_MEM_CLK_ROMLS_ACTIVE << MXC_F_GCR_MEM_CLK_ROMLS_POS) /**< MEM_CLK_ROMLS_ACTIVE Setting */ 737 #define MXC_V_GCR_MEM_CLK_ROMLS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEM_CLK_ROMLS_LIGHT_SLEEP Value */ 738 #define MXC_S_GCR_MEM_CLK_ROMLS_LIGHT_SLEEP (MXC_V_GCR_MEM_CLK_ROMLS_LIGHT_SLEEP << MXC_F_GCR_MEM_CLK_ROMLS_POS) /**< MEM_CLK_ROMLS_LIGHT_SLEEP Setting */ 739 740 /**@} end of group GCR_MEM_CLK_Register */ 741 742 /** 743 * @ingroup gcr_registers 744 * @defgroup GCR_MEM_ZERO GCR_MEM_ZERO 745 * @brief Memory Zeroize Control. 746 * @{ 747 */ 748 #define MXC_F_GCR_MEM_ZERO_SRAM0Z_POS 0 /**< MEM_ZERO_SRAM0Z Position */ 749 #define MXC_F_GCR_MEM_ZERO_SRAM0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM0Z_POS)) /**< MEM_ZERO_SRAM0Z Mask */ 750 #define MXC_V_GCR_MEM_ZERO_SRAM0Z_NOP ((uint32_t)0x0UL) /**< MEM_ZERO_SRAM0Z_NOP Value */ 751 #define MXC_S_GCR_MEM_ZERO_SRAM0Z_NOP (MXC_V_GCR_MEM_ZERO_SRAM0Z_NOP << MXC_F_GCR_MEM_ZERO_SRAM0Z_POS) /**< MEM_ZERO_SRAM0Z_NOP Setting */ 752 #define MXC_V_GCR_MEM_ZERO_SRAM0Z_START ((uint32_t)0x1UL) /**< MEM_ZERO_SRAM0Z_START Value */ 753 #define MXC_S_GCR_MEM_ZERO_SRAM0Z_START (MXC_V_GCR_MEM_ZERO_SRAM0Z_START << MXC_F_GCR_MEM_ZERO_SRAM0Z_POS) /**< MEM_ZERO_SRAM0Z_START Setting */ 754 755 #define MXC_F_GCR_MEM_ZERO_SRAM1Z_POS 1 /**< MEM_ZERO_SRAM1Z Position */ 756 #define MXC_F_GCR_MEM_ZERO_SRAM1Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM1Z_POS)) /**< MEM_ZERO_SRAM1Z Mask */ 757 #define MXC_V_GCR_MEM_ZERO_SRAM1Z_NOP ((uint32_t)0x0UL) /**< MEM_ZERO_SRAM1Z_NOP Value */ 758 #define MXC_S_GCR_MEM_ZERO_SRAM1Z_NOP (MXC_V_GCR_MEM_ZERO_SRAM1Z_NOP << MXC_F_GCR_MEM_ZERO_SRAM1Z_POS) /**< MEM_ZERO_SRAM1Z_NOP Setting */ 759 #define MXC_V_GCR_MEM_ZERO_SRAM1Z_START ((uint32_t)0x1UL) /**< MEM_ZERO_SRAM1Z_START Value */ 760 #define MXC_S_GCR_MEM_ZERO_SRAM1Z_START (MXC_V_GCR_MEM_ZERO_SRAM1Z_START << MXC_F_GCR_MEM_ZERO_SRAM1Z_POS) /**< MEM_ZERO_SRAM1Z_START Setting */ 761 762 #define MXC_F_GCR_MEM_ZERO_SRAM2Z_POS 2 /**< MEM_ZERO_SRAM2Z Position */ 763 #define MXC_F_GCR_MEM_ZERO_SRAM2Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM2Z_POS)) /**< MEM_ZERO_SRAM2Z Mask */ 764 #define MXC_V_GCR_MEM_ZERO_SRAM2Z_NOP ((uint32_t)0x0UL) /**< MEM_ZERO_SRAM2Z_NOP Value */ 765 #define MXC_S_GCR_MEM_ZERO_SRAM2Z_NOP (MXC_V_GCR_MEM_ZERO_SRAM2Z_NOP << MXC_F_GCR_MEM_ZERO_SRAM2Z_POS) /**< MEM_ZERO_SRAM2Z_NOP Setting */ 766 #define MXC_V_GCR_MEM_ZERO_SRAM2Z_START ((uint32_t)0x1UL) /**< MEM_ZERO_SRAM2Z_START Value */ 767 #define MXC_S_GCR_MEM_ZERO_SRAM2Z_START (MXC_V_GCR_MEM_ZERO_SRAM2Z_START << MXC_F_GCR_MEM_ZERO_SRAM2Z_POS) /**< MEM_ZERO_SRAM2Z_START Setting */ 768 769 #define MXC_F_GCR_MEM_ZERO_SRAM3Z_POS 3 /**< MEM_ZERO_SRAM3Z Position */ 770 #define MXC_F_GCR_MEM_ZERO_SRAM3Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM3Z_POS)) /**< MEM_ZERO_SRAM3Z Mask */ 771 #define MXC_V_GCR_MEM_ZERO_SRAM3Z_NOP ((uint32_t)0x0UL) /**< MEM_ZERO_SRAM3Z_NOP Value */ 772 #define MXC_S_GCR_MEM_ZERO_SRAM3Z_NOP (MXC_V_GCR_MEM_ZERO_SRAM3Z_NOP << MXC_F_GCR_MEM_ZERO_SRAM3Z_POS) /**< MEM_ZERO_SRAM3Z_NOP Setting */ 773 #define MXC_V_GCR_MEM_ZERO_SRAM3Z_START ((uint32_t)0x1UL) /**< MEM_ZERO_SRAM3Z_START Value */ 774 #define MXC_S_GCR_MEM_ZERO_SRAM3Z_START (MXC_V_GCR_MEM_ZERO_SRAM3Z_START << MXC_F_GCR_MEM_ZERO_SRAM3Z_POS) /**< MEM_ZERO_SRAM3Z_START Setting */ 775 776 #define MXC_F_GCR_MEM_ZERO_SRAM4Z_POS 4 /**< MEM_ZERO_SRAM4Z Position */ 777 #define MXC_F_GCR_MEM_ZERO_SRAM4Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM4Z_POS)) /**< MEM_ZERO_SRAM4Z Mask */ 778 #define MXC_V_GCR_MEM_ZERO_SRAM4Z_NOP ((uint32_t)0x0UL) /**< MEM_ZERO_SRAM4Z_NOP Value */ 779 #define MXC_S_GCR_MEM_ZERO_SRAM4Z_NOP (MXC_V_GCR_MEM_ZERO_SRAM4Z_NOP << MXC_F_GCR_MEM_ZERO_SRAM4Z_POS) /**< MEM_ZERO_SRAM4Z_NOP Setting */ 780 #define MXC_V_GCR_MEM_ZERO_SRAM4Z_START ((uint32_t)0x1UL) /**< MEM_ZERO_SRAM4Z_START Value */ 781 #define MXC_S_GCR_MEM_ZERO_SRAM4Z_START (MXC_V_GCR_MEM_ZERO_SRAM4Z_START << MXC_F_GCR_MEM_ZERO_SRAM4Z_POS) /**< MEM_ZERO_SRAM4Z_START Setting */ 782 783 #define MXC_F_GCR_MEM_ZERO_SRAM5Z_POS 5 /**< MEM_ZERO_SRAM5Z Position */ 784 #define MXC_F_GCR_MEM_ZERO_SRAM5Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM5Z_POS)) /**< MEM_ZERO_SRAM5Z Mask */ 785 #define MXC_V_GCR_MEM_ZERO_SRAM5Z_NOP ((uint32_t)0x0UL) /**< MEM_ZERO_SRAM5Z_NOP Value */ 786 #define MXC_S_GCR_MEM_ZERO_SRAM5Z_NOP (MXC_V_GCR_MEM_ZERO_SRAM5Z_NOP << MXC_F_GCR_MEM_ZERO_SRAM5Z_POS) /**< MEM_ZERO_SRAM5Z_NOP Setting */ 787 #define MXC_V_GCR_MEM_ZERO_SRAM5Z_START ((uint32_t)0x1UL) /**< MEM_ZERO_SRAM5Z_START Value */ 788 #define MXC_S_GCR_MEM_ZERO_SRAM5Z_START (MXC_V_GCR_MEM_ZERO_SRAM5Z_START << MXC_F_GCR_MEM_ZERO_SRAM5Z_POS) /**< MEM_ZERO_SRAM5Z_START Setting */ 789 790 #define MXC_F_GCR_MEM_ZERO_SRAM6Z_POS 6 /**< MEM_ZERO_SRAM6Z Position */ 791 #define MXC_F_GCR_MEM_ZERO_SRAM6Z ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SRAM6Z_POS)) /**< MEM_ZERO_SRAM6Z Mask */ 792 #define MXC_V_GCR_MEM_ZERO_SRAM6Z_NOP ((uint32_t)0x0UL) /**< MEM_ZERO_SRAM6Z_NOP Value */ 793 #define MXC_S_GCR_MEM_ZERO_SRAM6Z_NOP (MXC_V_GCR_MEM_ZERO_SRAM6Z_NOP << MXC_F_GCR_MEM_ZERO_SRAM6Z_POS) /**< MEM_ZERO_SRAM6Z_NOP Setting */ 794 #define MXC_V_GCR_MEM_ZERO_SRAM6Z_START ((uint32_t)0x1UL) /**< MEM_ZERO_SRAM6Z_START Value */ 795 #define MXC_S_GCR_MEM_ZERO_SRAM6Z_START (MXC_V_GCR_MEM_ZERO_SRAM6Z_START << MXC_F_GCR_MEM_ZERO_SRAM6Z_POS) /**< MEM_ZERO_SRAM6Z_START Setting */ 796 797 #define MXC_F_GCR_MEM_ZERO_ICACHEZ_POS 8 /**< MEM_ZERO_ICACHEZ Position */ 798 #define MXC_F_GCR_MEM_ZERO_ICACHEZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_ICACHEZ_POS)) /**< MEM_ZERO_ICACHEZ Mask */ 799 #define MXC_V_GCR_MEM_ZERO_ICACHEZ_NOP ((uint32_t)0x0UL) /**< MEM_ZERO_ICACHEZ_NOP Value */ 800 #define MXC_S_GCR_MEM_ZERO_ICACHEZ_NOP (MXC_V_GCR_MEM_ZERO_ICACHEZ_NOP << MXC_F_GCR_MEM_ZERO_ICACHEZ_POS) /**< MEM_ZERO_ICACHEZ_NOP Setting */ 801 #define MXC_V_GCR_MEM_ZERO_ICACHEZ_START ((uint32_t)0x1UL) /**< MEM_ZERO_ICACHEZ_START Value */ 802 #define MXC_S_GCR_MEM_ZERO_ICACHEZ_START (MXC_V_GCR_MEM_ZERO_ICACHEZ_START << MXC_F_GCR_MEM_ZERO_ICACHEZ_POS) /**< MEM_ZERO_ICACHEZ_START Setting */ 803 804 #define MXC_F_GCR_MEM_ZERO_ICACHEXIPZ_POS 9 /**< MEM_ZERO_ICACHEXIPZ Position */ 805 #define MXC_F_GCR_MEM_ZERO_ICACHEXIPZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_ICACHEXIPZ_POS)) /**< MEM_ZERO_ICACHEXIPZ Mask */ 806 #define MXC_V_GCR_MEM_ZERO_ICACHEXIPZ_NOP ((uint32_t)0x0UL) /**< MEM_ZERO_ICACHEXIPZ_NOP Value */ 807 #define MXC_S_GCR_MEM_ZERO_ICACHEXIPZ_NOP (MXC_V_GCR_MEM_ZERO_ICACHEXIPZ_NOP << MXC_F_GCR_MEM_ZERO_ICACHEXIPZ_POS) /**< MEM_ZERO_ICACHEXIPZ_NOP Setting */ 808 #define MXC_V_GCR_MEM_ZERO_ICACHEXIPZ_START ((uint32_t)0x1UL) /**< MEM_ZERO_ICACHEXIPZ_START Value */ 809 #define MXC_S_GCR_MEM_ZERO_ICACHEXIPZ_START (MXC_V_GCR_MEM_ZERO_ICACHEXIPZ_START << MXC_F_GCR_MEM_ZERO_ICACHEXIPZ_POS) /**< MEM_ZERO_ICACHEXIPZ_START Setting */ 810 811 #define MXC_F_GCR_MEM_ZERO_SCACHEDATAZ_POS 10 /**< MEM_ZERO_SCACHEDATAZ Position */ 812 #define MXC_F_GCR_MEM_ZERO_SCACHEDATAZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SCACHEDATAZ_POS)) /**< MEM_ZERO_SCACHEDATAZ Mask */ 813 #define MXC_V_GCR_MEM_ZERO_SCACHEDATAZ_NOP ((uint32_t)0x0UL) /**< MEM_ZERO_SCACHEDATAZ_NOP Value */ 814 #define MXC_S_GCR_MEM_ZERO_SCACHEDATAZ_NOP (MXC_V_GCR_MEM_ZERO_SCACHEDATAZ_NOP << MXC_F_GCR_MEM_ZERO_SCACHEDATAZ_POS) /**< MEM_ZERO_SCACHEDATAZ_NOP Setting */ 815 #define MXC_V_GCR_MEM_ZERO_SCACHEDATAZ_START ((uint32_t)0x1UL) /**< MEM_ZERO_SCACHEDATAZ_START Value */ 816 #define MXC_S_GCR_MEM_ZERO_SCACHEDATAZ_START (MXC_V_GCR_MEM_ZERO_SCACHEDATAZ_START << MXC_F_GCR_MEM_ZERO_SCACHEDATAZ_POS) /**< MEM_ZERO_SCACHEDATAZ_START Setting */ 817 818 #define MXC_F_GCR_MEM_ZERO_SCACHETAGZ_POS 11 /**< MEM_ZERO_SCACHETAGZ Position */ 819 #define MXC_F_GCR_MEM_ZERO_SCACHETAGZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_SCACHETAGZ_POS)) /**< MEM_ZERO_SCACHETAGZ Mask */ 820 #define MXC_V_GCR_MEM_ZERO_SCACHETAGZ_NOP ((uint32_t)0x0UL) /**< MEM_ZERO_SCACHETAGZ_NOP Value */ 821 #define MXC_S_GCR_MEM_ZERO_SCACHETAGZ_NOP (MXC_V_GCR_MEM_ZERO_SCACHETAGZ_NOP << MXC_F_GCR_MEM_ZERO_SCACHETAGZ_POS) /**< MEM_ZERO_SCACHETAGZ_NOP Setting */ 822 #define MXC_V_GCR_MEM_ZERO_SCACHETAGZ_START ((uint32_t)0x1UL) /**< MEM_ZERO_SCACHETAGZ_START Value */ 823 #define MXC_S_GCR_MEM_ZERO_SCACHETAGZ_START (MXC_V_GCR_MEM_ZERO_SCACHETAGZ_START << MXC_F_GCR_MEM_ZERO_SCACHETAGZ_POS) /**< MEM_ZERO_SCACHETAGZ_START Setting */ 824 825 #define MXC_F_GCR_MEM_ZERO_CRYPTOZ_POS 12 /**< MEM_ZERO_CRYPTOZ Position */ 826 #define MXC_F_GCR_MEM_ZERO_CRYPTOZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_CRYPTOZ_POS)) /**< MEM_ZERO_CRYPTOZ Mask */ 827 #define MXC_V_GCR_MEM_ZERO_CRYPTOZ_NOP ((uint32_t)0x0UL) /**< MEM_ZERO_CRYPTOZ_NOP Value */ 828 #define MXC_S_GCR_MEM_ZERO_CRYPTOZ_NOP (MXC_V_GCR_MEM_ZERO_CRYPTOZ_NOP << MXC_F_GCR_MEM_ZERO_CRYPTOZ_POS) /**< MEM_ZERO_CRYPTOZ_NOP Setting */ 829 #define MXC_V_GCR_MEM_ZERO_CRYPTOZ_START ((uint32_t)0x1UL) /**< MEM_ZERO_CRYPTOZ_START Value */ 830 #define MXC_S_GCR_MEM_ZERO_CRYPTOZ_START (MXC_V_GCR_MEM_ZERO_CRYPTOZ_START << MXC_F_GCR_MEM_ZERO_CRYPTOZ_POS) /**< MEM_ZERO_CRYPTOZ_START Setting */ 831 832 #define MXC_F_GCR_MEM_ZERO_USBFIFOZ_POS 13 /**< MEM_ZERO_USBFIFOZ Position */ 833 #define MXC_F_GCR_MEM_ZERO_USBFIFOZ ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZERO_USBFIFOZ_POS)) /**< MEM_ZERO_USBFIFOZ Mask */ 834 #define MXC_V_GCR_MEM_ZERO_USBFIFOZ_NOP ((uint32_t)0x0UL) /**< MEM_ZERO_USBFIFOZ_NOP Value */ 835 #define MXC_S_GCR_MEM_ZERO_USBFIFOZ_NOP (MXC_V_GCR_MEM_ZERO_USBFIFOZ_NOP << MXC_F_GCR_MEM_ZERO_USBFIFOZ_POS) /**< MEM_ZERO_USBFIFOZ_NOP Setting */ 836 #define MXC_V_GCR_MEM_ZERO_USBFIFOZ_START ((uint32_t)0x1UL) /**< MEM_ZERO_USBFIFOZ_START Value */ 837 #define MXC_S_GCR_MEM_ZERO_USBFIFOZ_START (MXC_V_GCR_MEM_ZERO_USBFIFOZ_START << MXC_F_GCR_MEM_ZERO_USBFIFOZ_POS) /**< MEM_ZERO_USBFIFOZ_START Setting */ 838 839 /**@} end of group GCR_MEM_ZERO_Register */ 840 841 /** 842 * @ingroup gcr_registers 843 * @defgroup GCR_SYS_STAT GCR_SYS_STAT 844 * @brief System Status Register. 845 * @{ 846 */ 847 #define MXC_F_GCR_SYS_STAT_ICELOCK_POS 0 /**< SYS_STAT_ICELOCK Position */ 848 #define MXC_F_GCR_SYS_STAT_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_ICELOCK_POS)) /**< SYS_STAT_ICELOCK Mask */ 849 #define MXC_V_GCR_SYS_STAT_ICELOCK_UNLOCKED ((uint32_t)0x0UL) /**< SYS_STAT_ICELOCK_UNLOCKED Value */ 850 #define MXC_S_GCR_SYS_STAT_ICELOCK_UNLOCKED (MXC_V_GCR_SYS_STAT_ICELOCK_UNLOCKED << MXC_F_GCR_SYS_STAT_ICELOCK_POS) /**< SYS_STAT_ICELOCK_UNLOCKED Setting */ 851 #define MXC_V_GCR_SYS_STAT_ICELOCK_LOCKED ((uint32_t)0x1UL) /**< SYS_STAT_ICELOCK_LOCKED Value */ 852 #define MXC_S_GCR_SYS_STAT_ICELOCK_LOCKED (MXC_V_GCR_SYS_STAT_ICELOCK_LOCKED << MXC_F_GCR_SYS_STAT_ICELOCK_POS) /**< SYS_STAT_ICELOCK_LOCKED Setting */ 853 854 #define MXC_F_GCR_SYS_STAT_CODEINTERR_POS 1 /**< SYS_STAT_CODEINTERR Position */ 855 #define MXC_F_GCR_SYS_STAT_CODEINTERR ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_CODEINTERR_POS)) /**< SYS_STAT_CODEINTERR Mask */ 856 #define MXC_V_GCR_SYS_STAT_CODEINTERR_NOERR ((uint32_t)0x0UL) /**< SYS_STAT_CODEINTERR_NOERR Value */ 857 #define MXC_S_GCR_SYS_STAT_CODEINTERR_NOERR (MXC_V_GCR_SYS_STAT_CODEINTERR_NOERR << MXC_F_GCR_SYS_STAT_CODEINTERR_POS) /**< SYS_STAT_CODEINTERR_NOERR Setting */ 858 #define MXC_V_GCR_SYS_STAT_CODEINTERR_ERR ((uint32_t)0x1UL) /**< SYS_STAT_CODEINTERR_ERR Value */ 859 #define MXC_S_GCR_SYS_STAT_CODEINTERR_ERR (MXC_V_GCR_SYS_STAT_CODEINTERR_ERR << MXC_F_GCR_SYS_STAT_CODEINTERR_POS) /**< SYS_STAT_CODEINTERR_ERR Setting */ 860 861 #define MXC_F_GCR_SYS_STAT_SCMEMF_POS 5 /**< SYS_STAT_SCMEMF Position */ 862 #define MXC_F_GCR_SYS_STAT_SCMEMF ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_SCMEMF_POS)) /**< SYS_STAT_SCMEMF Mask */ 863 #define MXC_V_GCR_SYS_STAT_SCMEMF_NOERR ((uint32_t)0x0UL) /**< SYS_STAT_SCMEMF_NOERR Value */ 864 #define MXC_S_GCR_SYS_STAT_SCMEMF_NOERR (MXC_V_GCR_SYS_STAT_SCMEMF_NOERR << MXC_F_GCR_SYS_STAT_SCMEMF_POS) /**< SYS_STAT_SCMEMF_NOERR Setting */ 865 #define MXC_V_GCR_SYS_STAT_SCMEMF_MEMFAULT ((uint32_t)0x1UL) /**< SYS_STAT_SCMEMF_MEMFAULT Value */ 866 #define MXC_S_GCR_SYS_STAT_SCMEMF_MEMFAULT (MXC_V_GCR_SYS_STAT_SCMEMF_MEMFAULT << MXC_F_GCR_SYS_STAT_SCMEMF_POS) /**< SYS_STAT_SCMEMF_MEMFAULT Setting */ 867 868 /**@} end of group GCR_SYS_STAT_Register */ 869 870 /** 871 * @ingroup gcr_registers 872 * @defgroup GCR_RST1 GCR_RST1 873 * @brief Reset 1. 874 * @{ 875 */ 876 #define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ 877 #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ 878 879 #define MXC_F_GCR_RST1_PT_POS 1 /**< RST1_PT Position */ 880 #define MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS)) /**< RST1_PT Mask */ 881 882 #define MXC_F_GCR_RST1_SPIXIP_POS 3 /**< RST1_SPIXIP Position */ 883 #define MXC_F_GCR_RST1_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIP_POS)) /**< RST1_SPIXIP Mask */ 884 885 #define MXC_F_GCR_RST1_XSPIM_POS 4 /**< RST1_XSPIM Position */ 886 #define MXC_F_GCR_RST1_XSPIM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_XSPIM_POS)) /**< RST1_XSPIM Mask */ 887 888 #define MXC_F_GCR_RST1_GPIO3_POS 5 /**< RST1_GPIO3 Position */ 889 #define MXC_F_GCR_RST1_GPIO3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_GPIO3_POS)) /**< RST1_GPIO3 Mask */ 890 891 #define MXC_F_GCR_RST1_SDHC_POS 6 /**< RST1_SDHC Position */ 892 #define MXC_F_GCR_RST1_SDHC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SDHC_POS)) /**< RST1_SDHC Mask */ 893 894 #define MXC_F_GCR_RST1_OWIRE_POS 7 /**< RST1_OWIRE Position */ 895 #define MXC_F_GCR_RST1_OWIRE ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWIRE_POS)) /**< RST1_OWIRE Mask */ 896 897 #define MXC_F_GCR_RST1_WDT1_POS 8 /**< RST1_WDT1 Position */ 898 #define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) /**< RST1_WDT1 Mask */ 899 900 #define MXC_F_GCR_RST1_SPI3_POS 9 /**< RST1_SPI3 Position */ 901 #define MXC_F_GCR_RST1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI3_POS)) /**< RST1_SPI3 Mask */ 902 903 #define MXC_F_GCR_RST1_I2S_POS 10 /**< RST1_I2S Position */ 904 #define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) /**< RST1_I2S Mask */ 905 906 #define MXC_F_GCR_RST1_XIPR_POS 15 /**< RST1_XIPR Position */ 907 #define MXC_F_GCR_RST1_XIPR ((uint32_t)(0x1UL << MXC_F_GCR_RST1_XIPR_POS)) /**< RST1_XIPR Mask */ 908 909 #define MXC_F_GCR_RST1_SEMA_POS 16 /**< RST1_SEMA Position */ 910 #define MXC_F_GCR_RST1_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SEMA_POS)) /**< RST1_SEMA Mask */ 911 912 /**@} end of group GCR_RST1_Register */ 913 914 /** 915 * @ingroup gcr_registers 916 * @defgroup GCR_PCLK_DIS1 GCR_PCLK_DIS1 917 * @brief Peripheral Clock Disable. 918 * @{ 919 */ 920 #define MXC_F_GCR_PCLK_DIS1_UART2_POS 1 /**< PCLK_DIS1_UART2 Position */ 921 #define MXC_F_GCR_PCLK_DIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_UART2_POS)) /**< PCLK_DIS1_UART2 Mask */ 922 #define MXC_V_GCR_PCLK_DIS1_UART2_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_UART2_EN Value */ 923 #define MXC_S_GCR_PCLK_DIS1_UART2_EN (MXC_V_GCR_PCLK_DIS1_UART2_EN << MXC_F_GCR_PCLK_DIS1_UART2_POS) /**< PCLK_DIS1_UART2_EN Setting */ 924 #define MXC_V_GCR_PCLK_DIS1_UART2_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_UART2_DIS Value */ 925 #define MXC_S_GCR_PCLK_DIS1_UART2_DIS (MXC_V_GCR_PCLK_DIS1_UART2_DIS << MXC_F_GCR_PCLK_DIS1_UART2_POS) /**< PCLK_DIS1_UART2_DIS Setting */ 926 927 #define MXC_F_GCR_PCLK_DIS1_TRNG_POS 2 /**< PCLK_DIS1_TRNG Position */ 928 #define MXC_F_GCR_PCLK_DIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_TRNG_POS)) /**< PCLK_DIS1_TRNG Mask */ 929 #define MXC_V_GCR_PCLK_DIS1_TRNG_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_TRNG_EN Value */ 930 #define MXC_S_GCR_PCLK_DIS1_TRNG_EN (MXC_V_GCR_PCLK_DIS1_TRNG_EN << MXC_F_GCR_PCLK_DIS1_TRNG_POS) /**< PCLK_DIS1_TRNG_EN Setting */ 931 #define MXC_V_GCR_PCLK_DIS1_TRNG_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_TRNG_DIS Value */ 932 #define MXC_S_GCR_PCLK_DIS1_TRNG_DIS (MXC_V_GCR_PCLK_DIS1_TRNG_DIS << MXC_F_GCR_PCLK_DIS1_TRNG_POS) /**< PCLK_DIS1_TRNG_DIS Setting */ 933 934 #define MXC_F_GCR_PCLK_DIS1_SFLC_POS 3 /**< PCLK_DIS1_SFLC Position */ 935 #define MXC_F_GCR_PCLK_DIS1_SFLC ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SFLC_POS)) /**< PCLK_DIS1_SFLC Mask */ 936 #define MXC_V_GCR_PCLK_DIS1_SFLC_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_SFLC_EN Value */ 937 #define MXC_S_GCR_PCLK_DIS1_SFLC_EN (MXC_V_GCR_PCLK_DIS1_SFLC_EN << MXC_F_GCR_PCLK_DIS1_SFLC_POS) /**< PCLK_DIS1_SFLC_EN Setting */ 938 #define MXC_V_GCR_PCLK_DIS1_SFLC_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_SFLC_DIS Value */ 939 #define MXC_S_GCR_PCLK_DIS1_SFLC_DIS (MXC_V_GCR_PCLK_DIS1_SFLC_DIS << MXC_F_GCR_PCLK_DIS1_SFLC_POS) /**< PCLK_DIS1_SFLC_DIS Setting */ 940 941 #define MXC_F_GCR_PCLK_DIS1_HBC_POS 4 /**< PCLK_DIS1_HBC Position */ 942 #define MXC_F_GCR_PCLK_DIS1_HBC ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_HBC_POS)) /**< PCLK_DIS1_HBC Mask */ 943 #define MXC_V_GCR_PCLK_DIS1_HBC_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_HBC_EN Value */ 944 #define MXC_S_GCR_PCLK_DIS1_HBC_EN (MXC_V_GCR_PCLK_DIS1_HBC_EN << MXC_F_GCR_PCLK_DIS1_HBC_POS) /**< PCLK_DIS1_HBC_EN Setting */ 945 #define MXC_V_GCR_PCLK_DIS1_HBC_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_HBC_DIS Value */ 946 #define MXC_S_GCR_PCLK_DIS1_HBC_DIS (MXC_V_GCR_PCLK_DIS1_HBC_DIS << MXC_F_GCR_PCLK_DIS1_HBC_POS) /**< PCLK_DIS1_HBC_DIS Setting */ 947 948 #define MXC_F_GCR_PCLK_DIS1_GPIO3_POS 6 /**< PCLK_DIS1_GPIO3 Position */ 949 #define MXC_F_GCR_PCLK_DIS1_GPIO3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_GPIO3_POS)) /**< PCLK_DIS1_GPIO3 Mask */ 950 #define MXC_V_GCR_PCLK_DIS1_GPIO3_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_GPIO3_EN Value */ 951 #define MXC_S_GCR_PCLK_DIS1_GPIO3_EN (MXC_V_GCR_PCLK_DIS1_GPIO3_EN << MXC_F_GCR_PCLK_DIS1_GPIO3_POS) /**< PCLK_DIS1_GPIO3_EN Setting */ 952 #define MXC_V_GCR_PCLK_DIS1_GPIO3_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_GPIO3_DIS Value */ 953 #define MXC_S_GCR_PCLK_DIS1_GPIO3_DIS (MXC_V_GCR_PCLK_DIS1_GPIO3_DIS << MXC_F_GCR_PCLK_DIS1_GPIO3_POS) /**< PCLK_DIS1_GPIO3_DIS Setting */ 954 955 #define MXC_F_GCR_PCLK_DIS1_SCACHE_POS 7 /**< PCLK_DIS1_SCACHE Position */ 956 #define MXC_F_GCR_PCLK_DIS1_SCACHE ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SCACHE_POS)) /**< PCLK_DIS1_SCACHE Mask */ 957 #define MXC_V_GCR_PCLK_DIS1_SCACHE_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_SCACHE_EN Value */ 958 #define MXC_S_GCR_PCLK_DIS1_SCACHE_EN (MXC_V_GCR_PCLK_DIS1_SCACHE_EN << MXC_F_GCR_PCLK_DIS1_SCACHE_POS) /**< PCLK_DIS1_SCACHE_EN Setting */ 959 #define MXC_V_GCR_PCLK_DIS1_SCACHE_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_SCACHE_DIS Value */ 960 #define MXC_S_GCR_PCLK_DIS1_SCACHE_DIS (MXC_V_GCR_PCLK_DIS1_SCACHE_DIS << MXC_F_GCR_PCLK_DIS1_SCACHE_POS) /**< PCLK_DIS1_SCACHE_DIS Setting */ 961 962 #define MXC_F_GCR_PCLK_DIS1_SDMA_POS 8 /**< PCLK_DIS1_SDMA Position */ 963 #define MXC_F_GCR_PCLK_DIS1_SDMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SDMA_POS)) /**< PCLK_DIS1_SDMA Mask */ 964 #define MXC_V_GCR_PCLK_DIS1_SDMA_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_SDMA_EN Value */ 965 #define MXC_S_GCR_PCLK_DIS1_SDMA_EN (MXC_V_GCR_PCLK_DIS1_SDMA_EN << MXC_F_GCR_PCLK_DIS1_SDMA_POS) /**< PCLK_DIS1_SDMA_EN Setting */ 966 #define MXC_V_GCR_PCLK_DIS1_SDMA_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_SDMA_DIS Value */ 967 #define MXC_S_GCR_PCLK_DIS1_SDMA_DIS (MXC_V_GCR_PCLK_DIS1_SDMA_DIS << MXC_F_GCR_PCLK_DIS1_SDMA_POS) /**< PCLK_DIS1_SDMA_DIS Setting */ 968 969 #define MXC_F_GCR_PCLK_DIS1_SEMA_POS 9 /**< PCLK_DIS1_SEMA Position */ 970 #define MXC_F_GCR_PCLK_DIS1_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SEMA_POS)) /**< PCLK_DIS1_SEMA Mask */ 971 #define MXC_V_GCR_PCLK_DIS1_SEMA_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_SEMA_EN Value */ 972 #define MXC_S_GCR_PCLK_DIS1_SEMA_EN (MXC_V_GCR_PCLK_DIS1_SEMA_EN << MXC_F_GCR_PCLK_DIS1_SEMA_POS) /**< PCLK_DIS1_SEMA_EN Setting */ 973 #define MXC_V_GCR_PCLK_DIS1_SEMA_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_SEMA_DIS Value */ 974 #define MXC_S_GCR_PCLK_DIS1_SEMA_DIS (MXC_V_GCR_PCLK_DIS1_SEMA_DIS << MXC_F_GCR_PCLK_DIS1_SEMA_POS) /**< PCLK_DIS1_SEMA_DIS Setting */ 975 976 #define MXC_F_GCR_PCLK_DIS1_SDHC_POS 10 /**< PCLK_DIS1_SDHC Position */ 977 #define MXC_F_GCR_PCLK_DIS1_SDHC ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SDHC_POS)) /**< PCLK_DIS1_SDHC Mask */ 978 #define MXC_V_GCR_PCLK_DIS1_SDHC_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_SDHC_EN Value */ 979 #define MXC_S_GCR_PCLK_DIS1_SDHC_EN (MXC_V_GCR_PCLK_DIS1_SDHC_EN << MXC_F_GCR_PCLK_DIS1_SDHC_POS) /**< PCLK_DIS1_SDHC_EN Setting */ 980 #define MXC_V_GCR_PCLK_DIS1_SDHC_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_SDHC_DIS Value */ 981 #define MXC_S_GCR_PCLK_DIS1_SDHC_DIS (MXC_V_GCR_PCLK_DIS1_SDHC_DIS << MXC_F_GCR_PCLK_DIS1_SDHC_POS) /**< PCLK_DIS1_SDHC_DIS Setting */ 982 983 #define MXC_F_GCR_PCLK_DIS1_ICACHE_POS 11 /**< PCLK_DIS1_ICACHE Position */ 984 #define MXC_F_GCR_PCLK_DIS1_ICACHE ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_ICACHE_POS)) /**< PCLK_DIS1_ICACHE Mask */ 985 #define MXC_V_GCR_PCLK_DIS1_ICACHE_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_ICACHE_EN Value */ 986 #define MXC_S_GCR_PCLK_DIS1_ICACHE_EN (MXC_V_GCR_PCLK_DIS1_ICACHE_EN << MXC_F_GCR_PCLK_DIS1_ICACHE_POS) /**< PCLK_DIS1_ICACHE_EN Setting */ 987 #define MXC_V_GCR_PCLK_DIS1_ICACHE_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_ICACHE_DIS Value */ 988 #define MXC_S_GCR_PCLK_DIS1_ICACHE_DIS (MXC_V_GCR_PCLK_DIS1_ICACHE_DIS << MXC_F_GCR_PCLK_DIS1_ICACHE_POS) /**< PCLK_DIS1_ICACHE_DIS Setting */ 989 990 #define MXC_F_GCR_PCLK_DIS1_ICACHEXIPF_POS 12 /**< PCLK_DIS1_ICACHEXIPF Position */ 991 #define MXC_F_GCR_PCLK_DIS1_ICACHEXIPF ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_ICACHEXIPF_POS)) /**< PCLK_DIS1_ICACHEXIPF Mask */ 992 #define MXC_V_GCR_PCLK_DIS1_ICACHEXIPF_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_ICACHEXIPF_EN Value */ 993 #define MXC_S_GCR_PCLK_DIS1_ICACHEXIPF_EN (MXC_V_GCR_PCLK_DIS1_ICACHEXIPF_EN << MXC_F_GCR_PCLK_DIS1_ICACHEXIPF_POS) /**< PCLK_DIS1_ICACHEXIPF_EN Setting */ 994 #define MXC_V_GCR_PCLK_DIS1_ICACHEXIPF_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_ICACHEXIPF_DIS Value */ 995 #define MXC_S_GCR_PCLK_DIS1_ICACHEXIPF_DIS (MXC_V_GCR_PCLK_DIS1_ICACHEXIPF_DIS << MXC_F_GCR_PCLK_DIS1_ICACHEXIPF_POS) /**< PCLK_DIS1_ICACHEXIPF_DIS Setting */ 996 997 #define MXC_F_GCR_PCLK_DIS1_OW_POS 13 /**< PCLK_DIS1_OW Position */ 998 #define MXC_F_GCR_PCLK_DIS1_OW ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_OW_POS)) /**< PCLK_DIS1_OW Mask */ 999 #define MXC_V_GCR_PCLK_DIS1_OW_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_OW_EN Value */ 1000 #define MXC_S_GCR_PCLK_DIS1_OW_EN (MXC_V_GCR_PCLK_DIS1_OW_EN << MXC_F_GCR_PCLK_DIS1_OW_POS) /**< PCLK_DIS1_OW_EN Setting */ 1001 #define MXC_V_GCR_PCLK_DIS1_OW_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_OW_DIS Value */ 1002 #define MXC_S_GCR_PCLK_DIS1_OW_DIS (MXC_V_GCR_PCLK_DIS1_OW_DIS << MXC_F_GCR_PCLK_DIS1_OW_POS) /**< PCLK_DIS1_OW_DIS Setting */ 1003 1004 #define MXC_F_GCR_PCLK_DIS1_SPI3_POS 14 /**< PCLK_DIS1_SPI3 Position */ 1005 #define MXC_F_GCR_PCLK_DIS1_SPI3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SPI3_POS)) /**< PCLK_DIS1_SPI3 Mask */ 1006 #define MXC_V_GCR_PCLK_DIS1_SPI3_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_SPI3_EN Value */ 1007 #define MXC_S_GCR_PCLK_DIS1_SPI3_EN (MXC_V_GCR_PCLK_DIS1_SPI3_EN << MXC_F_GCR_PCLK_DIS1_SPI3_POS) /**< PCLK_DIS1_SPI3_EN Setting */ 1008 #define MXC_V_GCR_PCLK_DIS1_SPI3_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_SPI3_DIS Value */ 1009 #define MXC_S_GCR_PCLK_DIS1_SPI3_DIS (MXC_V_GCR_PCLK_DIS1_SPI3_DIS << MXC_F_GCR_PCLK_DIS1_SPI3_POS) /**< PCLK_DIS1_SPI3_DIS Setting */ 1010 1011 #define MXC_F_GCR_PCLK_DIS1_I2S_POS 15 /**< PCLK_DIS1_I2S Position */ 1012 #define MXC_F_GCR_PCLK_DIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_I2S_POS)) /**< PCLK_DIS1_I2S Mask */ 1013 #define MXC_V_GCR_PCLK_DIS1_I2S_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_I2S_EN Value */ 1014 #define MXC_S_GCR_PCLK_DIS1_I2S_EN (MXC_V_GCR_PCLK_DIS1_I2S_EN << MXC_F_GCR_PCLK_DIS1_I2S_POS) /**< PCLK_DIS1_I2S_EN Setting */ 1015 #define MXC_V_GCR_PCLK_DIS1_I2S_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_I2S_DIS Value */ 1016 #define MXC_S_GCR_PCLK_DIS1_I2S_DIS (MXC_V_GCR_PCLK_DIS1_I2S_DIS << MXC_F_GCR_PCLK_DIS1_I2S_POS) /**< PCLK_DIS1_I2S_DIS Setting */ 1017 1018 #define MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS 20 /**< PCLK_DIS1_SPIXIPR Position */ 1019 #define MXC_F_GCR_PCLK_DIS1_SPIXIPR ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS)) /**< PCLK_DIS1_SPIXIPR Mask */ 1020 #define MXC_V_GCR_PCLK_DIS1_SPIXIPR_EN ((uint32_t)0x0UL) /**< PCLK_DIS1_SPIXIPR_EN Value */ 1021 #define MXC_S_GCR_PCLK_DIS1_SPIXIPR_EN (MXC_V_GCR_PCLK_DIS1_SPIXIPR_EN << MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS) /**< PCLK_DIS1_SPIXIPR_EN Setting */ 1022 #define MXC_V_GCR_PCLK_DIS1_SPIXIPR_DIS ((uint32_t)0x1UL) /**< PCLK_DIS1_SPIXIPR_DIS Value */ 1023 #define MXC_S_GCR_PCLK_DIS1_SPIXIPR_DIS (MXC_V_GCR_PCLK_DIS1_SPIXIPR_DIS << MXC_F_GCR_PCLK_DIS1_SPIXIPR_POS) /**< PCLK_DIS1_SPIXIPR_DIS Setting */ 1024 1025 /**@} end of group GCR_PCLK_DIS1_Register */ 1026 1027 /** 1028 * @ingroup gcr_registers 1029 * @defgroup GCR_EVENT_EN GCR_EVENT_EN 1030 * @brief Event Enable Register. 1031 * @{ 1032 */ 1033 #define MXC_F_GCR_EVENT_EN_DMAEVENT_POS 0 /**< EVENT_EN_DMAEVENT Position */ 1034 #define MXC_F_GCR_EVENT_EN_DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_DMAEVENT_POS)) /**< EVENT_EN_DMAEVENT Mask */ 1035 #define MXC_V_GCR_EVENT_EN_DMAEVENT_DIS ((uint32_t)0x0UL) /**< EVENT_EN_DMAEVENT_DIS Value */ 1036 #define MXC_S_GCR_EVENT_EN_DMAEVENT_DIS (MXC_V_GCR_EVENT_EN_DMAEVENT_DIS << MXC_F_GCR_EVENT_EN_DMAEVENT_POS) /**< EVENT_EN_DMAEVENT_DIS Setting */ 1037 #define MXC_V_GCR_EVENT_EN_DMAEVENT_EN ((uint32_t)0x1UL) /**< EVENT_EN_DMAEVENT_EN Value */ 1038 #define MXC_S_GCR_EVENT_EN_DMAEVENT_EN (MXC_V_GCR_EVENT_EN_DMAEVENT_EN << MXC_F_GCR_EVENT_EN_DMAEVENT_POS) /**< EVENT_EN_DMAEVENT_EN Setting */ 1039 1040 #define MXC_F_GCR_EVENT_EN_RXEVENT_POS 1 /**< EVENT_EN_RXEVENT Position */ 1041 #define MXC_F_GCR_EVENT_EN_RXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_RXEVENT_POS)) /**< EVENT_EN_RXEVENT Mask */ 1042 #define MXC_V_GCR_EVENT_EN_RXEVENT_DIS ((uint32_t)0x0UL) /**< EVENT_EN_RXEVENT_DIS Value */ 1043 #define MXC_S_GCR_EVENT_EN_RXEVENT_DIS (MXC_V_GCR_EVENT_EN_RXEVENT_DIS << MXC_F_GCR_EVENT_EN_RXEVENT_POS) /**< EVENT_EN_RXEVENT_DIS Setting */ 1044 #define MXC_V_GCR_EVENT_EN_RXEVENT_EN ((uint32_t)0x1UL) /**< EVENT_EN_RXEVENT_EN Value */ 1045 #define MXC_S_GCR_EVENT_EN_RXEVENT_EN (MXC_V_GCR_EVENT_EN_RXEVENT_EN << MXC_F_GCR_EVENT_EN_RXEVENT_POS) /**< EVENT_EN_RXEVENT_EN Setting */ 1046 1047 #define MXC_F_GCR_EVENT_EN_TXEVENT_POS 2 /**< EVENT_EN_TXEVENT Position */ 1048 #define MXC_F_GCR_EVENT_EN_TXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVENT_EN_TXEVENT_POS)) /**< EVENT_EN_TXEVENT Mask */ 1049 #define MXC_V_GCR_EVENT_EN_TXEVENT_DIS ((uint32_t)0x0UL) /**< EVENT_EN_TXEVENT_DIS Value */ 1050 #define MXC_S_GCR_EVENT_EN_TXEVENT_DIS (MXC_V_GCR_EVENT_EN_TXEVENT_DIS << MXC_F_GCR_EVENT_EN_TXEVENT_POS) /**< EVENT_EN_TXEVENT_DIS Setting */ 1051 #define MXC_V_GCR_EVENT_EN_TXEVENT_EN ((uint32_t)0x1UL) /**< EVENT_EN_TXEVENT_EN Value */ 1052 #define MXC_S_GCR_EVENT_EN_TXEVENT_EN (MXC_V_GCR_EVENT_EN_TXEVENT_EN << MXC_F_GCR_EVENT_EN_TXEVENT_POS) /**< EVENT_EN_TXEVENT_EN Setting */ 1053 1054 /**@} end of group GCR_EVENT_EN_Register */ 1055 1056 /** 1057 * @ingroup gcr_registers 1058 * @defgroup GCR_REV GCR_REV 1059 * @brief Revision Register. 1060 * @{ 1061 */ 1062 #define MXC_F_GCR_REV_REVISION_POS 0 /**< REV_REVISION Position */ 1063 #define MXC_F_GCR_REV_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REV_REVISION_POS)) /**< REV_REVISION Mask */ 1064 1065 /**@} end of group GCR_REV_Register */ 1066 1067 /** 1068 * @ingroup gcr_registers 1069 * @defgroup GCR_SYS_STAT_IE GCR_SYS_STAT_IE 1070 * @brief System Status Interrupt Enable Register. 1071 * @{ 1072 */ 1073 #define MXC_F_GCR_SYS_STAT_IE_ICEULIE_POS 0 /**< SYS_STAT_IE_ICEULIE Position */ 1074 #define MXC_F_GCR_SYS_STAT_IE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_IE_ICEULIE_POS)) /**< SYS_STAT_IE_ICEULIE Mask */ 1075 #define MXC_V_GCR_SYS_STAT_IE_ICEULIE_DIS ((uint32_t)0x0UL) /**< SYS_STAT_IE_ICEULIE_DIS Value */ 1076 #define MXC_S_GCR_SYS_STAT_IE_ICEULIE_DIS (MXC_V_GCR_SYS_STAT_IE_ICEULIE_DIS << MXC_F_GCR_SYS_STAT_IE_ICEULIE_POS) /**< SYS_STAT_IE_ICEULIE_DIS Setting */ 1077 #define MXC_V_GCR_SYS_STAT_IE_ICEULIE_EN ((uint32_t)0x1UL) /**< SYS_STAT_IE_ICEULIE_EN Value */ 1078 #define MXC_S_GCR_SYS_STAT_IE_ICEULIE_EN (MXC_V_GCR_SYS_STAT_IE_ICEULIE_EN << MXC_F_GCR_SYS_STAT_IE_ICEULIE_POS) /**< SYS_STAT_IE_ICEULIE_EN Setting */ 1079 1080 #define MXC_F_GCR_SYS_STAT_IE_CIEIE_POS 1 /**< SYS_STAT_IE_CIEIE Position */ 1081 #define MXC_F_GCR_SYS_STAT_IE_CIEIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_IE_CIEIE_POS)) /**< SYS_STAT_IE_CIEIE Mask */ 1082 #define MXC_V_GCR_SYS_STAT_IE_CIEIE_DIS ((uint32_t)0x0UL) /**< SYS_STAT_IE_CIEIE_DIS Value */ 1083 #define MXC_S_GCR_SYS_STAT_IE_CIEIE_DIS (MXC_V_GCR_SYS_STAT_IE_CIEIE_DIS << MXC_F_GCR_SYS_STAT_IE_CIEIE_POS) /**< SYS_STAT_IE_CIEIE_DIS Setting */ 1084 #define MXC_V_GCR_SYS_STAT_IE_CIEIE_EN ((uint32_t)0x1UL) /**< SYS_STAT_IE_CIEIE_EN Value */ 1085 #define MXC_S_GCR_SYS_STAT_IE_CIEIE_EN (MXC_V_GCR_SYS_STAT_IE_CIEIE_EN << MXC_F_GCR_SYS_STAT_IE_CIEIE_POS) /**< SYS_STAT_IE_CIEIE_EN Setting */ 1086 1087 #define MXC_F_GCR_SYS_STAT_IE_SCMFIE_POS 5 /**< SYS_STAT_IE_SCMFIE Position */ 1088 #define MXC_F_GCR_SYS_STAT_IE_SCMFIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_IE_SCMFIE_POS)) /**< SYS_STAT_IE_SCMFIE Mask */ 1089 #define MXC_V_GCR_SYS_STAT_IE_SCMFIE_DIS ((uint32_t)0x0UL) /**< SYS_STAT_IE_SCMFIE_DIS Value */ 1090 #define MXC_S_GCR_SYS_STAT_IE_SCMFIE_DIS (MXC_V_GCR_SYS_STAT_IE_SCMFIE_DIS << MXC_F_GCR_SYS_STAT_IE_SCMFIE_POS) /**< SYS_STAT_IE_SCMFIE_DIS Setting */ 1091 #define MXC_V_GCR_SYS_STAT_IE_SCMFIE_EN ((uint32_t)0x1UL) /**< SYS_STAT_IE_SCMFIE_EN Value */ 1092 #define MXC_S_GCR_SYS_STAT_IE_SCMFIE_EN (MXC_V_GCR_SYS_STAT_IE_SCMFIE_EN << MXC_F_GCR_SYS_STAT_IE_SCMFIE_POS) /**< SYS_STAT_IE_SCMFIE_EN Setting */ 1093 1094 /**@} end of group GCR_SYS_STAT_IE_Register */ 1095 1096 #ifdef __cplusplus 1097 } 1098 #endif 1099 1100 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_GCR_REGS_H_ 1101
