1 /*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #ifndef FSL_PLU_H_
8 #define FSL_PLU_H_
9
10 #include "fsl_common.h"
11
12 /*!
13 * @addtogroup plu
14 * @{
15 */
16
17 /*******************************************************************************
18 * Definitions
19 ******************************************************************************/
20
21 /*! @name Driver version */
22 /*! @{ */
23 #define FSL_PLU_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */
24 /*! @} */
25
26 /*! @brief Index of LUT */
27 typedef enum _plu_lut_index
28 {
29 kPLU_LUT_0 = 0U, /*!< 5-input Look-up Table 0 */
30 kPLU_LUT_1 = 1U, /*!< 5-input Look-up Table 1 */
31 kPLU_LUT_2 = 2U, /*!< 5-input Look-up Table 2 */
32 kPLU_LUT_3 = 3U, /*!< 5-input Look-up Table 3 */
33 kPLU_LUT_4 = 4U, /*!< 5-input Look-up Table 4 */
34 kPLU_LUT_5 = 5U, /*!< 5-input Look-up Table 5 */
35 kPLU_LUT_6 = 6U, /*!< 5-input Look-up Table 6 */
36 kPLU_LUT_7 = 7U, /*!< 5-input Look-up Table 7 */
37 kPLU_LUT_8 = 8U, /*!< 5-input Look-up Table 8 */
38 kPLU_LUT_9 = 9U, /*!< 5-input Look-up Table 9 */
39 kPLU_LUT_10 = 10U, /*!< 5-input Look-up Table 10 */
40 kPLU_LUT_11 = 11U, /*!< 5-input Look-up Table 11 */
41 kPLU_LUT_12 = 12U, /*!< 5-input Look-up Table 12 */
42 kPLU_LUT_13 = 13U, /*!< 5-input Look-up Table 13 */
43 kPLU_LUT_14 = 14U, /*!< 5-input Look-up Table 14 */
44 kPLU_LUT_15 = 15U, /*!< 5-input Look-up Table 15 */
45 kPLU_LUT_16 = 16U, /*!< 5-input Look-up Table 16 */
46 kPLU_LUT_17 = 17U, /*!< 5-input Look-up Table 17 */
47 kPLU_LUT_18 = 18U, /*!< 5-input Look-up Table 18 */
48 kPLU_LUT_19 = 19U, /*!< 5-input Look-up Table 19 */
49 kPLU_LUT_20 = 20U, /*!< 5-input Look-up Table 20 */
50 kPLU_LUT_21 = 21U, /*!< 5-input Look-up Table 21 */
51 kPLU_LUT_22 = 22U, /*!< 5-input Look-up Table 22 */
52 kPLU_LUT_23 = 23U, /*!< 5-input Look-up Table 23 */
53 kPLU_LUT_24 = 24U, /*!< 5-input Look-up Table 24 */
54 kPLU_LUT_25 = 25U /*!< 5-input Look-up Table 25 */
55 } plu_lut_index_t;
56
57 /*! @brief Inputs of LUT. 5 input present for each LUT. */
58 typedef enum _plu_lut_in_index
59 {
60 kPLU_LUT_IN_0 = 0U, /*!< LUT input 0 */
61 kPLU_LUT_IN_1 = 1U, /*!< LUT input 1 */
62 kPLU_LUT_IN_2 = 2U, /*!< LUT input 2 */
63 kPLU_LUT_IN_3 = 3U, /*!< LUT input 3 */
64 kPLU_LUT_IN_4 = 4U /*!< LUT input 4 */
65 } plu_lut_in_index_t;
66
67 /*! @brief Available sources of LUT input */
68 typedef enum _plu_lut_input_source
69 {
70 kPLU_LUT_IN_SRC_PLU_IN_0 = 0U, /*!< Select PLU input 0 to be connected to LUTn Input x */
71 kPLU_LUT_IN_SRC_PLU_IN_1 = 1U, /*!< Select PLU input 1 to be connected to LUTn Input x */
72 kPLU_LUT_IN_SRC_PLU_IN_2 = 2U, /*!< Select PLU input 2 to be connected to LUTn Input x */
73 kPLU_LUT_IN_SRC_PLU_IN_3 = 3U, /*!< Select PLU input 3 to be connected to LUTn Input x */
74 kPLU_LUT_IN_SRC_PLU_IN_4 = 4U, /*!< Select PLU input 4 to be connected to LUTn Input x */
75 kPLU_LUT_IN_SRC_PLU_IN_5 = 5U, /*!< Select PLU input 5 to be connected to LUTn Input x */
76 kPLU_LUT_IN_SRC_LUT_OUT_0 = 6U, /*!< Select LUT output 0 to be connected to LUTn Input x */
77 kPLU_LUT_IN_SRC_LUT_OUT_1 = 7U, /*!< Select LUT output 1 to be connected to LUTn Input x */
78 kPLU_LUT_IN_SRC_LUT_OUT_2 = 8U, /*!< Select LUT output 2 to be connected to LUTn Input x */
79 kPLU_LUT_IN_SRC_LUT_OUT_3 = 9U, /*!< Select LUT output 3 to be connected to LUTn Input x */
80 kPLU_LUT_IN_SRC_LUT_OUT_4 = 10U, /*!< Select LUT output 4 to be connected to LUTn Input x */
81 kPLU_LUT_IN_SRC_LUT_OUT_5 = 11U, /*!< Select LUT output 5 to be connected to LUTn Input x */
82 kPLU_LUT_IN_SRC_LUT_OUT_6 = 12U, /*!< Select LUT output 6 to be connected to LUTn Input x */
83 kPLU_LUT_IN_SRC_LUT_OUT_7 = 13U, /*!< Select LUT output 7 to be connected to LUTn Input x */
84 kPLU_LUT_IN_SRC_LUT_OUT_8 = 14U, /*!< Select LUT output 8 to be connected to LUTn Input x */
85 kPLU_LUT_IN_SRC_LUT_OUT_9 = 15U, /*!< Select LUT output 9 to be connected to LUTn Input x */
86 kPLU_LUT_IN_SRC_LUT_OUT_10 = 16U, /*!< Select LUT output 10 to be connected to LUTn Input x */
87 kPLU_LUT_IN_SRC_LUT_OUT_11 = 17U, /*!< Select LUT output 11 to be connected to LUTn Input x */
88 kPLU_LUT_IN_SRC_LUT_OUT_12 = 18U, /*!< Select LUT output 12 to be connected to LUTn Input x */
89 kPLU_LUT_IN_SRC_LUT_OUT_13 = 19U, /*!< Select LUT output 13 to be connected to LUTn Input x */
90 kPLU_LUT_IN_SRC_LUT_OUT_14 = 20U, /*!< Select LUT output 14 to be connected to LUTn Input x */
91 kPLU_LUT_IN_SRC_LUT_OUT_15 = 21U, /*!< Select LUT output 15 to be connected to LUTn Input x */
92 kPLU_LUT_IN_SRC_LUT_OUT_16 = 22U, /*!< Select LUT output 16 to be connected to LUTn Input x */
93 kPLU_LUT_IN_SRC_LUT_OUT_17 = 23U, /*!< Select LUT output 17 to be connected to LUTn Input x */
94 kPLU_LUT_IN_SRC_LUT_OUT_18 = 24U, /*!< Select LUT output 18 to be connected to LUTn Input x */
95 kPLU_LUT_IN_SRC_LUT_OUT_19 = 25U, /*!< Select LUT output 19 to be connected to LUTn Input x */
96 kPLU_LUT_IN_SRC_LUT_OUT_20 = 26U, /*!< Select LUT output 20 to be connected to LUTn Input x */
97 kPLU_LUT_IN_SRC_LUT_OUT_21 = 27U, /*!< Select LUT output 21 to be connected to LUTn Input x */
98 kPLU_LUT_IN_SRC_LUT_OUT_22 = 28U, /*!< Select LUT output 22 to be connected to LUTn Input x */
99 kPLU_LUT_IN_SRC_LUT_OUT_23 = 29U, /*!< Select LUT output 23 to be connected to LUTn Input x */
100 kPLU_LUT_IN_SRC_LUT_OUT_24 = 30U, /*!< Select LUT output 24 to be connected to LUTn Input x */
101 kPLU_LUT_IN_SRC_LUT_OUT_25 = 31U, /*!< Select LUT output 25 to be connected to LUTn Input x */
102 kPLU_LUT_IN_SRC_FLIPFLOP_0 = 32U, /*!< Select Flip-Flops state 0 to be connected to LUTn Input x */
103 kPLU_LUT_IN_SRC_FLIPFLOP_1 = 33U, /*!< Select Flip-Flops state 1 to be connected to LUTn Input x */
104 kPLU_LUT_IN_SRC_FLIPFLOP_2 = 34U, /*!< Select Flip-Flops state 2 to be connected to LUTn Input x */
105 kPLU_LUT_IN_SRC_FLIPFLOP_3 = 35U /*!< Select Flip-Flops state 3 to be connected to LUTn Input x */
106 } plu_lut_input_source_t;
107
108 /*! @brief PLU output multiplexer registers */
109 typedef enum _plu_output_index
110 {
111 kPLU_OUTPUT_0 = 0U, /*!< PLU OUTPUT 0 */
112 kPLU_OUTPUT_1 = 1U, /*!< PLU OUTPUT 1 */
113 kPLU_OUTPUT_2 = 2U, /*!< PLU OUTPUT 2 */
114 kPLU_OUTPUT_3 = 3U, /*!< PLU OUTPUT 3 */
115 kPLU_OUTPUT_4 = 4U, /*!< PLU OUTPUT 4 */
116 kPLU_OUTPUT_5 = 5U, /*!< PLU OUTPUT 5 */
117 kPLU_OUTPUT_6 = 6U, /*!< PLU OUTPUT 6 */
118 kPLU_OUTPUT_7 = 7U /*!< PLU OUTPUT 7 */
119 } plu_output_index_t;
120
121 /*! @brief Available sources of PLU output */
122 typedef enum _plu_output_source
123 {
124 kPLU_OUT_SRC_LUT_0 = 0U, /*!< Select LUT0 output to be connected to PLU output */
125 kPLU_OUT_SRC_LUT_1 = 1U, /*!< Select LUT1 output to be connected to PLU output */
126 kPLU_OUT_SRC_LUT_2 = 2U, /*!< Select LUT2 output to be connected to PLU output */
127 kPLU_OUT_SRC_LUT_3 = 3U, /*!< Select LUT3 output to be connected to PLU output */
128 kPLU_OUT_SRC_LUT_4 = 4U, /*!< Select LUT4 output to be connected to PLU output */
129 kPLU_OUT_SRC_LUT_5 = 5U, /*!< Select LUT5 output to be connected to PLU output */
130 kPLU_OUT_SRC_LUT_6 = 6U, /*!< Select LUT6 output to be connected to PLU output */
131 kPLU_OUT_SRC_LUT_7 = 7U, /*!< Select LUT7 output to be connected to PLU output */
132 kPLU_OUT_SRC_LUT_8 = 8U, /*!< Select LUT8 output to be connected to PLU output */
133 kPLU_OUT_SRC_LUT_9 = 9U, /*!< Select LUT9 output to be connected to PLU output */
134 kPLU_OUT_SRC_LUT_10 = 10U, /*!< Select LUT10 output to be connected to PLU output */
135 kPLU_OUT_SRC_LUT_11 = 11U, /*!< Select LUT11 output to be connected to PLU output */
136 kPLU_OUT_SRC_LUT_12 = 12U, /*!< Select LUT12 output to be connected to PLU output */
137 kPLU_OUT_SRC_LUT_13 = 13U, /*!< Select LUT13 output to be connected to PLU output */
138 kPLU_OUT_SRC_LUT_14 = 14U, /*!< Select LUT14 output to be connected to PLU output */
139 kPLU_OUT_SRC_LUT_15 = 15U, /*!< Select LUT15 output to be connected to PLU output */
140 kPLU_OUT_SRC_LUT_16 = 16U, /*!< Select LUT16 output to be connected to PLU output */
141 kPLU_OUT_SRC_LUT_17 = 17U, /*!< Select LUT17 output to be connected to PLU output */
142 kPLU_OUT_SRC_LUT_18 = 18U, /*!< Select LUT18 output to be connected to PLU output */
143 kPLU_OUT_SRC_LUT_19 = 19U, /*!< Select LUT19 output to be connected to PLU output */
144 kPLU_OUT_SRC_LUT_20 = 20U, /*!< Select LUT20 output to be connected to PLU output */
145 kPLU_OUT_SRC_LUT_21 = 21U, /*!< Select LUT21 output to be connected to PLU output */
146 kPLU_OUT_SRC_LUT_22 = 22U, /*!< Select LUT22 output to be connected to PLU output */
147 kPLU_OUT_SRC_LUT_23 = 23U, /*!< Select LUT23 output to be connected to PLU output */
148 kPLU_OUT_SRC_LUT_24 = 24U, /*!< Select LUT24 output to be connected to PLU output */
149 kPLU_OUT_SRC_LUT_25 = 25U, /*!< Select LUT25 output to be connected to PLU output */
150 kPLU_OUT_SRC_FLIPFLOP_0 = 26U, /*!< Select Flip-Flops state(0) to be connected to PLU output */
151 kPLU_OUT_SRC_FLIPFLOP_1 = 27U, /*!< Select Flip-Flops state(1) to be connected to PLU output */
152 kPLU_OUT_SRC_FLIPFLOP_2 = 28U, /*!< Select Flip-Flops state(2) to be connected to PLU output */
153 kPLU_OUT_SRC_FLIPFLOP_3 = 29U /*!< Select Flip-Flops state(3) to be connected to PLU output */
154 } plu_output_source_t;
155
156 #if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG
157
158 /*! @brief The enumerator of PLU Interrupt. */
159 enum _plu_interrupt_mask
160 {
161 kPLU_OUTPUT_0_INTERRUPT_MASK = 1 << 0, /*!< Select PLU output 0 contribute to interrupt/wake-up generation */
162 kPLU_OUTPUT_1_INTERRUPT_MASK = 1 << 1, /*!< Select PLU output 1 contribute to interrupt/wake-up generation */
163 kPLU_OUTPUT_2_INTERRUPT_MASK = 1 << 2, /*!< Select PLU output 2 contribute to interrupt/wake-up generation */
164 kPLU_OUTPUT_3_INTERRUPT_MASK = 1 << 3, /*!< Select PLU output 3 contribute to interrupt/wake-up generation */
165 kPLU_OUTPUT_4_INTERRUPT_MASK = 1 << 4, /*!< Select PLU output 4 contribute to interrupt/wake-up generation */
166 kPLU_OUTPUT_5_INTERRUPT_MASK = 1 << 5, /*!< Select PLU output 5 contribute to interrupt/wake-up generation */
167 kPLU_OUTPUT_6_INTERRUPT_MASK = 1 << 6, /*!< Select PLU output 6 contribute to interrupt/wake-up generation */
168 kPLU_OUTPUT_7_INTERRUPT_MASK = 1 << 7 /*!< Select PLU output 7 contribute to interrupt/wake-up generation */
169 };
170
171 /*! @brief Control input of the PLU, add filtering for glitch. */
172 typedef enum _plu_wakeint_filter_mode
173 {
174 kPLU_WAKEINT_FILTER_MODE_BYPASS = 0U, /*!< Select Bypass mode */
175 kPLU_WAKEINT_FILTER_MODE_1_CLK_PERIOD = 1U, /*!< Filter 1 clock period */
176 kPLU_WAKEINT_FILTER_MODE_2_CLK_PERIOD = 2U, /*!< Filter 2 clock period */
177 kPLU_WAKEINT_FILTER_MODE_3_CLK_PERIOD = 3U /*!< Filter 3 clock period */
178 } plu_wakeint_filter_mode_t;
179
180 /*! @brief Clock source for filter mode. */
181 typedef enum _plu_wakeint_filter_clock_source
182 {
183 kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC = 0U, /*!< Select the 1MHz low-power oscillator as the filter clock */
184 kPLU_WAKEINT_FILTER_CLK_SRC_12MHZ_FRO = 1U, /*!< Select the 12MHz FRO as the filer clock */
185 kPLU_WAKEINT_FILTER_CLK_SRC_ALT = 2U /*!< Select a third clock source */
186 } plu_wakeint_filter_clock_source_t;
187
188 /*! @brief Wake configuration. */
189 typedef struct _plu_wakeint_config
190 {
191 plu_wakeint_filter_mode_t filterMode; /*!< Filter Mode. */
192 plu_wakeint_filter_clock_source_t clockSource; /*!< The clock source for filter mode. */
193 } plu_wakeint_config_t;
194 #endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */
195
196 /*******************************************************************************
197 * API
198 ******************************************************************************/
199
200 #if defined(__cplusplus)
201 extern "C" {
202 #endif
203
204 /*!
205 * @name Initialization and deinitialization
206 * @{
207 */
208
209 /*!
210 * @brief Enable the PLU clock and reset the module.
211 *
212 * @note This API should be called at the beginning of the application using the PLU driver.
213 *
214 * @param base PLU peripheral base address
215 */
216 void PLU_Init(PLU_Type *base);
217
218 /*!
219 * @brief Gate the PLU clock
220 *
221 * @param base PLU peripheral base address
222 */
223 void PLU_Deinit(PLU_Type *base);
224
225 /*! @}*/
226
227 /*!
228 * @name Set input/output source and Truth Table
229 * @{
230 */
231
232 /*!
233 * @brief Set Input source of LUT.
234 *
235 * Note: An external clock must be applied to the PLU_CLKIN input when using FFs.
236 * For each LUT, the slot associated with the output from LUTn itself is tied low.
237 *
238 * @param base PLU peripheral base address.
239 * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration).
240 * @param lutInIndex LUT input index (see @ref plu_lut_in_index_t typedef enumeration).
241 * @param inputSrc LUT input source (see @ref plu_lut_input_source_t typedef enumeration).
242 */
PLU_SetLutInputSource(PLU_Type * base,plu_lut_index_t lutIndex,plu_lut_in_index_t lutInIndex,plu_lut_input_source_t inputSrc)243 static inline void PLU_SetLutInputSource(PLU_Type *base,
244 plu_lut_index_t lutIndex,
245 plu_lut_in_index_t lutInIndex,
246 plu_lut_input_source_t inputSrc)
247 {
248 PLU->LUT[lutIndex].INP_MUX[lutInIndex] = (uint32_t)inputSrc;
249 }
250
251 /*!
252 * @brief Set Output source of PLU.
253 *
254 * Note: An external clock must be applied to the PLU_CLKIN input when using FFs.
255 *
256 * @param base PLU peripheral base address.
257 * @param outputIndex PLU output index (see @ref plu_output_index_t typedef enumeration).
258 * @param outputSrc PLU output source (see @ref plu_output_source_t typedef enumeration).
259 */
PLU_SetOutputSource(PLU_Type * base,plu_output_index_t outputIndex,plu_output_source_t outputSrc)260 static inline void PLU_SetOutputSource(PLU_Type *base, plu_output_index_t outputIndex, plu_output_source_t outputSrc)
261 {
262 base->OUTPUT_MUX[outputIndex] = (uint32_t)outputSrc;
263 }
264
265 /*!
266 * @brief Set Truth Table of LUT.
267 *
268 * @param base PLU peripheral base address.
269 * @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration).
270 * @param truthTable Truth Table value.
271 */
PLU_SetLutTruthTable(PLU_Type * base,plu_lut_index_t lutIndex,uint32_t truthTable)272 static inline void PLU_SetLutTruthTable(PLU_Type *base, plu_lut_index_t lutIndex, uint32_t truthTable)
273 {
274 base->LUT_TRUTH[lutIndex] = truthTable;
275 }
276
277 /*! @}*/
278
279 /*!
280 * @name Read current Output State
281 * @{
282 */
283
284 /*!
285 * @brief Read the current state of the 8 designated PLU Outputs.
286 *
287 * Note: The PLU bus clock must be re-enabled prior to reading the Outpus Register if PLU bus clock is
288 * shut-off.
289 *
290 * @param base PLU peripheral base address.
291 * @return Current PLU output state value.
292 */
PLU_ReadOutputState(PLU_Type * base)293 static inline uint32_t PLU_ReadOutputState(PLU_Type *base)
294 {
295 return (base->OUTPUTS & PLU_OUTPUTS_OUTPUT_STATE_MASK);
296 }
297
298 /*! @}*/
299
300 #if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG
301 /*!
302 * @name Wake-up/Interrupt Control
303 * @{
304 */
305
306 /*!
307 * @brief Gets an available pre-defined settings for wakeup/interrupt control.
308 *
309 * This function initializes the initial configuration structure with an available settings. The default values are:
310 * @code
311 * config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS;
312 * config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC;
313 * @endcode
314 * @param config Pointer to configuration structure.
315 */
316 void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config);
317
318 /*!
319 * @brief Enable PLU outputs wakeup/interrupt request.
320 *
321 * This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt
322 * request.
323 *
324 * Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN
325 * whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint
326 * config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the
327 * glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may
328 * increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is
329 * generated.
330 *
331 * @param base PLU peripheral base address.
332 * @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration).
333 * @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration)
334 */
335 void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config);
336
337 /*!
338 * @brief Latch an interrupt
339 *
340 * This function latches the interrupt and then it can be cleared with PLU_ClearLatchedInterrupt().
341 *
342 * Note: This mode is not compatible with use of the glitch filter. If this bit is set, the FILTER MODE should be set
343 * to kPLU_WAKEINT_FILTER_MODE_BYPASS (Bypass Mode) and PLU_CLKIN should be provided. If this bit is set, the
344 * wake-up/interrupt request will be set on the rising-edge of PLU_CLKIN whenever the raw wake-up/interrupt signal is
345 * high. The request must be cleared by software.
346 *
347 * @param base PLU peripheral base address.
348 */
PLU_LatchInterrupt(PLU_Type * base)349 static inline void PLU_LatchInterrupt(PLU_Type *base)
350 {
351 base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK;
352 }
353
354 /*!
355 * @brief Clear the latched interrupt
356 *
357 * This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt()
358 *
359 * Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit.
360 *
361 * @param base PLU peripheral base address.
362 */
363 void PLU_ClearLatchedInterrupt(PLU_Type *base);
364
365 /*! @}*/
366 #endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */
367
368 #if defined(__cplusplus)
369 }
370 #endif
371
372 /*! @}*/
373
374 #endif /* FSL_PLU_H_ */
375
