1 /* 2 * 3 * Copyright (c) 2017 Linaro Limited. 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_ 9 #define ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_ 10 11 #include <stdint.h> 12 13 #include <zephyr/device.h> 14 15 #include <stm32_ll_utils.h> 16 17 #if CONFIG_CLOCK_STM32_MCO1_SRC_NOCLOCK 18 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_NOCLOCK 19 #elif CONFIG_CLOCK_STM32_MCO1_SRC_EXT_HSE 20 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_EXT_HSE 21 #elif CONFIG_CLOCK_STM32_MCO1_SRC_LSE 22 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_LSE 23 #elif CONFIG_CLOCK_STM32_MCO1_SRC_HSE 24 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_HSE 25 #elif CONFIG_CLOCK_STM32_MCO1_SRC_LSI 26 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_LSI 27 #elif CONFIG_CLOCK_STM32_MCO1_SRC_MSI 28 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_MSI 29 #elif CONFIG_CLOCK_STM32_MCO1_SRC_HSI 30 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_HSI 31 #elif CONFIG_CLOCK_STM32_MCO1_SRC_HSI16 32 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_HSI 33 #elif CONFIG_CLOCK_STM32_MCO1_SRC_HSI48 34 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_HSI48 35 #elif CONFIG_CLOCK_STM32_MCO1_SRC_PLLCLK 36 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLLCLK 37 #elif CONFIG_CLOCK_STM32_MCO1_SRC_PLLCLK_DIV2 38 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 39 #elif CONFIG_CLOCK_STM32_MCO1_SRC_PLL2CLK 40 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLL2CLK 41 #elif CONFIG_CLOCK_STM32_MCO1_SRC_PLLI2SCLK 42 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLLI2SCLK 43 #elif CONFIG_CLOCK_STM32_MCO1_SRC_PLLI2SCLK_DIV2 44 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 45 #elif CONFIG_CLOCK_STM32_MCO1_SRC_SYSCLK 46 #define MCO1_SOURCE LL_RCC_MCO1SOURCE_SYSCLK 47 #endif 48 49 #if CONFIG_CLOCK_STM32_MCO2_SRC_SYSCLK 50 #define MCO2_SOURCE LL_RCC_MCO2SOURCE_SYSCLK 51 #elif CONFIG_CLOCK_STM32_MCO2_SRC_PLLI2S 52 #define MCO2_SOURCE LL_RCC_MCO2SOURCE_PLLI2S 53 #elif CONFIG_CLOCK_STM32_MCO2_SRC_HSE 54 #define MCO2_SOURCE LL_RCC_MCO2SOURCE_HSE 55 #elif CONFIG_CLOCK_STM32_MCO2_SRC_PLLCLK 56 #define MCO2_SOURCE LL_RCC_MCO2SOURCE_PLLCLK 57 #endif 58 59 /* Macros to fill up multiplication and division factors values */ 60 #define z_pllm(v) LL_RCC_PLLM_DIV_ ## v 61 #define pllm(v) z_pllm(v) 62 63 #define z_pllp(v) LL_RCC_PLLP_DIV_ ## v 64 #define pllp(v) z_pllp(v) 65 66 #define z_pllq(v) LL_RCC_PLLQ_DIV_ ## v 67 #define pllq(v) z_pllq(v) 68 69 #define z_pllr(v) LL_RCC_PLLR_DIV_ ## v 70 #define pllr(v) z_pllr(v) 71 72 #define z_plli2s_m(v) LL_RCC_PLLI2SM_DIV_ ## v 73 #define plli2sm(v) z_plli2s_m(v) 74 75 #define z_plli2s_r(v) LL_RCC_PLLI2SR_DIV_ ## v 76 #define plli2sr(v) z_plli2s_r(v) 77 78 #ifdef __cplusplus 79 extern "C" { 80 #endif 81 82 #if defined(STM32_PLL_ENABLED) 83 void config_pll_sysclock(void); 84 uint32_t get_pllout_frequency(void); 85 uint32_t get_pllsrc_frequency(void); 86 #endif 87 #if defined(STM32_PLL2_ENABLED) 88 void config_pll2(void); 89 #endif 90 #if defined(STM32_PLLI2S_ENABLED) 91 void config_plli2s(void); 92 #endif 93 void config_enable_default_clocks(void); 94 95 /* function exported to the soc power.c */ 96 int stm32_clock_control_init(const struct device *dev); 97 98 #ifdef __cplusplus 99 } 100 #endif 101 102 #endif /* ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_ */ 103
