1 /*
2  *
3  * Copyright (c) 2017 Linaro Limited.
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_
9 #define ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_
10 
11 #include <stdint.h>
12 
13 #include <zephyr/device.h>
14 
15 #include <stm32_ll_utils.h>
16 
17 /* Macros to fill up multiplication and division factors values */
18 #define z_pllm(v) LL_RCC_PLLM_DIV_ ## v
19 #define pllm(v) z_pllm(v)
20 
21 #define z_pllp(v) LL_RCC_PLLP_DIV_ ## v
22 #define pllp(v) z_pllp(v)
23 
24 #define z_pllq(v) LL_RCC_PLLQ_DIV_ ## v
25 #define pllq(v) z_pllq(v)
26 
27 #define z_pllr(v) LL_RCC_PLLR_DIV_ ## v
28 #define pllr(v) z_pllr(v)
29 
30 #define z_plli2s_m(v) LL_RCC_PLLI2SM_DIV_ ## v
31 #define plli2sm(v) z_plli2s_m(v)
32 
33 #define z_plli2s_r(v) LL_RCC_PLLI2SR_DIV_ ## v
34 #define plli2sr(v) z_plli2s_r(v)
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 #if defined(STM32_PLL_ENABLED)
41 void config_pll_sysclock(void);
42 uint32_t get_pllout_frequency(void);
43 uint32_t get_pllsrc_frequency(void);
44 #endif
45 #if defined(STM32_PLL2_ENABLED)
46 void config_pll2(void);
47 #endif
48 #if defined(STM32_PLLI2S_ENABLED)
49 void config_plli2s(void);
50 #endif
51 void config_enable_default_clocks(void);
52 
53 /* function exported to the soc power.c */
54 int stm32_clock_control_init(const struct device *dev);
55 
56 #ifdef __cplusplus
57 }
58 #endif
59 
60 #endif /* ZEPHYR_DRIVERS_CLOCK_CONTROL_STM32_LL_CLOCK_H_ */
61