1 /*
2 * Copyright (c) 2018 Arm Limited
3 * Copyright (c) 2019-2021, Cypress Semiconductor Corporation. All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17
18 #include <inttypes.h>
19
20 #include "cy_prot.h"
21 #include "cycfg.h"
22 #include "device_definition.h"
23 #include "driver_ppu.h"
24 #include "driver_smpu.h"
25 #include "pc_config.h"
26 #include "platform_description.h"
27 #include "region.h"
28 #include "region_defs.h"
29 #include "RTE_Device.h"
30 #include "target_cfg.h"
31 #include "tfm_plat_defs.h"
32 #include "tfm_spm_log.h"
33
34
35 /* The section names come from the scatter file */
36 REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
37 #ifdef BL2
38 REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
39 #endif /* BL2 */
40
41 const struct memory_region_limits memory_regions = {
42 .non_secure_code_start =
43 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
44 CYBL_HEADER_SIZE,
45
46 .non_secure_partition_base =
47 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base),
48
49 .non_secure_partition_limit =
50 (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
51 NS_PARTITION_SIZE - 1,
52 };
53
54
55 #ifdef BL2
56 REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
57 #endif /* BL2 */
58
59 /* UART RX and TX pins */
60 const cy_stc_gpio_pin_config_t CYBSP_UART_RX_config =
61 {
62 .outVal = 1,
63 .driveMode = CY_GPIO_DM_HIGHZ,
64 .hsiom = CYBSP_UART_RX_HSIOM,
65 .intEdge = CY_GPIO_INTR_DISABLE,
66 .intMask = 0UL,
67 .vtrip = CY_GPIO_VTRIP_CMOS,
68 .slewRate = CY_GPIO_SLEW_FAST,
69 .driveSel = CY_GPIO_DRIVE_1_2,
70 .vregEn = 0UL,
71 .ibufMode = 0UL,
72 .vtripSel = 0UL,
73 .vrefSel = 0UL,
74 .vohSel = 0UL,
75 };
76 const cy_stc_gpio_pin_config_t CYBSP_UART_TX_config =
77 {
78 .outVal = 1,
79 .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
80 .hsiom = CYBSP_UART_TX_HSIOM,
81 .intEdge = CY_GPIO_INTR_DISABLE,
82 .intMask = 0UL,
83 .vtrip = CY_GPIO_VTRIP_CMOS,
84 .slewRate = CY_GPIO_SLEW_FAST,
85 .driveSel = CY_GPIO_DRIVE_1_2,
86 .vregEn = 0UL,
87 .ibufMode = 0UL,
88 .vtripSel = 0UL,
89 .vrefSel = 0UL,
90 .vohSel = 0UL,
91 };
92
93 /* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field,
94 * otherwise the processor ignores the write.
95 */
96 #define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos))
97
98 struct platform_data_t tfm_peripheral_std_uart = {
99 SCB5_BASE,
100 SCB5_BASE + 0xFFF,
101 -1,
102 -1
103 };
104
105 struct platform_data_t tfm_peripheral_timer0 = {
106 TCPWM0_BASE,
107 TCPWM0_BASE + (sizeof(TCPWM_Type) - 1),
108 -1,
109 -1
110 };
111
enable_fault_handlers(void)112 void enable_fault_handlers(void)
113 {
114 /* Fault handles enable registers are not present in Cortex-M0+ */
115 }
116
system_reset_cfg(void)117 void system_reset_cfg(void)
118 {
119 uint32_t reg_value = SCB->AIRCR;
120
121 /* Clear SCB_AIRCR_VECTKEY value */
122 reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk);
123
124 /* Set Access Key (0x05FA must be written to this field) */
125 reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK);
126
127 SCB->AIRCR = reg_value;
128 }
129
130 extern void Cy_Platform_Init(void);
platform_init(void)131 void platform_init(void)
132 {
133 cy_en_sysclk_status_t clk_rc;
134 #if defined(TEST_NS_SLIH_IRQ) || defined(TEST_NS_FLIH_IRQ)
135 cy_en_sysint_status_t int_rc;
136 #endif
137
138 Cy_PDL_Init(CY_DEVICE_CFG);
139
140 init_cycfg_all();
141
142 /* UART clock */
143 clk_rc = Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
144 if (clk_rc != CY_SYSCLK_SUCCESS) {
145 SPMLOG_INFMSG("WARNING: Failed to configure UART clock\r\n");
146 }
147 clk_rc = Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 108U);
148 if (clk_rc != CY_SYSCLK_SUCCESS) {
149 SPMLOG_INFMSG("WARNING: Failed to configure UART clock\r\n");
150 }
151 clk_rc = Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
152 if (clk_rc != CY_SYSCLK_SUCCESS) {
153 SPMLOG_INFMSG("WARNING: Failed to configure UART clock\r\n");
154 }
155 clk_rc = Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
156 if (clk_rc != CY_SYSCLK_SUCCESS) {
157 SPMLOG_INFMSG("WARNING: Failed to configure UART clock\r\n");
158 }
159 /* Secure: TIMER0 clock */
160 clk_rc = Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 1U);
161 if (clk_rc != CY_SYSCLK_SUCCESS) {
162 SPMLOG_INFMSG("WARNING: Failed to configure timer0 clock\r\n");
163 }
164 /* Non-Secure: TIMER1 clock */
165 clk_rc = Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 1U);
166 if (clk_rc != CY_SYSCLK_SUCCESS) {
167 SPMLOG_INFMSG("WARNING: Failed to configure timer1 clock\r\n");
168 }
169
170 Cy_GPIO_Pin_Init(CYBSP_UART_RX_PORT, CYBSP_UART_RX_PIN, &CYBSP_UART_RX_config);
171 Cy_GPIO_Pin_Init(CYBSP_UART_TX_PORT, CYBSP_UART_TX_PIN, &CYBSP_UART_TX_config);
172
173 Cy_Platform_Init();
174
175 #if defined(TEST_NS_SLIH_IRQ) || defined(TEST_NS_FLIH_IRQ)
176 int_rc = Cy_SysInt_Init(&CY_TCPWM_NVIC_CFG_S, TFM_TIMER0_IRQ_Handler);
177 if (int_rc != CY_SYSINT_SUCCESS) {
178 SPMLOG_INFMSG("WARNING: Fail to initialize timer interrupt (IRQ TEST might fail)!\r\n");
179 }
180 #endif /* TEST_NS_SLIH_IRQ */
181
182 /* make sure CM4 is disabled */
183 if (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status()) {
184 Cy_SysDisableCM4();
185 }
186 }
187
nvic_interrupt_target_state_cfg(void)188 enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void)
189 {
190 return TFM_PLAT_ERR_SUCCESS;
191 }
192
nvic_interrupt_enable(void)193 enum tfm_plat_err_t nvic_interrupt_enable(void)
194 {
195 /* PPU and SMPU don't generate interrupts.
196 * USART and Flash drivers don't export an EnableInterrupt function.
197 * So there's nothing to do here.
198 */
199 return TFM_PLAT_ERR_SUCCESS;
200 }
201
bus_masters_cfg(void)202 enum tfm_plat_err_t bus_masters_cfg(void)
203 {
204 /* Cortex-M4 - PC=6 */
205 if (Cy_Prot_SetActivePC(CPUSS_MS_ID_CM4,
206 CY_PROT_HOST_DEFAULT) != CY_PROT_SUCCESS) {
207 return TFM_PLAT_ERR_SYSTEM_ERR;
208 }
209
210 /* Test Controller - PC=7 */
211 if (Cy_Prot_SetActivePC(CPUSS_MS_ID_TC, CY_PROT_TC) != CY_PROT_SUCCESS) {
212 return TFM_PLAT_ERR_SYSTEM_ERR;
213 }
214
215 /* Cortex-M0+ - PC=1 */
216 if (Cy_Prot_SetActivePC(CPUSS_MS_ID_CM0,
217 CY_PROT_SPM_DEFAULT) != CY_PROT_SUCCESS) {
218 return TFM_PLAT_ERR_SYSTEM_ERR;
219 }
220
221 return TFM_PLAT_ERR_SUCCESS;
222 }
223
224 const SMPU_Resources *smpu_init_table[] = {
225 #if RTE_SMPU0
226 &SMPU0_Resources,
227 #endif
228
229 #if RTE_SMPU1
230 &SMPU1_Resources,
231 #endif
232
233 #if RTE_SMPU2
234 &SMPU2_Resources,
235 #endif
236
237 #if RTE_SMPU3
238 &SMPU3_Resources,
239 #endif
240
241 #if RTE_SMPU4
242 &SMPU4_Resources,
243 #endif
244
245 #if RTE_SMPU5
246 &SMPU5_Resources,
247 #endif
248
249 #if RTE_SMPU6
250 &SMPU6_Resources,
251 #endif
252
253 #if RTE_SMPU7
254 &SMPU7_Resources,
255 #endif
256
257 #if RTE_SMPU8
258 &SMPU8_Resources,
259 #endif
260
261 #if RTE_SMPU9
262 &SMPU9_Resources,
263 #endif
264
265 #if RTE_SMPU10
266 &SMPU10_Resources,
267 #endif
268
269 #if RTE_SMPU11
270 &SMPU11_Resources,
271 #endif
272
273 #if RTE_SMPU12
274 &SMPU12_Resources,
275 #endif
276
277 #if RTE_SMPU13
278 &SMPU13_Resources,
279 #endif
280 };
281
smpu_init_cfg(void)282 enum tfm_plat_err_t smpu_init_cfg(void)
283 {
284 enum tfm_plat_err_t ret = TFM_PLAT_ERR_SUCCESS;
285
286 size_t n = sizeof(smpu_init_table)/sizeof(smpu_init_table[0]);
287
288 for (int i = (n - 1); i >= 0; i--)
289 {
290 if (SMPU_Configure(smpu_init_table[i]) != CY_PROT_SUCCESS) {
291 ret = TFM_PLAT_ERR_SYSTEM_ERR;
292 }
293 }
294
295 /* Now protect all unconfigured SMPUs */
296 if(protect_unconfigured_smpus() != CY_PROT_SUCCESS) {
297 ret = TFM_PLAT_ERR_SYSTEM_ERR;
298 }
299
300 __DSB();
301 __ISB();
302
303 return ret;
304 }
305
smpu_print_config(void)306 void smpu_print_config(void)
307 {
308 SPMLOG_INFMSG("\r\nSMPU config:\r\n");
309 SPMLOG_INFMSGVAL("memory_regions.non_secure_code_start = ",
310 memory_regions.non_secure_code_start);
311 SPMLOG_INFMSGVAL("memory_regions.non_secure_partition_base = ",
312 memory_regions.non_secure_partition_base);
313 SPMLOG_INFMSGVAL("memory_regions.non_secure_partition_limit = ",
314 memory_regions.non_secure_partition_limit);
315
316 size_t n = sizeof(smpu_init_table)/sizeof(smpu_init_table[0]);
317
318 for (int i = 0; i < n; i++)
319 {
320 SMPU_Print_Config(smpu_init_table[i]);
321 }
322 }
323
324 const PPU_Resources *ppu_init_table[] = {
325 #if RTE_MS_PPU_PR7
326 &PR7_PPU_Resources,
327 #endif
328 #if RTE_MS_PPU_PERI_MAIN
329 &PERI_MAIN_PPU_Resources,
330 #endif
331
332 #if RTE_MS_PPU_PERI_GR0_GROUP
333 &PERI_GR0_GROUP_PPU_Resources,
334 #endif
335
336 #if RTE_MS_PPU_PERI_GR1_GROUP
337 &PERI_GR1_GROUP_PPU_Resources,
338 #endif
339
340 #if RTE_MS_PPU_PERI_GR2_GROUP
341 &PERI_GR2_GROUP_PPU_Resources,
342 #endif
343
344 #if RTE_MS_PPU_PERI_GR3_GROUP
345 &PERI_GR3_GROUP_PPU_Resources,
346 #endif
347
348 #if RTE_MS_PPU_PERI_GR4_GROUP
349 &PERI_GR4_GROUP_PPU_Resources,
350 #endif
351
352 #if RTE_MS_PPU_PERI_GR6_GROUP
353 &PERI_GR6_GROUP_PPU_Resources,
354 #endif
355
356 #if RTE_MS_PPU_PERI_GR9_GROUP
357 &PERI_GR9_GROUP_PPU_Resources,
358 #endif
359
360 #if RTE_MS_PPU_PERI_GR10_GROUP
361 &PERI_GR10_GROUP_PPU_Resources,
362 #endif
363
364 #if RTE_MS_PPU_PERI_TR
365 &PERI_TR_PPU_Resources,
366 #endif
367
368 #if RTE_MS_PPU_CRYPTO_MAIN
369 &CRYPTO_MAIN_PPU_Resources,
370 #endif
371
372 #if RTE_MS_PPU_CRYPTO_CRYPTO
373 &CRYPTO_CRYPTO_PPU_Resources,
374 #endif
375
376 #if RTE_MS_PPU_CRYPTO_BOOT
377 &CRYPTO_BOOT_PPU_Resources,
378 #endif
379
380 #if RTE_MS_PPU_CRYPTO_KEY0
381 &CRYPTO_KEY0_PPU_Resources,
382 #endif
383
384 #if RTE_MS_PPU_CRYPTO_KEY1
385 &CRYPTO_KEY1_PPU_Resources,
386 #endif
387
388 #if RTE_MS_PPU_CRYPTO_BUF
389 &CRYPTO_BUF_PPU_Resources,
390 #endif
391
392 #if RTE_MS_PPU_CPUSS_CM4
393 &CPUSS_CM4_PPU_Resources,
394 #endif
395
396 #if RTE_MS_PPU_CPUSS_CM0
397 &CPUSS_CM0_PPU_Resources,
398 #endif
399
400 #if RTE_MS_PPU_CPUSS_BOOT
401 &CPUSS_BOOT_PPU_Resources,
402 #endif
403
404 #if RTE_MS_PPU_CPUSS_CM0_INT
405 &CPUSS_CM0_INT_PPU_Resources,
406 #endif
407
408 #if RTE_MS_PPU_CPUSS_CM4_INT
409 &CPUSS_CM4_INT_PPU_Resources,
410 #endif
411
412 #if RTE_MS_PPU_FAULT_STRUCT0_MAIN
413 &FAULT_STRUCT0_MAIN_PPU_Resources,
414 #endif
415
416 #if RTE_MS_PPU_FAULT_STRUCT1_MAIN
417 &FAULT_STRUCT1_MAIN_PPU_Resources,
418 #endif
419
420 #if RTE_MS_PPU_IPC_STRUCT0_IPC
421 &IPC_STRUCT0_IPC_PPU_Resources,
422 #endif
423
424 #if RTE_MS_PPU_IPC_STRUCT1_IPC
425 &IPC_STRUCT1_IPC_PPU_Resources,
426 #endif
427
428 #if RTE_MS_PPU_IPC_STRUCT2_IPC
429 &IPC_STRUCT2_IPC_PPU_Resources,
430 #endif
431
432 #if RTE_MS_PPU_IPC_STRUCT3_IPC
433 &IPC_STRUCT3_IPC_PPU_Resources,
434 #endif
435
436 #if RTE_MS_PPU_IPC_STRUCT4_IPC
437 &IPC_STRUCT4_IPC_PPU_Resources,
438 #endif
439
440 #if RTE_MS_PPU_IPC_STRUCT5_IPC
441 &IPC_STRUCT5_IPC_PPU_Resources,
442 #endif
443
444 #if RTE_MS_PPU_IPC_STRUCT6_IPC
445 &IPC_STRUCT6_IPC_PPU_Resources,
446 #endif
447
448 #if RTE_MS_PPU_IPC_STRUCT7_IPC
449 &IPC_STRUCT7_IPC_PPU_Resources,
450 #endif
451
452 #if RTE_MS_PPU_IPC_STRUCT8_IPC
453 &IPC_STRUCT8_IPC_PPU_Resources,
454 #endif
455
456 #if RTE_MS_PPU_IPC_STRUCT9_IPC
457 &IPC_STRUCT9_IPC_PPU_Resources,
458 #endif
459
460 #if RTE_MS_PPU_IPC_STRUCT10_IPC
461 &IPC_STRUCT10_IPC_PPU_Resources,
462 #endif
463
464 #if RTE_MS_PPU_IPC_STRUCT11_IPC
465 &IPC_STRUCT11_IPC_PPU_Resources,
466 #endif
467
468 #if RTE_MS_PPU_IPC_STRUCT12_IPC
469 &IPC_STRUCT12_IPC_PPU_Resources,
470 #endif
471
472 #if RTE_MS_PPU_IPC_STRUCT13_IPC
473 &IPC_STRUCT13_IPC_PPU_Resources,
474 #endif
475
476 #if RTE_MS_PPU_IPC_STRUCT14_IPC
477 &IPC_STRUCT14_IPC_PPU_Resources,
478 #endif
479
480 #if RTE_MS_PPU_IPC_STRUCT15_IPC
481 &IPC_STRUCT15_IPC_PPU_Resources,
482 #endif
483
484 #if RTE_MS_PPU_IPC_INTR_STRUCT0_INTR
485 &IPC_INTR_STRUCT0_INTR_PPU_Resources,
486 #endif
487
488 #if RTE_MS_PPU_IPC_INTR_STRUCT1_INTR
489 &IPC_INTR_STRUCT1_INTR_PPU_Resources,
490 #endif
491
492 #if RTE_MS_PPU_IPC_INTR_STRUCT2_INTR
493 &IPC_INTR_STRUCT2_INTR_PPU_Resources,
494 #endif
495
496 #if RTE_MS_PPU_IPC_INTR_STRUCT3_INTR
497 &IPC_INTR_STRUCT3_INTR_PPU_Resources,
498 #endif
499
500 #if RTE_MS_PPU_IPC_INTR_STRUCT4_INTR
501 &IPC_INTR_STRUCT4_INTR_PPU_Resources,
502 #endif
503
504 #if RTE_MS_PPU_IPC_INTR_STRUCT5_INTR
505 &IPC_INTR_STRUCT5_INTR_PPU_Resources,
506 #endif
507
508 #if RTE_MS_PPU_IPC_INTR_STRUCT6_INTR
509 &IPC_INTR_STRUCT6_INTR_PPU_Resources,
510 #endif
511
512 #if RTE_MS_PPU_IPC_INTR_STRUCT7_INTR
513 &IPC_INTR_STRUCT7_INTR_PPU_Resources,
514 #endif
515
516 #if RTE_MS_PPU_IPC_INTR_STRUCT8_INTR
517 &IPC_INTR_STRUCT8_INTR_PPU_Resources,
518 #endif
519
520 #if RTE_MS_PPU_IPC_INTR_STRUCT9_INTR
521 &IPC_INTR_STRUCT9_INTR_PPU_Resources,
522 #endif
523
524 #if RTE_MS_PPU_IPC_INTR_STRUCT10_INTR
525 &IPC_INTR_STRUCT10_INTR_PPU_Resources,
526 #endif
527
528 #if RTE_MS_PPU_IPC_INTR_STRUCT11_INTR
529 &IPC_INTR_STRUCT11_INTR_PPU_Resources,
530 #endif
531
532 #if RTE_MS_PPU_IPC_INTR_STRUCT12_INTR
533 &IPC_INTR_STRUCT12_INTR_PPU_Resources,
534 #endif
535
536 #if RTE_MS_PPU_IPC_INTR_STRUCT13_INTR
537 &IPC_INTR_STRUCT13_INTR_PPU_Resources,
538 #endif
539
540 #if RTE_MS_PPU_IPC_INTR_STRUCT14_INTR
541 &IPC_INTR_STRUCT14_INTR_PPU_Resources,
542 #endif
543
544 #if RTE_MS_PPU_IPC_INTR_STRUCT15_INTR
545 &IPC_INTR_STRUCT15_INTR_PPU_Resources,
546 #endif
547
548 #if RTE_MS_PPU_PROT_SMPU_MAIN
549 &PROT_SMPU_MAIN_PPU_Resources,
550 #endif
551
552 #if RTE_MS_PPU_PROT_MPU0_MAIN
553 &PROT_MPU0_MAIN_PPU_Resources,
554 #endif
555
556 #if RTE_MS_PPU_PROT_MPU5_MAIN
557 &PROT_MPU5_MAIN_PPU_Resources,
558 #endif
559
560 #if RTE_MS_PPU_PROT_MPU6_MAIN
561 &PROT_MPU6_MAIN_PPU_Resources,
562 #endif
563
564 #if RTE_MS_PPU_PROT_MPU14_MAIN
565 &PROT_MPU14_MAIN_PPU_Resources,
566 #endif
567
568 #if RTE_MS_PPU_PROT_MPU15_MAIN
569 &PROT_MPU15_MAIN_PPU_Resources,
570 #endif
571
572 #if RTE_MS_PPU_FLASHC_MAIN
573 &FLASHC_MAIN_PPU_Resources,
574 #endif
575
576 #if RTE_MS_PPU_FLASHC_CMD
577 &FLASHC_CMD_PPU_Resources,
578 #endif
579
580 #if RTE_MS_PPU_FLASHC_DFT
581 &FLASHC_DFT_PPU_Resources,
582 #endif
583
584 #if RTE_MS_PPU_FLASHC_CM0
585 &FLASHC_CM0_PPU_Resources,
586 #endif
587
588 #if RTE_MS_PPU_FLASHC_CM4
589 &FLASHC_CM4_PPU_Resources,
590 #endif
591
592 #if RTE_MS_PPU_FLASHC_CRYPTO
593 &FLASHC_CRYPTO_PPU_Resources,
594 #endif
595
596 #if RTE_MS_PPU_FLASHC_DW0
597 &FLASHC_DW0_PPU_Resources,
598 #endif
599
600 #if RTE_MS_PPU_FLASHC_DW1
601 &FLASHC_DW1_PPU_Resources,
602 #endif
603
604 #if RTE_MS_PPU_FLASHC_DMAC
605 &FLASHC_DMAC_PPU_Resources,
606 #endif
607
608 #if RTE_MS_PPU_FLASHC_EXT_MS0
609 &FLASHC_EXT_MS0_PPU_Resources,
610 #endif
611
612 #if RTE_MS_PPU_FLASHC_EXT_MS1
613 &FLASHC_EXT_MS1_PPU_Resources,
614 #endif
615
616 #if RTE_MS_PPU_FLASHC_FM
617 &FLASHC_FM_PPU_Resources,
618 #endif
619
620 #if RTE_MS_PPU_SRSS_MAIN1
621 &SRSS_MAIN1_PPU_Resources,
622 #endif
623
624 #if RTE_MS_PPU_SRSS_MAIN2
625 &SRSS_MAIN2_PPU_Resources,
626 #endif
627
628 #if RTE_MS_PPU_WDT
629 &WDT_PPU_Resources,
630 #endif
631
632 #if RTE_MS_PPU_MAIN
633 &MAIN_PPU_Resources,
634 #endif
635
636 #if RTE_MS_PPU_SRSS_MAIN3
637 &SRSS_MAIN3_PPU_Resources,
638 #endif
639
640 #if RTE_MS_PPU_SRSS_MAIN4
641 &SRSS_MAIN4_PPU_Resources,
642 #endif
643
644 #if RTE_MS_PPU_SRSS_MAIN5
645 &SRSS_MAIN5_PPU_Resources,
646 #endif
647
648 #if RTE_MS_PPU_SRSS_MAIN6
649 &SRSS_MAIN6_PPU_Resources,
650 #endif
651
652 #if RTE_MS_PPU_SRSS_MAIN7
653 &SRSS_MAIN7_PPU_Resources,
654 #endif
655
656 #if RTE_MS_PPU_BACKUP_BACKUP
657 &BACKUP_BACKUP_PPU_Resources,
658 #endif
659
660 #if RTE_MS_PPU_DW0_DW
661 &DW0_DW_PPU_Resources,
662 #endif
663
664 #if RTE_MS_PPU_DW1_DW
665 &DW1_DW_PPU_Resources,
666 #endif
667
668 #if RTE_MS_PPU_DW0_DW_CRC
669 &DW0_DW_CRC_PPU_Resources,
670 #endif
671
672 #if RTE_MS_PPU_DW1_DW_CRC
673 &DW1_DW_CRC_PPU_Resources,
674 #endif
675
676 #if RTE_MS_PPU_DW0_CH_STRUCT0_CH
677 &DW0_CH_STRUCT0_CH_PPU_Resources,
678 #endif
679
680 #if RTE_MS_PPU_DW0_CH_STRUCT1_CH
681 &DW0_CH_STRUCT1_CH_PPU_Resources,
682 #endif
683
684 #if RTE_MS_PPU_DW0_CH_STRUCT2_CH
685 &DW0_CH_STRUCT2_CH_PPU_Resources,
686 #endif
687
688 #if RTE_MS_PPU_DW0_CH_STRUCT3_CH
689 &DW0_CH_STRUCT3_CH_PPU_Resources,
690 #endif
691
692 #if RTE_MS_PPU_DW0_CH_STRUCT4_CH
693 &DW0_CH_STRUCT4_CH_PPU_Resources,
694 #endif
695
696 #if RTE_MS_PPU_DW0_CH_STRUCT5_CH
697 &DW0_CH_STRUCT5_CH_PPU_Resources,
698 #endif
699
700 #if RTE_MS_PPU_DW0_CH_STRUCT6_CH
701 &DW0_CH_STRUCT6_CH_PPU_Resources,
702 #endif
703
704 #if RTE_MS_PPU_DW0_CH_STRUCT7_CH
705 &DW0_CH_STRUCT7_CH_PPU_Resources,
706 #endif
707
708 #if RTE_MS_PPU_DW0_CH_STRUCT8_CH
709 &DW0_CH_STRUCT8_CH_PPU_Resources,
710 #endif
711
712 #if RTE_MS_PPU_DW0_CH_STRUCT9_CH
713 &DW0_CH_STRUCT9_CH_PPU_Resources,
714 #endif
715
716 #if RTE_MS_PPU_DW0_CH_STRUCT10_CH
717 &DW0_CH_STRUCT10_CH_PPU_Resources,
718 #endif
719
720 #if RTE_MS_PPU_DW0_CH_STRUCT11_CH
721 &DW0_CH_STRUCT11_CH_PPU_Resources,
722 #endif
723
724 #if RTE_MS_PPU_DW0_CH_STRUCT12_CH
725 &DW0_CH_STRUCT12_CH_PPU_Resources,
726 #endif
727
728 #if RTE_MS_PPU_DW0_CH_STRUCT13_CH
729 &DW0_CH_STRUCT13_CH_PPU_Resources,
730 #endif
731
732 #if RTE_MS_PPU_DW0_CH_STRUCT14_CH
733 &DW0_CH_STRUCT14_CH_PPU_Resources,
734 #endif
735
736 #if RTE_MS_PPU_DW0_CH_STRUCT15_CH
737 &DW0_CH_STRUCT15_CH_PPU_Resources,
738 #endif
739
740 #if RTE_MS_PPU_DW0_CH_STRUCT16_CH
741 &DW0_CH_STRUCT16_CH_PPU_Resources,
742 #endif
743
744 #if RTE_MS_PPU_DW0_CH_STRUCT17_CH
745 &DW0_CH_STRUCT17_CH_PPU_Resources,
746 #endif
747
748 #if RTE_MS_PPU_DW0_CH_STRUCT18_CH
749 &DW0_CH_STRUCT18_CH_PPU_Resources,
750 #endif
751
752 #if RTE_MS_PPU_DW0_CH_STRUCT19_CH
753 &DW0_CH_STRUCT19_CH_PPU_Resources,
754 #endif
755
756 #if RTE_MS_PPU_DW0_CH_STRUCT20_CH
757 &DW0_CH_STRUCT20_CH_PPU_Resources,
758 #endif
759
760 #if RTE_MS_PPU_DW0_CH_STRUCT21_CH
761 &DW0_CH_STRUCT21_CH_PPU_Resources,
762 #endif
763
764 #if RTE_MS_PPU_DW0_CH_STRUCT22_CH
765 &DW0_CH_STRUCT22_CH_PPU_Resources,
766 #endif
767
768 #if RTE_MS_PPU_DW0_CH_STRUCT23_CH
769 &DW0_CH_STRUCT23_CH_PPU_Resources,
770 #endif
771
772 #if RTE_MS_PPU_DW0_CH_STRUCT24_CH
773 &DW0_CH_STRUCT24_CH_PPU_Resources,
774 #endif
775
776 #if RTE_MS_PPU_DW0_CH_STRUCT25_CH
777 &DW0_CH_STRUCT25_CH_PPU_Resources,
778 #endif
779
780 #if RTE_MS_PPU_DW0_CH_STRUCT26_CH
781 &DW0_CH_STRUCT26_CH_PPU_Resources,
782 #endif
783
784 #if RTE_MS_PPU_DW0_CH_STRUCT27_CH
785 &DW0_CH_STRUCT27_CH_PPU_Resources,
786 #endif
787
788 #if RTE_MS_PPU_DW0_CH_STRUCT28_CH
789 &DW0_CH_STRUCT28_CH_PPU_Resources,
790 #endif
791
792 #if RTE_MS_PPU_DW1_CH_STRUCT0_CH
793 &DW1_CH_STRUCT0_CH_PPU_Resources,
794 #endif
795
796 #if RTE_MS_PPU_DW1_CH_STRUCT1_CH
797 &DW1_CH_STRUCT1_CH_PPU_Resources,
798 #endif
799
800 #if RTE_MS_PPU_DW1_CH_STRUCT2_CH
801 &DW1_CH_STRUCT2_CH_PPU_Resources,
802 #endif
803
804 #if RTE_MS_PPU_DW1_CH_STRUCT3_CH
805 &DW1_CH_STRUCT3_CH_PPU_Resources,
806 #endif
807
808 #if RTE_MS_PPU_DW1_CH_STRUCT4_CH
809 &DW1_CH_STRUCT4_CH_PPU_Resources,
810 #endif
811
812 #if RTE_MS_PPU_DW1_CH_STRUCT5_CH
813 &DW1_CH_STRUCT5_CH_PPU_Resources,
814 #endif
815
816 #if RTE_MS_PPU_DW1_CH_STRUCT6_CH
817 &DW1_CH_STRUCT6_CH_PPU_Resources,
818 #endif
819
820 #if RTE_MS_PPU_DW1_CH_STRUCT7_CH
821 &DW1_CH_STRUCT7_CH_PPU_Resources,
822 #endif
823
824 #if RTE_MS_PPU_DW1_CH_STRUCT8_CH
825 &DW1_CH_STRUCT8_CH_PPU_Resources,
826 #endif
827
828 #if RTE_MS_PPU_DW1_CH_STRUCT9_CH
829 &DW1_CH_STRUCT9_CH_PPU_Resources,
830 #endif
831
832 #if RTE_MS_PPU_DW1_CH_STRUCT10_CH
833 &DW1_CH_STRUCT10_CH_PPU_Resources,
834 #endif
835
836 #if RTE_MS_PPU_DW1_CH_STRUCT11_CH
837 &DW1_CH_STRUCT11_CH_PPU_Resources,
838 #endif
839
840 #if RTE_MS_PPU_DW1_CH_STRUCT12_CH
841 &DW1_CH_STRUCT12_CH_PPU_Resources,
842 #endif
843
844 #if RTE_MS_PPU_DW1_CH_STRUCT13_CH
845 &DW1_CH_STRUCT13_CH_PPU_Resources,
846 #endif
847
848 #if RTE_MS_PPU_DW1_CH_STRUCT14_CH
849 &DW1_CH_STRUCT14_CH_PPU_Resources,
850 #endif
851
852 #if RTE_MS_PPU_DW1_CH_STRUCT15_CH
853 &DW1_CH_STRUCT15_CH_PPU_Resources,
854 #endif
855
856 #if RTE_MS_PPU_DW1_CH_STRUCT16_CH
857 &DW1_CH_STRUCT16_CH_PPU_Resources,
858 #endif
859
860 #if RTE_MS_PPU_DW1_CH_STRUCT17_CH
861 &DW1_CH_STRUCT17_CH_PPU_Resources,
862 #endif
863
864 #if RTE_MS_PPU_DW1_CH_STRUCT18_CH
865 &DW1_CH_STRUCT18_CH_PPU_Resources,
866 #endif
867
868 #if RTE_MS_PPU_DW1_CH_STRUCT19_CH
869 &DW1_CH_STRUCT19_CH_PPU_Resources,
870 #endif
871
872 #if RTE_MS_PPU_DW1_CH_STRUCT20_CH
873 &DW1_CH_STRUCT20_CH_PPU_Resources,
874 #endif
875
876 #if RTE_MS_PPU_DW1_CH_STRUCT21_CH
877 &DW1_CH_STRUCT21_CH_PPU_Resources,
878 #endif
879
880 #if RTE_MS_PPU_DW1_CH_STRUCT22_CH
881 &DW1_CH_STRUCT22_CH_PPU_Resources,
882 #endif
883
884 #if RTE_MS_PPU_DW1_CH_STRUCT23_CH
885 &DW1_CH_STRUCT23_CH_PPU_Resources,
886 #endif
887
888 #if RTE_MS_PPU_DW1_CH_STRUCT24_CH
889 &DW1_CH_STRUCT24_CH_PPU_Resources,
890 #endif
891
892 #if RTE_MS_PPU_DW1_CH_STRUCT25_CH
893 &DW1_CH_STRUCT25_CH_PPU_Resources,
894 #endif
895
896 #if RTE_MS_PPU_DW1_CH_STRUCT26_CH
897 &DW1_CH_STRUCT26_CH_PPU_Resources,
898 #endif
899
900 #if RTE_MS_PPU_DW1_CH_STRUCT27_CH
901 &DW1_CH_STRUCT27_CH_PPU_Resources,
902 #endif
903
904 #if RTE_MS_PPU_DW1_CH_STRUCT28_CH
905 &DW1_CH_STRUCT28_CH_PPU_Resources,
906 #endif
907
908 #if RTE_MS_PPU_DMAC_TOP
909 &DMAC_TOP_PPU_Resources,
910 #endif
911
912 #if RTE_MS_PPU_DMAC_CH0_CH
913 &DMAC_CH0_CH_PPU_Resources,
914 #endif
915
916 #if RTE_MS_PPU_DMAC_CH1_CH
917 &DMAC_CH1_CH_PPU_Resources,
918 #endif
919
920 #if RTE_MS_PPU_DMAC_CH2_CH
921 &DMAC_CH2_CH_PPU_Resources,
922 #endif
923
924 #if RTE_MS_PPU_DMAC_CH3_CH
925 &DMAC_CH3_CH_PPU_Resources,
926 #endif
927
928 #if RTE_MS_PPU_EFUSE_CTL
929 &EFUSE_CTL_PPU_Resources,
930 #endif
931
932 #if RTE_MS_PPU_EFUSE_DATA
933 &EFUSE_DATA_PPU_Resources,
934 #endif
935
936 #if RTE_MS_PPU_PROFILE
937 &PROFILE_PPU_Resources,
938 #endif
939
940 #if RTE_MS_PPU_HSIOM_PRT0_PRT
941 &HSIOM_PRT0_PRT_PPU_Resources,
942 #endif
943
944 #if RTE_MS_PPU_HSIOM_PRT1_PRT
945 &HSIOM_PRT1_PRT_PPU_Resources,
946 #endif
947
948 #if RTE_MS_PPU_HSIOM_PRT2_PRT
949 &HSIOM_PRT2_PRT_PPU_Resources,
950 #endif
951
952 #if RTE_MS_PPU_HSIOM_PRT3_PRT
953 &HSIOM_PRT3_PRT_PPU_Resources,
954 #endif
955
956 #if RTE_MS_PPU_HSIOM_PRT4_PRT
957 &HSIOM_PRT4_PRT_PPU_Resources,
958 #endif
959
960 #if RTE_MS_PPU_HSIOM_PRT5_PRT
961 &HSIOM_PRT5_PRT_PPU_Resources,
962 #endif
963
964 #if RTE_MS_PPU_HSIOM_PRT6_PRT
965 &HSIOM_PRT6_PRT_PPU_Resources,
966 #endif
967
968 #if RTE_MS_PPU_HSIOM_PRT7_PRT
969 &HSIOM_PRT7_PRT_PPU_Resources,
970 #endif
971
972 #if RTE_MS_PPU_HSIOM_PRT8_PRT
973 &HSIOM_PRT8_PRT_PPU_Resources,
974 #endif
975
976 #if RTE_MS_PPU_HSIOM_PRT9_PRT
977 &HSIOM_PRT9_PRT_PPU_Resources,
978 #endif
979
980 #if RTE_MS_PPU_HSIOM_PRT10_PRT
981 &HSIOM_PRT10_PRT_PPU_Resources,
982 #endif
983
984 #if RTE_MS_PPU_HSIOM_PRT11_PRT
985 &HSIOM_PRT11_PRT_PPU_Resources,
986 #endif
987
988 #if RTE_MS_PPU_HSIOM_PRT12_PRT
989 &HSIOM_PRT12_PRT_PPU_Resources,
990 #endif
991
992 #if RTE_MS_PPU_HSIOM_PRT13_PRT
993 &HSIOM_PRT13_PRT_PPU_Resources,
994 #endif
995
996 #if RTE_MS_PPU_HSIOM_PRT14_PRT
997 &HSIOM_PRT14_PRT_PPU_Resources,
998 #endif
999
1000 #if RTE_MS_PPU_HSIOM_AMUX
1001 &HSIOM_AMUX_PPU_Resources,
1002 #endif
1003
1004 #if RTE_MS_PPU_HSIOM_MON
1005 &HSIOM_MON_PPU_Resources,
1006 #endif
1007
1008 #if RTE_MS_PPU_GPIO_PRT0_PRT
1009 &GPIO_PRT0_PRT_PPU_Resources,
1010 #endif
1011
1012 #if RTE_MS_PPU_GPIO_PRT1_PRT
1013 &GPIO_PRT1_PRT_PPU_Resources,
1014 #endif
1015
1016 #if RTE_MS_PPU_GPIO_PRT2_PRT
1017 &GPIO_PRT2_PRT_PPU_Resources,
1018 #endif
1019
1020 #if RTE_MS_PPU_GPIO_PRT3_PRT
1021 &GPIO_PRT3_PRT_PPU_Resources,
1022 #endif
1023
1024 #if RTE_MS_PPU_GPIO_PRT4_PRT
1025 &GPIO_PRT4_PRT_PPU_Resources,
1026 #endif
1027
1028 #if RTE_MS_PPU_GPIO_PRT5_PRT
1029 &GPIO_PRT5_PRT_PPU_Resources,
1030 #endif
1031
1032 #if RTE_MS_PPU_GPIO_PRT6_PRT
1033 &GPIO_PRT6_PRT_PPU_Resources,
1034 #endif
1035
1036 #if RTE_MS_PPU_GPIO_PRT7_PRT
1037 &GPIO_PRT7_PRT_PPU_Resources,
1038 #endif
1039
1040 #if RTE_MS_PPU_GPIO_PRT8_PRT
1041 &GPIO_PRT8_PRT_PPU_Resources,
1042 #endif
1043
1044 #if RTE_MS_PPU_GPIO_PRT9_PRT
1045 &GPIO_PRT9_PRT_PPU_Resources,
1046 #endif
1047
1048 #if RTE_MS_PPU_GPIO_PRT10_PRT
1049 &GPIO_PRT10_PRT_PPU_Resources,
1050 #endif
1051
1052 #if RTE_MS_PPU_GPIO_PRT11_PRT
1053 &GPIO_PRT11_PRT_PPU_Resources,
1054 #endif
1055
1056 #if RTE_MS_PPU_GPIO_PRT12_PRT
1057 &GPIO_PRT12_PRT_PPU_Resources,
1058 #endif
1059
1060 #if RTE_MS_PPU_GPIO_PRT13_PRT
1061 &GPIO_PRT13_PRT_PPU_Resources,
1062 #endif
1063
1064 #if RTE_MS_PPU_GPIO_PRT14_PRT
1065 &GPIO_PRT14_PRT_PPU_Resources,
1066 #endif
1067
1068 #if RTE_MS_PPU_GPIO_PRT0_CFG
1069 &GPIO_PRT0_CFG_PPU_Resources,
1070 #endif
1071
1072 #if RTE_MS_PPU_GPIO_PRT1_CFG
1073 &GPIO_PRT1_CFG_PPU_Resources,
1074 #endif
1075
1076 #if RTE_MS_PPU_GPIO_PRT2_CFG
1077 &GPIO_PRT2_CFG_PPU_Resources,
1078 #endif
1079
1080 #if RTE_MS_PPU_GPIO_PRT3_CFG
1081 &GPIO_PRT3_CFG_PPU_Resources,
1082 #endif
1083
1084 #if RTE_MS_PPU_GPIO_PRT4_CFG
1085 &GPIO_PRT4_CFG_PPU_Resources,
1086 #endif
1087
1088 #if RTE_MS_PPU_GPIO_PRT5_CFG
1089 &GPIO_PRT5_CFG_PPU_Resources,
1090 #endif
1091
1092 #if RTE_MS_PPU_GPIO_PRT6_CFG
1093 &GPIO_PRT6_CFG_PPU_Resources,
1094 #endif
1095
1096 #if RTE_MS_PPU_GPIO_PRT7_CFG
1097 &GPIO_PRT7_CFG_PPU_Resources,
1098 #endif
1099
1100 #if RTE_MS_PPU_GPIO_PRT8_CFG
1101 &GPIO_PRT8_CFG_PPU_Resources,
1102 #endif
1103
1104 #if RTE_MS_PPU_GPIO_PRT9_CFG
1105 &GPIO_PRT9_CFG_PPU_Resources,
1106 #endif
1107
1108 #if RTE_MS_PPU_GPIO_PRT10_CFG
1109 &GPIO_PRT10_CFG_PPU_Resources,
1110 #endif
1111
1112 #if RTE_MS_PPU_GPIO_PRT11_CFG
1113 &GPIO_PRT11_CFG_PPU_Resources,
1114 #endif
1115
1116 #if RTE_MS_PPU_GPIO_PRT12_CFG
1117 &GPIO_PRT12_CFG_PPU_Resources,
1118 #endif
1119
1120 #if RTE_MS_PPU_GPIO_PRT13_CFG
1121 &GPIO_PRT13_CFG_PPU_Resources,
1122 #endif
1123
1124 #if RTE_MS_PPU_GPIO_PRT14_CFG
1125 &GPIO_PRT14_CFG_PPU_Resources,
1126 #endif
1127
1128 #if RTE_MS_PPU_GPIO_GPIO
1129 &GPIO_GPIO_PPU_Resources,
1130 #endif
1131
1132 #if RTE_MS_PPU_GPIO_TEST
1133 &GPIO_TEST_PPU_Resources,
1134 #endif
1135
1136 #if RTE_MS_PPU_SMARTIO_PRT8_PRT
1137 &SMARTIO_PRT8_PRT_PPU_Resources,
1138 #endif
1139
1140 #if RTE_MS_PPU_SMARTIO_PRT9_PRT
1141 &SMARTIO_PRT9_PRT_PPU_Resources,
1142 #endif
1143
1144 #if RTE_MS_PPU_LPCOMP
1145 &LPCOMP_PPU_Resources,
1146 #endif
1147
1148 #if RTE_MS_PPU_CSD0
1149 &CSD0_PPU_Resources,
1150 #endif
1151
1152 #if RTE_MS_PPU_TCPWM0
1153 &TCPWM0_PPU_Resources,
1154 #endif
1155
1156 #if RTE_MS_PPU_TCPWM1
1157 &TCPWM1_PPU_Resources,
1158 #endif
1159
1160 #if RTE_MS_PPU_LCD0
1161 &LCD0_PPU_Resources,
1162 #endif
1163
1164 #if RTE_MS_PPU_USBFS0
1165 &USBFS0_PPU_Resources,
1166 #endif
1167
1168 #if RTE_MS_PPU_SMIF0
1169 &SMIF0_PPU_Resources,
1170 #endif
1171
1172 #if RTE_MS_PPU_SDHC0
1173 &SDHC0_PPU_Resources,
1174 #endif
1175
1176 #if RTE_MS_PPU_SDHC1
1177 &SDHC1_PPU_Resources,
1178 #endif
1179
1180 #if RTE_MS_PPU_SCB0
1181 &SCB0_PPU_Resources,
1182 #endif
1183
1184 #if RTE_MS_PPU_SCB1
1185 &SCB1_PPU_Resources,
1186 #endif
1187
1188 #if RTE_MS_PPU_SCB2
1189 &SCB2_PPU_Resources,
1190 #endif
1191
1192 #if RTE_MS_PPU_SCB3
1193 &SCB3_PPU_Resources,
1194 #endif
1195
1196 #if RTE_MS_PPU_SCB4
1197 &SCB4_PPU_Resources,
1198 #endif
1199
1200 #if RTE_MS_PPU_SCB5
1201 &SCB5_PPU_Resources,
1202 #endif
1203
1204 #if RTE_MS_PPU_SCB6
1205 &SCB6_PPU_Resources,
1206 #endif
1207
1208 #if RTE_MS_PPU_SCB7
1209 &SCB7_PPU_Resources,
1210 #endif
1211
1212 #if RTE_MS_PPU_SCB8
1213 &SCB8_PPU_Resources,
1214 #endif
1215
1216 #if RTE_MS_PPU_SCB9
1217 &SCB9_PPU_Resources,
1218 #endif
1219
1220 #if RTE_MS_PPU_SCB10
1221 &SCB10_PPU_Resources,
1222 #endif
1223
1224 #if RTE_MS_PPU_SCB11
1225 &SCB11_PPU_Resources,
1226 #endif
1227
1228 #if RTE_MS_PPU_SCB12
1229 &SCB12_PPU_Resources,
1230 #endif
1231
1232 #if RTE_MS_PPU_PDM0
1233 &PDM0_PPU_Resources,
1234 #endif
1235
1236 #if RTE_MS_PPU_I2S0
1237 &I2S0_PPU_Resources,
1238 #endif
1239
1240 #if RTE_MS_PPU_I2S1
1241 &I2S1_PPU_Resources,
1242 #endif
1243 };
1244
ppu_init_cfg(void)1245 enum tfm_plat_err_t ppu_init_cfg(void)
1246 {
1247 enum tfm_plat_err_t ret = TFM_PLAT_ERR_SUCCESS;
1248
1249 size_t n = sizeof(ppu_init_table)/sizeof(ppu_init_table[0]);
1250
1251 for (int i = 0; i < n; i++)
1252 {
1253 if (PPU_Configure(ppu_init_table[i]) != CY_PROT_SUCCESS) {
1254 ret = TFM_PLAT_ERR_SYSTEM_ERR;
1255 }
1256 }
1257
1258 __DSB();
1259 __ISB();
1260
1261 return ret;
1262 }
1263
