1 /* 2 * Copyright (c) 2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __INTEL_DAI_DRIVER_ALH_H__ 8 #define __INTEL_DAI_DRIVER_ALH_H__ 9 10 #include <stdint.h> 11 #include <zephyr/drivers/dai.h> 12 13 #include "alh_map.h" 14 15 #define DAI_NUM_ALH_BI_DIR_LINKS_GROUP 4 16 17 #define ALH_STREAM_OFFSET 0x4 18 19 #define IPC4_ALH_MAX_NUMBER_OF_GTW 16 20 #define IPC4_ALH_DAI_INDEX_OFFSET 7 21 22 /* copier id = (group id << 4) + codec id + IPC4_ALH_DAI_INDEX_OFFSET 23 * dai_index = (group id << 8) + codec id; 24 */ 25 #define IPC4_ALH_DAI_INDEX(x) ((((x) & 0xF0) << DAI_NUM_ALH_BI_DIR_LINKS_GROUP) + \ 26 (((x) & 0xF) - IPC4_ALH_DAI_INDEX_OFFSET)) 27 28 #define ALH_GPDMA_BURST_LENGTH 4 29 30 #define ALH_SET_BITS(b_hi, b_lo, x) \ 31 (((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo)) 32 #define ALHASCTL_OSEL(x) ALH_SET_BITS(25, 24, x) 33 34 #define dai_get_drvdata(dai) &dai->priv_data 35 #define dai_base(dai) dai->plat_data.base 36 37 #define DAI_DIR_PLAYBACK 0 38 #define DAI_DIR_CAPTURE 1 39 40 #define ALH_CHANNELS_DEFAULT 2 41 #define ALH_RATE_DEFAULT 48000 42 #define ALH_WORD_SIZE_DEFAULT 32 43 44 #if CONFIG_INTEL_ADSP_CAVS 45 #define ALH_TXDA_OFFSET 0x400 46 #define ALH_RXDA_OFFSET 0x500 47 #else 48 #define ALH_TXDA_OFFSET 0 49 #define ALH_RXDA_OFFSET 0x100 50 #endif 51 52 union dai_intel_ipc4_gateway_attributes { 53 /**< Raw value */ 54 uint32_t dw; 55 56 /**< Access to the fields */ 57 struct { 58 /**< Gateway data requested in low power memory. */ 59 uint32_t lp_buffer_alloc : 1; 60 61 /**< Gateway data requested in register file memory. */ 62 uint32_t alloc_from_reg_file : 1; 63 64 /**< Reserved field */ 65 uint32_t _rsvd : 30; 66 } bits; /**<< Bits */ 67 } __packed; 68 69 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */ 70 struct dai_intel_ipc3_alh_params { 71 uint32_t reserved0; 72 uint32_t stream_id; 73 uint32_t rate; 74 uint32_t channels; 75 76 /* reserved for future use */ 77 uint32_t reserved[13]; 78 } __packed; 79 80 struct ipc4_alh_multi_gtw_cfg { 81 /* Number of single channels (valid items in mapping array). */ 82 uint32_t count; 83 /* Single to multi aggregation mapping item. */ 84 struct { 85 /* Vindex of a single ALH channel aggregated. */ 86 uint32_t alh_id; 87 /* Channel mask */ 88 uint32_t channel_mask; 89 } mapping[IPC4_ALH_MAX_NUMBER_OF_GTW]; /* < Mapping items */ 90 } __packed; 91 92 struct dai_intel_ipc4_alh_configuration_blob { 93 union dai_intel_ipc4_gateway_attributes gtw_attributes; 94 struct ipc4_alh_multi_gtw_cfg alh_cfg; 95 } __packed; 96 97 struct dai_intel_alh_plat_data { 98 uint32_t base; 99 uint32_t fifo_depth[2]; 100 }; 101 102 struct dai_intel_alh_pdata { 103 struct dai_config config; 104 struct dai_properties props; 105 struct dai_intel_ipc3_alh_params params; 106 }; 107 108 struct dai_intel_alh { 109 uint32_t index; /**< index */ 110 struct dai_intel_alh_plat_data plat_data; 111 struct dai_intel_alh_pdata priv_data; 112 }; 113 114 /* Common data for all ALH DAI instances */ 115 struct dai_alh_global_shared { 116 struct k_spinlock lock; /**< locking mechanism */ 117 int sref; /**< simple ref counter, guarded by lock */ 118 }; 119 120 #endif 121
