1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: Configuration Register */ 14 /** Type of conf0 register 15 * a 16 */ 17 typedef union { 18 struct { 19 /** tx_rst : R/W; bitpos: [0]; default: 0; 20 * Write 1 then write 0 to this bit to reset decode state machine. 21 */ 22 uint32_t tx_rst:1; 23 /** rx_rst : R/W; bitpos: [1]; default: 0; 24 * Write 1 then write 0 to this bit to reset encode state machine. 25 */ 26 uint32_t rx_rst:1; 27 /** uart0_ce : R/W; bitpos: [2]; default: 0; 28 * Set this bit to link up HCI and UART0. 29 */ 30 uint32_t uart0_ce:1; 31 /** uart1_ce : R/W; bitpos: [3]; default: 0; 32 * Set this bit to link up HCI and UART1. 33 */ 34 uint32_t uart1_ce:1; 35 uint32_t reserved_4:1; 36 /** seper_en : R/W; bitpos: [5]; default: 1; 37 * Set this bit to separate the data frame using a special char. 38 */ 39 uint32_t seper_en:1; 40 /** head_en : R/W; bitpos: [6]; default: 1; 41 * Set this bit to encode the data packet with a formatting header. 42 */ 43 uint32_t head_en:1; 44 /** crc_rec_en : R/W; bitpos: [7]; default: 1; 45 * Set this bit to enable UHCI to receive the 16 bit CRC. 46 */ 47 uint32_t crc_rec_en:1; 48 /** uart_idle_eof_en : R/W; bitpos: [8]; default: 0; 49 * If this bit is set to 1 UHCI will end the payload receiving process when UART has 50 * been in idle state. 51 */ 52 uint32_t uart_idle_eof_en:1; 53 /** len_eof_en : R/W; bitpos: [9]; default: 1; 54 * If this bit is set to 1 UHCI decoder receiving payload data is end when the 55 * receiving byte count has reached the specified value. The value is payload length 56 * indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is 57 * configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder 58 * receiving payload data is end when 0xc0 is received. 59 */ 60 uint32_t len_eof_en:1; 61 /** encode_crc_en : R/W; bitpos: [10]; default: 1; 62 * Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to 63 * end of the payload. 64 */ 65 uint32_t encode_crc_en:1; 66 /** clk_en : R/W; bitpos: [11]; default: 0; 67 * 1'b1: Force clock on for register. 1'b0: Support clock only when application writes 68 * registers. 69 */ 70 uint32_t clk_en:1; 71 /** uart_rx_brk_eof_en : R/W; bitpos: [12]; default: 0; 72 * If this bit is set to 1 UHCI will end payload receive process when NULL frame is 73 * received by UART. 74 */ 75 uint32_t uart_rx_brk_eof_en:1; 76 uint32_t reserved_13:19; 77 }; 78 uint32_t val; 79 } uhci_conf0_reg_t; 80 81 /** Type of conf1 register 82 * a 83 */ 84 typedef union { 85 struct { 86 /** check_sum_en : R/W; bitpos: [0]; default: 1; 87 * a 88 */ 89 uint32_t check_sum_en:1; 90 /** check_seq_en : R/W; bitpos: [1]; default: 1; 91 * a 92 */ 93 uint32_t check_seq_en:1; 94 /** crc_disable : R/W; bitpos: [2]; default: 0; 95 * a 96 */ 97 uint32_t crc_disable:1; 98 /** save_head : R/W; bitpos: [3]; default: 0; 99 * a 100 */ 101 uint32_t save_head:1; 102 /** tx_check_sum_re : R/W; bitpos: [4]; default: 1; 103 * a 104 */ 105 uint32_t tx_check_sum_re:1; 106 /** tx_ack_num_re : R/W; bitpos: [5]; default: 1; 107 * a 108 */ 109 uint32_t tx_ack_num_re:1; 110 uint32_t reserved_6:1; 111 /** wait_sw_start : R/W; bitpos: [7]; default: 0; 112 * a 113 */ 114 uint32_t wait_sw_start:1; 115 /** sw_start : WT; bitpos: [8]; default: 0; 116 * a 117 */ 118 uint32_t sw_start:1; 119 uint32_t reserved_9:23; 120 }; 121 uint32_t val; 122 } uhci_conf1_reg_t; 123 124 /** Type of escape_conf register 125 * a 126 */ 127 typedef union { 128 struct { 129 /** tx_c0_esc_en : R/W; bitpos: [0]; default: 1; 130 * a 131 */ 132 uint32_t tx_c0_esc_en:1; 133 /** tx_db_esc_en : R/W; bitpos: [1]; default: 1; 134 * a 135 */ 136 uint32_t tx_db_esc_en:1; 137 /** tx_11_esc_en : R/W; bitpos: [2]; default: 0; 138 * a 139 */ 140 uint32_t tx_11_esc_en:1; 141 /** tx_13_esc_en : R/W; bitpos: [3]; default: 0; 142 * a 143 */ 144 uint32_t tx_13_esc_en:1; 145 /** rx_c0_esc_en : R/W; bitpos: [4]; default: 1; 146 * a 147 */ 148 uint32_t rx_c0_esc_en:1; 149 /** rx_db_esc_en : R/W; bitpos: [5]; default: 1; 150 * a 151 */ 152 uint32_t rx_db_esc_en:1; 153 /** rx_11_esc_en : R/W; bitpos: [6]; default: 0; 154 * a 155 */ 156 uint32_t rx_11_esc_en:1; 157 /** rx_13_esc_en : R/W; bitpos: [7]; default: 0; 158 * a 159 */ 160 uint32_t rx_13_esc_en:1; 161 uint32_t reserved_8:24; 162 }; 163 uint32_t val; 164 } uhci_escape_conf_reg_t; 165 166 /** Type of hung_conf register 167 * a 168 */ 169 typedef union { 170 struct { 171 /** txfifo_timeout : R/W; bitpos: [7:0]; default: 16; 172 * a 173 */ 174 uint32_t txfifo_timeout:8; 175 /** txfifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; 176 * a 177 */ 178 uint32_t txfifo_timeout_shift:3; 179 /** txfifo_timeout_ena : R/W; bitpos: [11]; default: 1; 180 * a 181 */ 182 uint32_t txfifo_timeout_ena:1; 183 /** rxfifo_timeout : R/W; bitpos: [19:12]; default: 16; 184 * a 185 */ 186 uint32_t rxfifo_timeout:8; 187 /** rxfifo_timeout_shift : R/W; bitpos: [22:20]; default: 0; 188 * a 189 */ 190 uint32_t rxfifo_timeout_shift:3; 191 /** rxfifo_timeout_ena : R/W; bitpos: [23]; default: 1; 192 * a 193 */ 194 uint32_t rxfifo_timeout_ena:1; 195 uint32_t reserved_24:8; 196 }; 197 uint32_t val; 198 } uhci_hung_conf_reg_t; 199 200 /** Type of ack_num register 201 * a 202 */ 203 typedef union { 204 struct { 205 /** ack_num : R/W; bitpos: [2:0]; default: 0; 206 * a 207 */ 208 uint32_t ack_num:3; 209 /** ack_num_load : WT; bitpos: [3]; default: 0; 210 * a 211 */ 212 uint32_t ack_num_load:1; 213 uint32_t reserved_4:28; 214 }; 215 uint32_t val; 216 } uhci_ack_num_reg_t; 217 218 /** Type of quick_sent register 219 * a 220 */ 221 typedef union { 222 struct { 223 /** single_send_num : R/W; bitpos: [2:0]; default: 0; 224 * a 225 */ 226 uint32_t single_send_num:3; 227 /** single_send_en : WT; bitpos: [3]; default: 0; 228 * a 229 */ 230 uint32_t single_send_en:1; 231 /** always_send_num : R/W; bitpos: [6:4]; default: 0; 232 * a 233 */ 234 uint32_t always_send_num:3; 235 /** always_send_en : R/W; bitpos: [7]; default: 0; 236 * a 237 */ 238 uint32_t always_send_en:1; 239 uint32_t reserved_8:24; 240 }; 241 uint32_t val; 242 } uhci_quick_sent_reg_t; 243 244 /** Type of reg_qn_word0 register 245 * a 246 */ 247 typedef union { 248 struct { 249 /** send_word0 : R/W; bitpos: [31:0]; default: 0; 250 * a 251 */ 252 uint32_t send_word0:32; 253 }; 254 uint32_t val; 255 } uhci_reg_qn_word0_reg_t; 256 257 /** Type of reg_qn_word1 register 258 * a 259 */ 260 typedef union { 261 struct { 262 /** send_word1 : R/W; bitpos: [31:0]; default: 0; 263 * a 264 */ 265 uint32_t send_word1:32; 266 }; 267 uint32_t val; 268 } uhci_reg_qn_word1_reg_t; 269 270 /** Type of esc_conf0 register 271 * a 272 */ 273 typedef union { 274 struct { 275 /** seper_char : R/W; bitpos: [7:0]; default: 192; 276 * a 277 */ 278 uint32_t seper_char:8; 279 /** seper_esc_char0 : R/W; bitpos: [15:8]; default: 219; 280 * a 281 */ 282 uint32_t seper_esc_char0:8; 283 /** seper_esc_char1 : R/W; bitpos: [23:16]; default: 220; 284 * a 285 */ 286 uint32_t seper_esc_char1:8; 287 uint32_t reserved_24:8; 288 }; 289 uint32_t val; 290 } uhci_esc_conf0_reg_t; 291 292 /** Type of esc_conf1 register 293 * a 294 */ 295 typedef union { 296 struct { 297 /** esc_seq0 : R/W; bitpos: [7:0]; default: 219; 298 * a 299 */ 300 uint32_t esc_seq0:8; 301 /** esc_seq0_char0 : R/W; bitpos: [15:8]; default: 219; 302 * a 303 */ 304 uint32_t esc_seq0_char0:8; 305 /** esc_seq0_char1 : R/W; bitpos: [23:16]; default: 221; 306 * a 307 */ 308 uint32_t esc_seq0_char1:8; 309 uint32_t reserved_24:8; 310 }; 311 uint32_t val; 312 } uhci_esc_conf1_reg_t; 313 314 /** Type of esc_conf2 register 315 * a 316 */ 317 typedef union { 318 struct { 319 /** esc_seq1 : R/W; bitpos: [7:0]; default: 17; 320 * a 321 */ 322 uint32_t esc_seq1:8; 323 /** esc_seq1_char0 : R/W; bitpos: [15:8]; default: 219; 324 * a 325 */ 326 uint32_t esc_seq1_char0:8; 327 /** esc_seq1_char1 : R/W; bitpos: [23:16]; default: 222; 328 * a 329 */ 330 uint32_t esc_seq1_char1:8; 331 uint32_t reserved_24:8; 332 }; 333 uint32_t val; 334 } uhci_esc_conf2_reg_t; 335 336 /** Type of esc_conf3 register 337 * a 338 */ 339 typedef union { 340 struct { 341 /** esc_seq2 : R/W; bitpos: [7:0]; default: 19; 342 * a 343 */ 344 uint32_t esc_seq2:8; 345 /** esc_seq2_char0 : R/W; bitpos: [15:8]; default: 219; 346 * a 347 */ 348 uint32_t esc_seq2_char0:8; 349 /** esc_seq2_char1 : R/W; bitpos: [23:16]; default: 223; 350 * a 351 */ 352 uint32_t esc_seq2_char1:8; 353 uint32_t reserved_24:8; 354 }; 355 uint32_t val; 356 } uhci_esc_conf3_reg_t; 357 358 /** Type of pkt_thres register 359 * a 360 */ 361 typedef union { 362 struct { 363 /** pkt_thrs : R/W; bitpos: [12:0]; default: 128; 364 * a 365 */ 366 uint32_t pkt_thrs:13; 367 uint32_t reserved_13:19; 368 }; 369 uint32_t val; 370 } uhci_pkt_thres_reg_t; 371 372 373 /** Group: Interrupt Register */ 374 /** Type of int_raw register 375 * a 376 */ 377 typedef union { 378 struct { 379 /** rx_start_int_raw : R/WTC/SS; bitpos: [0]; default: 0; 380 * a 381 */ 382 uint32_t rx_start_int_raw:1; 383 /** tx_start_int_raw : R/WTC/SS; bitpos: [1]; default: 0; 384 * a 385 */ 386 uint32_t tx_start_int_raw:1; 387 /** rx_hung_int_raw : R/WTC/SS; bitpos: [2]; default: 0; 388 * a 389 */ 390 uint32_t rx_hung_int_raw:1; 391 /** tx_hung_int_raw : R/WTC/SS; bitpos: [3]; default: 0; 392 * a 393 */ 394 uint32_t tx_hung_int_raw:1; 395 /** send_s_reg_q_int_raw : R/WTC/SS; bitpos: [4]; default: 0; 396 * a 397 */ 398 uint32_t send_s_reg_q_int_raw:1; 399 /** send_a_reg_q_int_raw : R/WTC/SS; bitpos: [5]; default: 0; 400 * a 401 */ 402 uint32_t send_a_reg_q_int_raw:1; 403 /** out_eof_int_raw : R/WTC/SS; bitpos: [6]; default: 0; 404 * This is the interrupt raw bit. Triggered when there are some errors in EOF in the 405 */ 406 uint32_t out_eof_int_raw:1; 407 /** app_ctrl0_int_raw : R/W; bitpos: [7]; default: 0; 408 * Soft control int raw bit. 409 */ 410 uint32_t app_ctrl0_int_raw:1; 411 /** app_ctrl1_int_raw : R/W; bitpos: [8]; default: 0; 412 * Soft control int raw bit. 413 */ 414 uint32_t app_ctrl1_int_raw:1; 415 uint32_t reserved_9:23; 416 }; 417 uint32_t val; 418 } uhci_int_raw_reg_t; 419 420 /** Type of int_st register 421 * a 422 */ 423 typedef union { 424 struct { 425 /** rx_start_int_st : RO; bitpos: [0]; default: 0; 426 * a 427 */ 428 uint32_t rx_start_int_st:1; 429 /** tx_start_int_st : RO; bitpos: [1]; default: 0; 430 * a 431 */ 432 uint32_t tx_start_int_st:1; 433 /** rx_hung_int_st : RO; bitpos: [2]; default: 0; 434 * a 435 */ 436 uint32_t rx_hung_int_st:1; 437 /** tx_hung_int_st : RO; bitpos: [3]; default: 0; 438 * a 439 */ 440 uint32_t tx_hung_int_st:1; 441 /** send_s_reg_q_int_st : RO; bitpos: [4]; default: 0; 442 * a 443 */ 444 uint32_t send_s_reg_q_int_st:1; 445 /** send_a_reg_q_int_st : RO; bitpos: [5]; default: 0; 446 * a 447 */ 448 uint32_t send_a_reg_q_int_st:1; 449 /** outlink_eof_err_int_st : RO; bitpos: [6]; default: 0; 450 * a 451 */ 452 uint32_t outlink_eof_err_int_st:1; 453 /** app_ctrl0_int_st : RO; bitpos: [7]; default: 0; 454 * a 455 */ 456 uint32_t app_ctrl0_int_st:1; 457 /** app_ctrl1_int_st : RO; bitpos: [8]; default: 0; 458 * a 459 */ 460 uint32_t app_ctrl1_int_st:1; 461 uint32_t reserved_9:23; 462 }; 463 uint32_t val; 464 } uhci_int_st_reg_t; 465 466 /** Type of int_ena register 467 * a 468 */ 469 typedef union { 470 struct { 471 /** rx_start_int_ena : R/W; bitpos: [0]; default: 0; 472 * a 473 */ 474 uint32_t rx_start_int_ena:1; 475 /** tx_start_int_ena : R/W; bitpos: [1]; default: 0; 476 * a 477 */ 478 uint32_t tx_start_int_ena:1; 479 /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0; 480 * a 481 */ 482 uint32_t rx_hung_int_ena:1; 483 /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0; 484 * a 485 */ 486 uint32_t tx_hung_int_ena:1; 487 /** send_s_reg_q_int_ena : R/W; bitpos: [4]; default: 0; 488 * a 489 */ 490 uint32_t send_s_reg_q_int_ena:1; 491 /** send_a_reg_q_int_ena : R/W; bitpos: [5]; default: 0; 492 * a 493 */ 494 uint32_t send_a_reg_q_int_ena:1; 495 /** outlink_eof_err_int_ena : R/W; bitpos: [6]; default: 0; 496 * a 497 */ 498 uint32_t outlink_eof_err_int_ena:1; 499 /** app_ctrl0_int_ena : R/W; bitpos: [7]; default: 0; 500 * a 501 */ 502 uint32_t app_ctrl0_int_ena:1; 503 /** app_ctrl1_int_ena : R/W; bitpos: [8]; default: 0; 504 * a 505 */ 506 uint32_t app_ctrl1_int_ena:1; 507 uint32_t reserved_9:23; 508 }; 509 uint32_t val; 510 } uhci_int_ena_reg_t; 511 512 /** Type of int_clr register 513 * a 514 */ 515 typedef union { 516 struct { 517 /** rx_start_int_clr : WT; bitpos: [0]; default: 0; 518 * a 519 */ 520 uint32_t rx_start_int_clr:1; 521 /** tx_start_int_clr : WT; bitpos: [1]; default: 0; 522 * a 523 */ 524 uint32_t tx_start_int_clr:1; 525 /** rx_hung_int_clr : WT; bitpos: [2]; default: 0; 526 * a 527 */ 528 uint32_t rx_hung_int_clr:1; 529 /** tx_hung_int_clr : WT; bitpos: [3]; default: 0; 530 * a 531 */ 532 uint32_t tx_hung_int_clr:1; 533 /** send_s_reg_q_int_clr : WT; bitpos: [4]; default: 0; 534 * a 535 */ 536 uint32_t send_s_reg_q_int_clr:1; 537 /** send_a_reg_q_int_clr : WT; bitpos: [5]; default: 0; 538 * a 539 */ 540 uint32_t send_a_reg_q_int_clr:1; 541 /** outlink_eof_err_int_clr : WT; bitpos: [6]; default: 0; 542 * a 543 */ 544 uint32_t outlink_eof_err_int_clr:1; 545 /** app_ctrl0_int_clr : WT; bitpos: [7]; default: 0; 546 * a 547 */ 548 uint32_t app_ctrl0_int_clr:1; 549 /** app_ctrl1_int_clr : WT; bitpos: [8]; default: 0; 550 * a 551 */ 552 uint32_t app_ctrl1_int_clr:1; 553 uint32_t reserved_9:23; 554 }; 555 uint32_t val; 556 } uhci_int_clr_reg_t; 557 558 559 /** Group: UHCI Status Register */ 560 /** Type of state0 register 561 * a 562 */ 563 typedef union { 564 struct { 565 /** rx_err_cause : RO; bitpos: [2:0]; default: 0; 566 * a 567 */ 568 uint32_t rx_err_cause:3; 569 /** decode_state : RO; bitpos: [5:3]; default: 0; 570 * a 571 */ 572 uint32_t decode_state:3; 573 uint32_t reserved_6:26; 574 }; 575 uint32_t val; 576 } uhci_state0_reg_t; 577 578 /** Type of state1 register 579 * a 580 */ 581 typedef union { 582 struct { 583 /** encode_state : RO; bitpos: [2:0]; default: 0; 584 * a 585 */ 586 uint32_t encode_state:3; 587 uint32_t reserved_3:29; 588 }; 589 uint32_t val; 590 } uhci_state1_reg_t; 591 592 /** Type of rx_head register 593 * a 594 */ 595 typedef union { 596 struct { 597 /** rx_head : RO; bitpos: [31:0]; default: 0; 598 * a 599 */ 600 uint32_t rx_head:32; 601 }; 602 uint32_t val; 603 } uhci_rx_head_reg_t; 604 605 606 /** Group: Version Register */ 607 /** Type of date register 608 * a 609 */ 610 typedef union { 611 struct { 612 /** date : R/W; bitpos: [31:0]; default: 35655936; 613 * a 614 */ 615 uint32_t date:32; 616 }; 617 uint32_t val; 618 } uhci_date_reg_t; 619 620 621 typedef struct uhci_dev_s { 622 volatile uhci_conf0_reg_t conf0; 623 volatile uhci_int_raw_reg_t int_raw; 624 volatile uhci_int_st_reg_t int_st; 625 volatile uhci_int_ena_reg_t int_ena; 626 volatile uhci_int_clr_reg_t int_clr; 627 volatile uhci_conf1_reg_t conf1; 628 volatile uhci_state0_reg_t state0; 629 volatile uhci_state1_reg_t state1; 630 volatile uhci_escape_conf_reg_t escape_conf; 631 volatile uhci_hung_conf_reg_t hung_conf; 632 volatile uhci_ack_num_reg_t ack_num; 633 volatile uhci_rx_head_reg_t rx_head; 634 volatile uhci_quick_sent_reg_t quick_sent; 635 volatile struct { 636 uhci_reg_qn_word0_reg_t word0; 637 uhci_reg_qn_word1_reg_t word1; 638 } q_data[7]; 639 volatile uhci_esc_conf0_reg_t esc_conf0; 640 volatile uhci_esc_conf1_reg_t esc_conf1; 641 volatile uhci_esc_conf2_reg_t esc_conf2; 642 volatile uhci_esc_conf3_reg_t esc_conf3; 643 volatile uhci_pkt_thres_reg_t pkt_thres; 644 volatile uhci_date_reg_t date; 645 } uhci_dev_t; 646 647 extern uhci_dev_t UHCI0; 648 649 #ifndef __cplusplus 650 _Static_assert(sizeof(uhci_dev_t) == 0x84, "Invalid size of uhci_dev_t structure"); 651 #endif 652 653 #ifdef __cplusplus 654 } 655 #endif 656
