1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_PIO_H 9 #define _HARDWARE_STRUCTS_PIO_H 10 11 /** 12 * \file rp2350/pio.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/pio.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pio 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/pio.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV 28 // Clock divisor register for state machine 0 + 29 // 0xffff0000 [31:16] INT (0x0001) Effective frequency is sysclk/(int + frac/256) 30 // 0x0000ff00 [15:8] FRAC (0x00) Fractional part of clock divisor 31 io_rw_32 clkdiv; 32 33 _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL 34 // Execution/behavioural settings for state machine 0 35 // 0x80000000 [31] EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,... 36 // 0x40000000 [30] SIDE_EN (0) If 1, the MSB of the Delay/Side-set instruction field is... 37 // 0x20000000 [29] SIDE_PINDIR (0) If 1, side-set data is asserted to pin directions,... 38 // 0x1f000000 [28:24] JMP_PIN (0x00) The GPIO number to use as condition for JMP PIN 39 // 0x00f80000 [23:19] OUT_EN_SEL (0x00) Which data bit to use for inline OUT enable 40 // 0x00040000 [18] INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable + 41 // 0x00020000 [17] OUT_STICKY (0) Continuously assert the most recent OUT/SET to the pins 42 // 0x0001f000 [16:12] WRAP_TOP (0x1f) After reaching this address, execution is wrapped to wrap_bottom 43 // 0x00000f80 [11:7] WRAP_BOTTOM (0x00) After reaching wrap_top, execution is wrapped to this address 44 // 0x00000060 [6:5] STATUS_SEL (0x0) Comparison used for the MOV x, STATUS instruction 45 // 0x0000001f [4:0] STATUS_N (0x00) Comparison level or IRQ index for the MOV x, STATUS instruction 46 io_rw_32 execctrl; 47 48 _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL 49 // Control behaviour of the input/output shift registers for state machine 0 50 // 0x80000000 [31] FJOIN_RX (0) When 1, RX FIFO steals the TX FIFO's storage, and... 51 // 0x40000000 [30] FJOIN_TX (0) When 1, TX FIFO steals the RX FIFO's storage, and... 52 // 0x3e000000 [29:25] PULL_THRESH (0x00) Number of bits shifted out of OSR before autopull, or... 53 // 0x01f00000 [24:20] PUSH_THRESH (0x00) Number of bits shifted into ISR before autopush, or... 54 // 0x00080000 [19] OUT_SHIFTDIR (1) 1 = shift out of output shift register to right 55 // 0x00040000 [18] IN_SHIFTDIR (1) 1 = shift input shift register to right (data enters from left) 56 // 0x00020000 [17] AUTOPULL (0) Pull automatically when the output shift register is emptied, i 57 // 0x00010000 [16] AUTOPUSH (0) Push automatically when the input shift register is filled, i 58 // 0x00008000 [15] FJOIN_RX_PUT (0) If 1, disable this state machine's RX FIFO, make its... 59 // 0x00004000 [14] FJOIN_RX_GET (0) If 1, disable this state machine's RX FIFO, make its... 60 // 0x0000001f [4:0] IN_COUNT (0x00) Set the number of pins which are not masked to 0 when... 61 io_rw_32 shiftctrl; 62 63 _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR 64 // Current instruction address of state machine 0 65 // 0x0000001f [4:0] SM0_ADDR (0x00) 66 io_ro_32 addr; 67 68 _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR 69 // Read to see the instruction currently addressed by state machine 0's program counter + 70 // 0x0000ffff [15:0] SM0_INSTR (-) 71 io_rw_32 instr; 72 73 _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL 74 // State machine pin control 75 // 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction... 76 // 0x1c000000 [28:26] SET_COUNT (0x5) The number of pins asserted by a SET 77 // 0x03f00000 [25:20] OUT_COUNT (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS... 78 // 0x000f8000 [19:15] IN_BASE (0x00) The pin which is mapped to the least-significant bit of... 79 // 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a... 80 // 0x000003e0 [9:5] SET_BASE (0x00) The lowest-numbered pin that will be affected by a SET... 81 // 0x0000001f [4:0] OUT_BASE (0x00) The lowest-numbered pin that will be affected by an OUT... 82 io_rw_32 pinctrl; 83 } pio_sm_hw_t; 84 85 typedef struct { 86 _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE 87 // Interrupt Enable for irq0 88 // 0x00008000 [15] SM7 (0) 89 // 0x00004000 [14] SM6 (0) 90 // 0x00002000 [13] SM5 (0) 91 // 0x00001000 [12] SM4 (0) 92 // 0x00000800 [11] SM3 (0) 93 // 0x00000400 [10] SM2 (0) 94 // 0x00000200 [9] SM1 (0) 95 // 0x00000100 [8] SM0 (0) 96 // 0x00000080 [7] SM3_TXNFULL (0) 97 // 0x00000040 [6] SM2_TXNFULL (0) 98 // 0x00000020 [5] SM1_TXNFULL (0) 99 // 0x00000010 [4] SM0_TXNFULL (0) 100 // 0x00000008 [3] SM3_RXNEMPTY (0) 101 // 0x00000004 [2] SM2_RXNEMPTY (0) 102 // 0x00000002 [1] SM1_RXNEMPTY (0) 103 // 0x00000001 [0] SM0_RXNEMPTY (0) 104 io_rw_32 inte; 105 106 _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF 107 // Interrupt Force for irq0 108 // 0x00008000 [15] SM7 (0) 109 // 0x00004000 [14] SM6 (0) 110 // 0x00002000 [13] SM5 (0) 111 // 0x00001000 [12] SM4 (0) 112 // 0x00000800 [11] SM3 (0) 113 // 0x00000400 [10] SM2 (0) 114 // 0x00000200 [9] SM1 (0) 115 // 0x00000100 [8] SM0 (0) 116 // 0x00000080 [7] SM3_TXNFULL (0) 117 // 0x00000040 [6] SM2_TXNFULL (0) 118 // 0x00000020 [5] SM1_TXNFULL (0) 119 // 0x00000010 [4] SM0_TXNFULL (0) 120 // 0x00000008 [3] SM3_RXNEMPTY (0) 121 // 0x00000004 [2] SM2_RXNEMPTY (0) 122 // 0x00000002 [1] SM1_RXNEMPTY (0) 123 // 0x00000001 [0] SM0_RXNEMPTY (0) 124 io_rw_32 intf; 125 126 _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS 127 // Interrupt status after masking & forcing for irq0 128 // 0x00008000 [15] SM7 (0) 129 // 0x00004000 [14] SM6 (0) 130 // 0x00002000 [13] SM5 (0) 131 // 0x00001000 [12] SM4 (0) 132 // 0x00000800 [11] SM3 (0) 133 // 0x00000400 [10] SM2 (0) 134 // 0x00000200 [9] SM1 (0) 135 // 0x00000100 [8] SM0 (0) 136 // 0x00000080 [7] SM3_TXNFULL (0) 137 // 0x00000040 [6] SM2_TXNFULL (0) 138 // 0x00000020 [5] SM1_TXNFULL (0) 139 // 0x00000010 [4] SM0_TXNFULL (0) 140 // 0x00000008 [3] SM3_RXNEMPTY (0) 141 // 0x00000004 [2] SM2_RXNEMPTY (0) 142 // 0x00000002 [1] SM1_RXNEMPTY (0) 143 // 0x00000001 [0] SM0_RXNEMPTY (0) 144 io_ro_32 ints; 145 } pio_irq_ctrl_hw_t; 146 147 typedef struct { 148 _REG_(PIO_CTRL_OFFSET) // PIO_CTRL 149 // PIO control register 150 // 0x04000000 [26] NEXTPREV_CLKDIV_RESTART (0) Write 1 to restart the clock dividers of state machines... 151 // 0x02000000 [25] NEXTPREV_SM_DISABLE (0) Write 1 to disable state machines in neighbouring PIO... 152 // 0x01000000 [24] NEXTPREV_SM_ENABLE (0) Write 1 to enable state machines in neighbouring PIO... 153 // 0x00f00000 [23:20] NEXT_PIO_MASK (0x0) A mask of state machines in the neighbouring... 154 // 0x000f0000 [19:16] PREV_PIO_MASK (0x0) A mask of state machines in the neighbouring... 155 // 0x00000f00 [11:8] CLKDIV_RESTART (0x0) Restart a state machine's clock divider from an initial... 156 // 0x000000f0 [7:4] SM_RESTART (0x0) Write 1 to instantly clear internal SM state which may... 157 // 0x0000000f [3:0] SM_ENABLE (0x0) Enable/disable each of the four state machines by... 158 io_rw_32 ctrl; 159 160 _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT 161 // FIFO status register 162 // 0x0f000000 [27:24] TXEMPTY (0xf) State machine TX FIFO is empty 163 // 0x000f0000 [19:16] TXFULL (0x0) State machine TX FIFO is full 164 // 0x00000f00 [11:8] RXEMPTY (0xf) State machine RX FIFO is empty 165 // 0x0000000f [3:0] RXFULL (0x0) State machine RX FIFO is full 166 io_ro_32 fstat; 167 168 _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG 169 // FIFO debug register 170 // 0x0f000000 [27:24] TXSTALL (0x0) State machine has stalled on empty TX FIFO during a... 171 // 0x000f0000 [19:16] TXOVER (0x0) TX FIFO overflow (i 172 // 0x00000f00 [11:8] RXUNDER (0x0) RX FIFO underflow (i 173 // 0x0000000f [3:0] RXSTALL (0x0) State machine has stalled on full RX FIFO during a... 174 io_rw_32 fdebug; 175 176 _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL 177 // FIFO levels 178 // 0xf0000000 [31:28] RX3 (0x0) 179 // 0x0f000000 [27:24] TX3 (0x0) 180 // 0x00f00000 [23:20] RX2 (0x0) 181 // 0x000f0000 [19:16] TX2 (0x0) 182 // 0x0000f000 [15:12] RX1 (0x0) 183 // 0x00000f00 [11:8] TX1 (0x0) 184 // 0x000000f0 [7:4] RX0 (0x0) 185 // 0x0000000f [3:0] TX0 (0x0) 186 io_ro_32 flevel; 187 188 // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes) 189 _REG_(PIO_TXF0_OFFSET) // PIO_TXF0 190 // Direct write access to the TX FIFO for this state machine 191 // 0xffffffff [31:0] TXF0 (0x00000000) 192 io_wo_32 txf[4]; 193 194 // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes) 195 _REG_(PIO_RXF0_OFFSET) // PIO_RXF0 196 // Direct read access to the RX FIFO for this state machine 197 // 0xffffffff [31:0] RXF0 (-) 198 io_ro_32 rxf[4]; 199 200 _REG_(PIO_IRQ_OFFSET) // PIO_IRQ 201 // State machine IRQ flags register 202 // 0x000000ff [7:0] IRQ (0x00) 203 io_rw_32 irq; 204 205 _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE 206 // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ 207 // 0x000000ff [7:0] IRQ_FORCE (0x00) 208 io_wo_32 irq_force; 209 210 _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS 211 // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities 212 // 0xffffffff [31:0] INPUT_SYNC_BYPASS (0x00000000) 213 io_rw_32 input_sync_bypass; 214 215 _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT 216 // Read to sample the pad output values PIO is currently driving to the GPIOs 217 // 0xffffffff [31:0] DBG_PADOUT (0x00000000) 218 io_ro_32 dbg_padout; 219 220 _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE 221 // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs 222 // 0xffffffff [31:0] DBG_PADOE (0x00000000) 223 io_ro_32 dbg_padoe; 224 225 _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO 226 // The PIO hardware has some free parameters that may vary between chip products 227 // 0xf0000000 [31:28] VERSION (0x1) Version of the core PIO hardware 228 // 0x003f0000 [21:16] IMEM_SIZE (-) The size of the instruction memory, measured in units of... 229 // 0x00000f00 [11:8] SM_COUNT (-) The number of state machines this PIO instance is equipped with 230 // 0x0000003f [5:0] FIFO_DEPTH (-) The depth of the state machine TX/RX FIFOs, measured in words 231 io_ro_32 dbg_cfginfo; 232 233 // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes) 234 _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0 235 // Write-only access to instruction memory location 0 236 // 0x0000ffff [15:0] INSTR_MEM0 (0x0000) 237 io_wo_32 instr_mem[32]; 238 239 pio_sm_hw_t sm[4]; 240 241 // (Description copied from array index 0 register PIO_RXF0_PUTGET0 applies similarly to other array indexes) 242 _REG_(PIO_RXF0_PUTGET0_OFFSET) // PIO_RXF0_PUTGET0 243 // Direct read/write access to the RX FIFO on all SMs, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set 244 // 0xffffffff [31:0] RXF0_PUTGET0 (0x00000000) 245 io_rw_32 rxf_putget[4][4]; 246 247 _REG_(PIO_GPIOBASE_OFFSET) // PIO_GPIOBASE 248 // Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32... 249 // 0x00000010 [4] GPIOBASE (0) 250 io_rw_32 gpiobase; 251 252 _REG_(PIO_INTR_OFFSET) // PIO_INTR 253 // Raw Interrupts 254 // 0x00008000 [15] SM7 (0) 255 // 0x00004000 [14] SM6 (0) 256 // 0x00002000 [13] SM5 (0) 257 // 0x00001000 [12] SM4 (0) 258 // 0x00000800 [11] SM3 (0) 259 // 0x00000400 [10] SM2 (0) 260 // 0x00000200 [9] SM1 (0) 261 // 0x00000100 [8] SM0 (0) 262 // 0x00000080 [7] SM3_TXNFULL (0) 263 // 0x00000040 [6] SM2_TXNFULL (0) 264 // 0x00000020 [5] SM1_TXNFULL (0) 265 // 0x00000010 [4] SM0_TXNFULL (0) 266 // 0x00000008 [3] SM3_RXNEMPTY (0) 267 // 0x00000004 [2] SM2_RXNEMPTY (0) 268 // 0x00000002 [1] SM1_RXNEMPTY (0) 269 // 0x00000001 [0] SM0_RXNEMPTY (0) 270 io_ro_32 intr; 271 272 union { 273 struct { 274 _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE 275 // Interrupt Enable for irq0 276 // 0x00000800 [11] SM3 (0) 277 // 0x00000400 [10] SM2 (0) 278 // 0x00000200 [9] SM1 (0) 279 // 0x00000100 [8] SM0 (0) 280 // 0x00000080 [7] SM3_TXNFULL (0) 281 // 0x00000040 [6] SM2_TXNFULL (0) 282 // 0x00000020 [5] SM1_TXNFULL (0) 283 // 0x00000010 [4] SM0_TXNFULL (0) 284 // 0x00000008 [3] SM3_RXNEMPTY (0) 285 // 0x00000004 [2] SM2_RXNEMPTY (0) 286 // 0x00000002 [1] SM1_RXNEMPTY (0) 287 // 0x00000001 [0] SM0_RXNEMPTY (0) 288 io_rw_32 inte0; 289 290 _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF 291 // Interrupt Force for irq0 292 // 0x00000800 [11] SM3 (0) 293 // 0x00000400 [10] SM2 (0) 294 // 0x00000200 [9] SM1 (0) 295 // 0x00000100 [8] SM0 (0) 296 // 0x00000080 [7] SM3_TXNFULL (0) 297 // 0x00000040 [6] SM2_TXNFULL (0) 298 // 0x00000020 [5] SM1_TXNFULL (0) 299 // 0x00000010 [4] SM0_TXNFULL (0) 300 // 0x00000008 [3] SM3_RXNEMPTY (0) 301 // 0x00000004 [2] SM2_RXNEMPTY (0) 302 // 0x00000002 [1] SM1_RXNEMPTY (0) 303 // 0x00000001 [0] SM0_RXNEMPTY (0) 304 io_rw_32 intf0; 305 306 _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS 307 // Interrupt status after masking & forcing for irq0 308 // 0x00000800 [11] SM3 (0) 309 // 0x00000400 [10] SM2 (0) 310 // 0x00000200 [9] SM1 (0) 311 // 0x00000100 [8] SM0 (0) 312 // 0x00000080 [7] SM3_TXNFULL (0) 313 // 0x00000040 [6] SM2_TXNFULL (0) 314 // 0x00000020 [5] SM1_TXNFULL (0) 315 // 0x00000010 [4] SM0_TXNFULL (0) 316 // 0x00000008 [3] SM3_RXNEMPTY (0) 317 // 0x00000004 [2] SM2_RXNEMPTY (0) 318 // 0x00000002 [1] SM1_RXNEMPTY (0) 319 // 0x00000001 [0] SM0_RXNEMPTY (0) 320 io_ro_32 ints0; 321 322 _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE 323 // Interrupt Enable for irq1 324 // 0x00000800 [11] SM3 (0) 325 // 0x00000400 [10] SM2 (0) 326 // 0x00000200 [9] SM1 (0) 327 // 0x00000100 [8] SM0 (0) 328 // 0x00000080 [7] SM3_TXNFULL (0) 329 // 0x00000040 [6] SM2_TXNFULL (0) 330 // 0x00000020 [5] SM1_TXNFULL (0) 331 // 0x00000010 [4] SM0_TXNFULL (0) 332 // 0x00000008 [3] SM3_RXNEMPTY (0) 333 // 0x00000004 [2] SM2_RXNEMPTY (0) 334 // 0x00000002 [1] SM1_RXNEMPTY (0) 335 // 0x00000001 [0] SM0_RXNEMPTY (0) 336 io_rw_32 inte1; 337 338 _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF 339 // Interrupt Force for irq1 340 // 0x00000800 [11] SM3 (0) 341 // 0x00000400 [10] SM2 (0) 342 // 0x00000200 [9] SM1 (0) 343 // 0x00000100 [8] SM0 (0) 344 // 0x00000080 [7] SM3_TXNFULL (0) 345 // 0x00000040 [6] SM2_TXNFULL (0) 346 // 0x00000020 [5] SM1_TXNFULL (0) 347 // 0x00000010 [4] SM0_TXNFULL (0) 348 // 0x00000008 [3] SM3_RXNEMPTY (0) 349 // 0x00000004 [2] SM2_RXNEMPTY (0) 350 // 0x00000002 [1] SM1_RXNEMPTY (0) 351 // 0x00000001 [0] SM0_RXNEMPTY (0) 352 io_rw_32 intf1; 353 354 _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS 355 // Interrupt status after masking & forcing for irq1 356 // 0x00000800 [11] SM3 (0) 357 // 0x00000400 [10] SM2 (0) 358 // 0x00000200 [9] SM1 (0) 359 // 0x00000100 [8] SM0 (0) 360 // 0x00000080 [7] SM3_TXNFULL (0) 361 // 0x00000040 [6] SM2_TXNFULL (0) 362 // 0x00000020 [5] SM1_TXNFULL (0) 363 // 0x00000010 [4] SM0_TXNFULL (0) 364 // 0x00000008 [3] SM3_RXNEMPTY (0) 365 // 0x00000004 [2] SM2_RXNEMPTY (0) 366 // 0x00000002 [1] SM1_RXNEMPTY (0) 367 // 0x00000001 [0] SM0_RXNEMPTY (0) 368 io_ro_32 ints1; 369 }; 370 pio_irq_ctrl_hw_t irq_ctrl[2]; 371 }; 372 } pio_hw_t; 373 374 #define pio0_hw ((pio_hw_t *)PIO0_BASE) 375 #define pio1_hw ((pio_hw_t *)PIO1_BASE) 376 #define pio2_hw ((pio_hw_t *)PIO2_BASE) 377 static_assert(sizeof (pio_hw_t) == 0x0188, ""); 378 379 #endif // _HARDWARE_STRUCTS_PIO_H 380 381
