1 /* 2 * Copyright (c) 2016 Nordic Semiconductor ASA 3 * Copyright (c) 2016 Vinayak Kariappa Chettimada 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 /* 9 * PDU fields sizes 10 */ 11 12 #define PDU_PREAMBLE_SIZE(phy) (phy&0x3) 13 #define PDU_ACCESS_ADDR_SIZE 4 14 #define PDU_HEADER_SIZE 2 15 #define PDU_MIC_SIZE 4 16 #define PDU_CRC_SIZE 3 17 #define PDU_OVERHEAD_SIZE(phy) (PDU_PREAMBLE_SIZE(phy) + \ 18 PDU_ACCESS_ADDR_SIZE + \ 19 PDU_HEADER_SIZE + \ 20 PDU_CRC_SIZE) 21 22 #define BDADDR_SIZE 6 23 #define ADVA_SIZE BDADDR_SIZE 24 #define SCANA_SIZE BDADDR_SIZE 25 #define INITA_SIZE BDADDR_SIZE 26 #define TARGETA_SIZE BDADDR_SIZE 27 #define LLDATA_SIZE 22 28 29 /* Constant offsets in extended header (TargetA is present in PDUs with AdvA) */ 30 #define ADVA_OFFSET 0 31 #define TGTA_OFFSET (ADVA_OFFSET + BDADDR_SIZE) 32 33 #define BYTES2US(bytes, phy) (((bytes)<<3)/BIT((phy&0x3)>>1)) 34 35 /* Advertisement channel minimum payload size */ 36 #define PDU_AC_PAYLOAD_SIZE_MIN 1 37 /* Advertisement channel maximum legacy payload size */ 38 #define PDU_AC_LEG_PAYLOAD_SIZE_MAX 37 39 /* Advertisement channel maximum legacy advertising/scan data size */ 40 #define PDU_AC_LEG_DATA_SIZE_MAX 31 41 42 #if defined(CONFIG_BT_CTLR_ADV_EXT) 43 /* Advertisement channel maximum extended payload size */ 44 #define PDU_AC_EXT_PAYLOAD_SIZE_MAX 255 45 46 /* Extended Scan and Periodic Sync Rx PDU time reservation */ 47 #if defined(CONFIG_BT_CTLR_SCAN_AUX_SYNC_RESERVE_MIN) 48 #define PDU_AC_EXT_PAYLOAD_RX_SIZE 0U 49 #else /* !CONFIG_BT_CTLR_SCAN_AUX_SYNC_RESERVE_MIN */ 50 #define PDU_AC_EXT_PAYLOAD_RX_SIZE PDU_AC_EXT_PAYLOAD_SIZE_MAX 51 #endif /* !CONFIG_BT_CTLR_SCAN_AUX_SYNC_RESERVE_MIN */ 52 53 #define PDU_AC_EXT_HEADER_SIZE_MIN offsetof(struct pdu_adv_com_ext_adv, \ 54 ext_hdr_adv_data) 55 #define PDU_AC_EXT_HEADER_SIZE_MAX 63 56 /* TODO: PDU_AC_EXT_PAYLOAD_OVERHEAD can be reduced based on supported 57 * features, like omitting support for periodic advertising will reduce 58 * 18 octets in the Common Extended Advertising Payload Format. 59 */ 60 #define PDU_AC_EXT_PAYLOAD_OVERHEAD (PDU_AC_EXT_HEADER_SIZE_MIN + \ 61 PDU_AC_EXT_HEADER_SIZE_MAX) 62 #endif /* CONFIG_BT_CTLR_ADV_EXT */ 63 64 #if defined(CONFIG_BT_CTLR_ADV_EXT) && defined(CONFIG_BT_BROADCASTER) 65 #define PDU_AC_PAYLOAD_SIZE_MAX MAX(MIN((PDU_AC_EXT_PAYLOAD_OVERHEAD + \ 66 CONFIG_BT_CTLR_ADV_DATA_LEN_MAX), \ 67 PDU_AC_EXT_PAYLOAD_SIZE_MAX), \ 68 PDU_AC_LEG_PAYLOAD_SIZE_MAX) 69 #define PDU_AC_EXT_AD_DATA_LEN_MAX (PDU_AC_PAYLOAD_SIZE_MAX - \ 70 PDU_AC_EXT_PAYLOAD_OVERHEAD) 71 #else /* !CONFIG_BT_CTLR_ADV_EXT || !CONFIG_BT_BROADCASTER */ 72 #define PDU_AC_PAYLOAD_SIZE_MAX PDU_AC_LEG_PAYLOAD_SIZE_MAX 73 #endif /* !CONFIG_BT_CTLR_ADV_EXT || !CONFIG_BT_BROADCASTER */ 74 75 /* Link Layer header size of Adv PDU. Assumes pdu_adv is packed */ 76 #define PDU_AC_LL_HEADER_SIZE (offsetof(struct pdu_adv, payload)) 77 78 /* Link Layer Advertisement channel maximum PDU buffer size */ 79 #define PDU_AC_LL_SIZE_MAX (PDU_AC_LL_HEADER_SIZE + PDU_AC_PAYLOAD_SIZE_MAX) 80 81 /* Advertisement channel Access Address */ 82 #define PDU_AC_ACCESS_ADDR 0x8e89bed6 83 84 /* Advertisement channel CRC init value */ 85 #define PDU_AC_CRC_IV 0x555555 86 87 /* CRC polynomial */ 88 #define PDU_CRC_POLYNOMIAL ((0x5bUL) | ((0x06UL) << 8) | ((0x00UL) << 16)) 89 90 /* Data channel minimum payload size and time in us */ 91 #define PDU_DC_PAYLOAD_SIZE_MIN 27 92 #define PDU_DC_PAYLOAD_TIME_MIN 328 93 #define PDU_DC_PAYLOAD_TIME_MIN_CODED 2704 94 95 /* Data channel maximum payload size and time in us */ 96 #define PDU_DC_PAYLOAD_SIZE_MAX 251 97 #define PDU_DC_PAYLOAD_TIME_MAX_CODED 17040 98 99 #if defined(CONFIG_BT_CTLR_DF) 100 #define PDU_DC_PAYLOAD_TIME_MAX 2128 101 #else /* !CONFIG_BT_CTLR_DF */ 102 #define PDU_DC_PAYLOAD_TIME_MAX 2120 103 #endif /* !CONFIG_BT_CTLR_DF */ 104 105 /* Data channel control PDU maximum payload size */ 106 #if defined(CONFIG_BT_CONN) 107 #if defined(CONFIG_BT_CTLR_CONN_ISO) 108 #if defined(CONFIG_BT_CENTRAL) && defined(CONFIG_BT_PERIPHERAL) 109 /* Isochronous Central and Peripheral */ 110 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(cis_req) 111 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(cis_req) 112 #elif defined(CONFIG_BT_CENTRAL) 113 /* Isochronous Central */ 114 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(cis_req) 115 #if defined(CONFIG_BT_CTLR_CONN_PARAM_REQ) 116 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_param_req) 117 #elif defined(CONFIG_BT_CTLR_LE_ENC) 118 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_rsp) 119 #else /* !CONFIG_BT_CTLR_LE_ENC */ 120 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(cis_rsp) 121 #endif /* !CONFIG_BT_CTLR_LE_ENC */ 122 #elif defined(CONFIG_BT_PERIPHERAL) 123 /* Isochronous Peripheral */ 124 #if defined(CONFIG_BT_CTLR_CONN_PARAM_REQ) 125 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_param_req) 126 #elif defined(CONFIG_BT_CTLR_LE_ENC) 127 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_rsp) 128 #else /* !CONFIG_BT_CTLR_LE_ENC */ 129 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(cis_rsp) 130 #endif /* !CONFIG_BT_CTLR_LE_ENC */ 131 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(cis_req) 132 #endif /* !CONFIG_BT_PERIPHERAL */ 133 134 #elif defined(CONFIG_BT_CTLR_CONN_PARAM_REQ) 135 /* Central and Peripheral with Connection Parameter Request */ 136 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_param_req) 137 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_param_req) 138 139 #elif defined(CONFIG_BT_CTLR_LE_ENC) 140 #if defined(CONFIG_BT_CENTRAL) && defined(CONFIG_BT_PERIPHERAL) 141 /* Central and Peripheral with encryption */ 142 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_req) 143 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_req) 144 #elif defined(CONFIG_BT_CENTRAL) 145 /* Central with encryption */ 146 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_req) 147 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_rsp) 148 #elif defined(CONFIG_BT_PERIPHERAL) 149 /* Peripheral with encryption */ 150 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_rsp) 151 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_req) 152 #endif /* !CONFIG_BT_PERIPHERAL */ 153 154 #else /* !CONFIG_BT_CTLR_LE_ENC */ 155 #if defined(CONFIG_BT_CENTRAL) && defined(CONFIG_BT_PERIPHERAL) 156 /* Central and Peripheral without encryption */ 157 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_update_ind) 158 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_update_ind) 159 #elif defined(CONFIG_BT_CENTRAL) 160 /* Central without encryption */ 161 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_update_ind) 162 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(feature_rsp) 163 #elif defined(CONFIG_BT_PERIPHERAL) 164 /* Peripheral without encryption */ 165 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(feature_rsp) 166 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_update_ind) 167 #endif /* !CONFIG_BT_PERIPHERAL */ 168 #endif /* !CONFIG_BT_CTLR_LE_ENC */ 169 170 #else /* !CONFIG_BT_CONN */ 171 #define PDU_DC_CTRL_TX_SIZE_MAX 0U 172 #define PDU_DC_CTRL_RX_SIZE_MAX 0U 173 #endif /* !CONFIG_BT_CONN */ 174 175 /* Link Layer header size of Data PDU. Assumes pdu_data is packed */ 176 #define PDU_DC_LL_HEADER_SIZE (offsetof(struct pdu_data, lldata)) 177 178 /* Link Layer Max size of an empty PDU. TODO: Remove; only used in Nordic LLL */ 179 #define PDU_EM_LL_SIZE_MAX (PDU_DC_LL_HEADER_SIZE) 180 181 /* Link Layer header size of BIS PDU. Assumes pdu_bis is packed */ 182 #define PDU_BIS_LL_HEADER_SIZE (offsetof(struct pdu_bis, payload)) 183 184 /* Event Active Clock Jitter */ 185 #define EVENT_CLOCK_JITTER_US 2 186 /* Event interframe timings */ 187 #define EVENT_IFS_US 150 188 /* Standard allows 2 us timing uncertainty inside the event */ 189 #define EVENT_IFS_MAX_US (EVENT_IFS_US + EVENT_CLOCK_JITTER_US) 190 /* Controller will layout extended adv with minimum separation */ 191 #define EVENT_MAFS_US 300 192 /* Standard allows 2 us timing uncertainty inside the event */ 193 #define EVENT_MAFS_MAX_US (EVENT_MAFS_US + EVENT_CLOCK_JITTER_US) 194 /* Controller defined back to back transmit MAFS for extended advertising */ 195 #define EVENT_B2B_MAFS_US (CONFIG_BT_CTLR_ADV_AUX_PDU_BACK2BACK_AFS) 196 /* Controller defined back to back transmit MAFS for periodic advertising */ 197 #define EVENT_SYNC_B2B_MAFS_US (CONFIG_BT_CTLR_ADV_SYNC_PDU_BACK2BACK_AFS) 198 /* Minimum Subevent Space timings */ 199 #define EVENT_MSS_US 150 200 /* Standard allows 2 us timing uncertainty inside the event */ 201 #define EVENT_MSS_MAX_US (EVENT_MSS_US + EVENT_CLOCK_JITTER_US) 202 203 /* Instant maximum value and maximum latency (or delta) past the instant */ 204 #define EVENT_INSTANT_MAX 0xffff 205 #define EVENT_INSTANT_LATENCY_MAX 0x7fff 206 207 /* Channel Map Unused channels count minimum */ 208 #define CHM_USED_COUNT_MIN 2U 209 210 /* Channel Map hop count minimum and maximum */ 211 #define CHM_HOP_COUNT_MIN 5U 212 #define CHM_HOP_COUNT_MAX 16U 213 214 /* Offset Units field encoding */ 215 #define OFFS_UNIT_BITS 13 216 #define OFFS_UNIT_30_US 30 217 #define OFFS_UNIT_300_US 300 218 #define OFFS_UNIT_VALUE_30_US 0 219 #define OFFS_UNIT_VALUE_300_US 1 220 /* Value specified in BT Spec. Vol 6, Part B, section 2.3.4.6 */ 221 #define OFFS_ADJUST_US 2457600UL 222 223 /* Macros for getting offset/phy from pdu_adv_aux_ptr */ 224 #define PDU_ADV_AUX_PTR_OFFSET_GET(aux_ptr) ((aux_ptr)->offs_phy_packed[0] | \ 225 (((aux_ptr)->offs_phy_packed[1] & 0x1F) << 8)) 226 #define PDU_ADV_AUX_PTR_PHY_GET(aux_ptr) (((aux_ptr)->offs_phy_packed[1] >> 5) & 0x07) 227 228 /* Macros for getting/setting offset/offset_units/offset_adjust from pdu_adv_sync_info */ 229 #define PDU_ADV_SYNC_INFO_OFFSET_GET(si) ((si)->offs_packed[0] | \ 230 (((si)->offs_packed[1] & 0x1F) << 8)) 231 #define PDU_ADV_SYNC_INFO_OFFS_UNITS_GET(si) (((si)->offs_packed[1] >> 5) & 0x01) 232 #define PDU_ADV_SYNC_INFO_OFFS_ADJUST_GET(si) (((si)->offs_packed[1] >> 6) & 0x01) 233 #define PDU_ADV_SYNC_INFO_OFFS_SET(si, offs, offs_units, offs_adjust) \ 234 do { \ 235 (si)->offs_packed[0] = (offs) & 0xFF; \ 236 (si)->offs_packed[1] = (((offs) >> 8) & 0x1F) + \ 237 (((offs_units) << 5) & 0x20) + \ 238 (((offs_adjust) << 6) & 0x40); \ 239 } while (0) 240 241 /* Advertiser's Sleep Clock Accuracy Value */ 242 #define SCA_500_PPM 500 /* 51 ppm to 500 ppm */ 243 #define SCA_50_PPM 50 /* 0 ppm to 50 ppm */ 244 #define SCA_VALUE_500_PPM 0 /* 51 ppm to 500 ppm */ 245 #define SCA_VALUE_50_PPM 1 /* 0 ppm to 50 ppm */ 246 247 /* Sleep Clock Accuracy, calculate drift in microseconds */ 248 #define SCA_DRIFT_50_PPM_US(t) (((t) * 50UL) / 1000000UL) 249 #define SCA_DRIFT_500_PPM_US(t) (((t) * 500UL) / 1000000UL) 250 251 /* transmitWindowDelay times (us) */ 252 #define WIN_DELAY_LEGACY 1250 253 #define WIN_DELAY_UNCODED 2500 254 #define WIN_DELAY_CODED 3750 255 256 /* Channel Map Size */ 257 #define PDU_CHANNEL_MAP_SIZE 5 258 259 /* Advertising Data */ 260 #define PDU_ADV_DATA_HEADER_SIZE 2U 261 #define PDU_ADV_DATA_HEADER_LEN_SIZE 1U 262 #define PDU_ADV_DATA_HEADER_TYPE_SIZE 1U 263 #define PDU_ADV_DATA_HEADER_LEN_OFFSET 0U 264 #define PDU_ADV_DATA_HEADER_TYPE_OFFSET 1U 265 #define PDU_ADV_DATA_HEADER_DATA_OFFSET 2U 266 267 /* Advertising Data Types in ACAD */ 268 #define PDU_ADV_DATA_TYPE_CHANNEL_MAP_UPDATE_IND 0x28 269 270 /* 271 * Macros to return correct Data Channel PDU time 272 * Note: formula is valid for 1M, 2M and Coded S8 273 * see BT spec Version 5.1 Vol 6. Part B, chapters 2.1 and 2.2 274 * for packet formats and thus lengths 275 */ 276 277 #define PHY_LEGACY 0 278 #define PHY_1M BIT(0) 279 #define PHY_2M BIT(1) 280 #define PHY_CODED BIT(2) 281 #define PHY_FLAGS_S2 0 282 #define PHY_FLAGS_S8 BIT(0) 283 284 /* Macros for getting/setting did/sid from pdu_adv_adi */ 285 #define PDU_ADV_ADI_DID_GET(adi) ((adi)->did_sid_packed[0] | \ 286 (((adi)->did_sid_packed[1] & 0x0F) << 8)) 287 #define PDU_ADV_ADI_SID_GET(adi) (((adi)->did_sid_packed[1] >> 4) & 0x0F) 288 #define PDU_ADV_ADI_SID_SET(adi, sid) (adi)->did_sid_packed[1] = (((sid) << 4) + \ 289 ((adi)->did_sid_packed[1] & 0x0F)) 290 #define PDU_ADV_ADI_DID_SID_SET(adi, did, sid) \ 291 do { \ 292 (adi)->did_sid_packed[0] = (did) & 0xFF; \ 293 (adi)->did_sid_packed[1] = (((did) >> 8) & 0x0F) + ((sid) << 4); \ 294 } while (0) 295 296 #if defined(CONFIG_BT_CTLR_PHY_CODED) 297 #define CODED_PHY_PREAMBLE_TIME_US 80 298 #define CODED_PHY_ACCESS_ADDRESS_TIME_US 256 299 #define CODED_PHY_CI_TIME_US 16 300 #define CODED_PHY_TERM1_TIME_US 24 301 #define CODED_PHY_CRC_SIZE 24 302 #define CODED_PHY_TERM2_SIZE 3 303 304 #define FEC_BLOCK1_US ((CODED_PHY_ACCESS_ADDRESS_TIME_US) + \ 305 (CODED_PHY_CI_TIME_US) + \ 306 (CODED_PHY_TERM1_TIME_US)) 307 308 /* cs = 0, S2 coding scheme, use PHY_FLAGS_S2 309 * cs = 1, S8 coding scheme, use PHY_FLAGS_S8 310 * 311 * Not using the term CI, Coding Indicator, where in the Spec its defined value 312 * of 0 is S8 encoding, 1 is S2 encoding. 313 */ 314 #define FEC_BLOCK2_US(octets, mic, cs) (((((PDU_HEADER_SIZE) + \ 315 (octets) + \ 316 (mic)) << 3) + \ 317 (CODED_PHY_CRC_SIZE) + \ 318 (CODED_PHY_TERM2_SIZE)) << \ 319 (1 + (((cs) & 0x01) << 1))) 320 321 #define PDU_US(octets, mic, phy, cs) (((phy) & PHY_CODED) ? \ 322 ((CODED_PHY_PREAMBLE_TIME_US) + \ 323 (FEC_BLOCK1_US) + \ 324 FEC_BLOCK2_US((octets), (mic), \ 325 (cs))) : \ 326 (((PDU_PREAMBLE_SIZE(phy) + \ 327 (PDU_ACCESS_ADDR_SIZE) + \ 328 (PDU_HEADER_SIZE) + \ 329 (octets) + \ 330 (mic) + \ 331 (PDU_CRC_SIZE)) << 3) / \ 332 BIT(((phy) & 0x03) >> 1))) 333 334 #define PDU_MAX_US(octets, mic, phy) PDU_US((octets), (mic), (phy), \ 335 PHY_FLAGS_S8) 336 337 #else /* !CONFIG_BT_CTLR_PHY_CODED */ 338 #define PDU_US(octets, mic, phy, cs) (((PDU_PREAMBLE_SIZE(phy) + \ 339 (PDU_ACCESS_ADDR_SIZE) + \ 340 (PDU_HEADER_SIZE) + \ 341 (octets) + \ 342 (mic) + \ 343 (PDU_CRC_SIZE)) << 3) / \ 344 BIT(((phy) & 0x03) >> 1)) 345 346 #define PDU_MAX_US(octets, mic, phy) PDU_US((octets), (mic), (phy), 0) 347 #endif /* !CONFIG_BT_CTLR_PHY_CODED */ 348 349 #define PDU_DC_MAX_US(octets, phy) PDU_MAX_US((octets), (PDU_MIC_SIZE), (phy)) 350 351 #define PDU_DC_US(octets, mic, phy, cs) PDU_US((octets), (mic), (phy), (cs)) 352 353 #define PDU_AC_MAX_US(octets, phy) PDU_MAX_US((octets), 0, (phy)) 354 355 #define PDU_AC_US(octets, phy, cs) PDU_US((octets), 0, (phy), (cs)) 356 357 #define PDU_BIS_MAX_US(octets, enc, phy) PDU_MAX_US((octets), \ 358 ((enc) ? \ 359 (PDU_MIC_SIZE) : 0), \ 360 (phy)) 361 362 #define PDU_BIS_US(octets, enc, phy, s8) PDU_US((octets), \ 363 ((enc) ? (PDU_MIC_SIZE) : 0), \ 364 (phy), (s8)) 365 366 #define PDU_CIS_MAX_US(octets, enc, phy) PDU_MAX_US((octets), \ 367 ((enc) ? \ 368 (PDU_MIC_SIZE) : 0), \ 369 (phy)) 370 #define PDU_CIS_OFFSET_MIN_US 500U 371 372 struct pdu_adv_adv_ind { 373 uint8_t addr[BDADDR_SIZE]; 374 uint8_t data[PDU_AC_LEG_DATA_SIZE_MAX]; 375 } __packed; 376 377 struct pdu_adv_direct_ind { 378 uint8_t adv_addr[BDADDR_SIZE]; 379 uint8_t tgt_addr[BDADDR_SIZE]; 380 } __packed; 381 382 struct pdu_adv_scan_rsp { 383 uint8_t addr[BDADDR_SIZE]; 384 uint8_t data[PDU_AC_LEG_DATA_SIZE_MAX]; 385 } __packed; 386 387 struct pdu_adv_scan_req { 388 uint8_t scan_addr[BDADDR_SIZE]; 389 uint8_t adv_addr[BDADDR_SIZE]; 390 } __packed; 391 392 struct pdu_adv_connect_ind { 393 uint8_t init_addr[BDADDR_SIZE]; 394 uint8_t adv_addr[BDADDR_SIZE]; 395 struct { 396 uint8_t access_addr[4]; 397 uint8_t crc_init[3]; 398 uint8_t win_size; 399 uint16_t win_offset; 400 uint16_t interval; 401 uint16_t latency; 402 uint16_t timeout; 403 uint8_t chan_map[PDU_CHANNEL_MAP_SIZE]; 404 #ifdef CONFIG_LITTLE_ENDIAN 405 uint8_t hop:5; 406 uint8_t sca:3; 407 #else 408 uint8_t sca:3; 409 uint8_t hop:5; 410 #endif /* CONFIG_LITTLE_ENDIAN */ 411 412 } __packed; 413 } __packed; 414 415 struct pdu_adv_ext_hdr { 416 #ifdef CONFIG_LITTLE_ENDIAN 417 uint8_t adv_addr:1; 418 uint8_t tgt_addr:1; 419 uint8_t cte_info:1; 420 uint8_t adi:1; 421 uint8_t aux_ptr:1; 422 uint8_t sync_info:1; 423 uint8_t tx_pwr:1; 424 uint8_t rfu:1; 425 #else 426 uint8_t rfu:1; 427 uint8_t tx_pwr:1; 428 uint8_t sync_info:1; 429 uint8_t aux_ptr:1; 430 uint8_t adi:1; 431 uint8_t cte_info:1; 432 uint8_t tgt_addr:1; 433 uint8_t adv_addr:1; 434 #endif /* CONFIG_LITTLE_ENDIAN */ 435 uint8_t data[0]; 436 } __packed; 437 438 struct pdu_adv_com_ext_adv { 439 #ifdef CONFIG_LITTLE_ENDIAN 440 uint8_t ext_hdr_len:6; 441 uint8_t adv_mode:2; 442 #else 443 uint8_t adv_mode:2; 444 uint8_t ext_hdr_len:6; 445 #endif /* CONFIG_LITTLE_ENDIAN */ 446 union { 447 struct pdu_adv_ext_hdr ext_hdr; 448 uint8_t ext_hdr_adv_data[0]; 449 }; 450 } __packed; 451 452 enum pdu_adv_mode { 453 EXT_ADV_MODE_NON_CONN_NON_SCAN = 0x00, 454 EXT_ADV_MODE_CONN_NON_SCAN = 0x01, 455 EXT_ADV_MODE_NON_CONN_SCAN = 0x02, 456 }; 457 458 #define PDU_ADV_SID_COUNT 16 459 460 struct pdu_adv_adi { 461 /* did:12 462 * sid:4 463 * NOTE: This layout as bitfields is not portable for BE using 464 * endianness conversion macros. 465 */ 466 uint8_t did_sid_packed[2]; 467 } __packed; 468 469 struct pdu_adv_aux_ptr { 470 #ifdef CONFIG_LITTLE_ENDIAN 471 uint8_t chan_idx:6; 472 uint8_t ca:1; 473 uint8_t offs_units:1; 474 #else 475 uint8_t offs_units:1; 476 uint8_t ca:1; 477 uint8_t chan_idx:6; 478 #endif /* CONFIG_LITTLE_ENDIAN */ 479 /* offs:13 480 * phy:3 481 * NOTE: This layout as bitfields is not portable for BE using 482 * endianness conversion macros. 483 */ 484 uint8_t offs_phy_packed[2]; 485 } __packed; 486 487 enum pdu_adv_aux_ptr_ca { 488 EXT_ADV_AUX_PTR_CA_500_PPM = 0x00, 489 EXT_ADV_AUX_PTR_CA_50_PPM = 0x01, 490 }; 491 492 enum pdu_adv_offs_units { 493 EXT_ADV_AUX_PTR_OFFS_UNITS_30 = 0x00, 494 EXT_ADV_AUX_PTR_OFFS_UNITS_300 = 0x01, 495 }; 496 497 enum pdu_adv_aux_phy { 498 EXT_ADV_AUX_PHY_LE_1M = 0x00, 499 EXT_ADV_AUX_PHY_LE_2M = 0x01, 500 EXT_ADV_AUX_PHY_LE_CODED = 0x02, 501 }; 502 503 struct pdu_adv_sync_info { 504 /* offs:13 505 * offs_units:1 506 * offs_adjust:1 507 * rfu:1 508 * NOTE: This layout as bitfields is not portable for BE using 509 * endianness conversion macros. 510 */ 511 uint8_t offs_packed[2]; 512 uint16_t interval; 513 uint8_t sca_chm[PDU_CHANNEL_MAP_SIZE]; 514 uint8_t aa[4]; 515 uint8_t crc_init[3]; 516 uint16_t evt_cntr; 517 } __packed; 518 519 #define PDU_SYNC_INFO_SCA_CHM_SCA_BYTE_OFFSET 4 520 #define PDU_SYNC_INFO_SCA_CHM_SCA_BIT_POS 5 521 #define PDU_SYNC_INFO_SCA_CHM_SCA_BIT_MASK \ 522 (0x07 << (PDU_SYNC_INFO_SCA_CHM_SCA_BIT_POS)) 523 524 struct pdu_adv_sync_chm_upd_ind { 525 uint8_t chm[PDU_CHANNEL_MAP_SIZE]; 526 uint16_t instant; 527 } __packed; 528 529 enum pdu_adv_type { 530 PDU_ADV_TYPE_ADV_IND = 0x00, 531 PDU_ADV_TYPE_DIRECT_IND = 0x01, 532 PDU_ADV_TYPE_NONCONN_IND = 0x02, 533 PDU_ADV_TYPE_SCAN_REQ = 0x03, 534 PDU_ADV_TYPE_AUX_SCAN_REQ = PDU_ADV_TYPE_SCAN_REQ, 535 PDU_ADV_TYPE_SCAN_RSP = 0x04, 536 PDU_ADV_TYPE_ADV_IND_SCAN_RSP = 0x05, 537 PDU_ADV_TYPE_CONNECT_IND = 0x05, 538 PDU_ADV_TYPE_AUX_CONNECT_REQ = PDU_ADV_TYPE_CONNECT_IND, 539 PDU_ADV_TYPE_SCAN_IND = 0x06, 540 PDU_ADV_TYPE_EXT_IND = 0x07, 541 PDU_ADV_TYPE_AUX_ADV_IND = PDU_ADV_TYPE_EXT_IND, 542 PDU_ADV_TYPE_AUX_SCAN_RSP = PDU_ADV_TYPE_EXT_IND, 543 PDU_ADV_TYPE_AUX_SYNC_IND = PDU_ADV_TYPE_EXT_IND, 544 PDU_ADV_TYPE_AUX_CHAIN_IND = PDU_ADV_TYPE_EXT_IND, 545 PDU_ADV_TYPE_AUX_CONNECT_RSP = 0x08, 546 } __packed; 547 548 struct pdu_adv { 549 #ifdef CONFIG_LITTLE_ENDIAN 550 uint8_t type:4; 551 uint8_t rfu:1; 552 uint8_t chan_sel:1; 553 uint8_t tx_addr:1; 554 uint8_t rx_addr:1; 555 #else 556 uint8_t rx_addr:1; 557 uint8_t tx_addr:1; 558 uint8_t chan_sel:1; 559 uint8_t rfu:1; 560 uint8_t type:4; 561 #endif /* CONFIG_LITTLE_ENDIAN */ 562 563 uint8_t len; 564 565 union { 566 uint8_t payload[0]; 567 struct pdu_adv_adv_ind adv_ind; 568 struct pdu_adv_direct_ind direct_ind; 569 struct pdu_adv_scan_req scan_req; 570 struct pdu_adv_scan_rsp scan_rsp; 571 struct pdu_adv_connect_ind connect_ind; 572 573 #if defined(CONFIG_BT_CTLR_ADV_EXT) 574 struct pdu_adv_com_ext_adv adv_ext_ind; 575 #endif /* CONFIG_BT_CTLR_ADV_EXT */ 576 } __packed; 577 } __packed; 578 579 enum pdu_data_llid { 580 PDU_DATA_LLID_RESV = 0x00, 581 PDU_DATA_LLID_DATA_CONTINUE = 0x01, 582 PDU_DATA_LLID_DATA_START = 0x02, 583 PDU_DATA_LLID_CTRL = 0x03, 584 }; 585 586 enum pdu_data_llctrl_type { 587 PDU_DATA_LLCTRL_TYPE_CONN_UPDATE_IND = 0x00, 588 PDU_DATA_LLCTRL_TYPE_CHAN_MAP_IND = 0x01, 589 PDU_DATA_LLCTRL_TYPE_TERMINATE_IND = 0x02, 590 PDU_DATA_LLCTRL_TYPE_ENC_REQ = 0x03, 591 PDU_DATA_LLCTRL_TYPE_ENC_RSP = 0x04, 592 PDU_DATA_LLCTRL_TYPE_START_ENC_REQ = 0x05, 593 PDU_DATA_LLCTRL_TYPE_START_ENC_RSP = 0x06, 594 PDU_DATA_LLCTRL_TYPE_UNKNOWN_RSP = 0x07, 595 PDU_DATA_LLCTRL_TYPE_FEATURE_REQ = 0x08, 596 PDU_DATA_LLCTRL_TYPE_FEATURE_RSP = 0x09, 597 PDU_DATA_LLCTRL_TYPE_PAUSE_ENC_REQ = 0x0A, 598 PDU_DATA_LLCTRL_TYPE_PAUSE_ENC_RSP = 0x0B, 599 PDU_DATA_LLCTRL_TYPE_VERSION_IND = 0x0C, 600 PDU_DATA_LLCTRL_TYPE_REJECT_IND = 0x0D, 601 PDU_DATA_LLCTRL_TYPE_PER_INIT_FEAT_XCHG = 0x0E, 602 PDU_DATA_LLCTRL_TYPE_CONN_PARAM_REQ = 0x0F, 603 PDU_DATA_LLCTRL_TYPE_CONN_PARAM_RSP = 0x10, 604 PDU_DATA_LLCTRL_TYPE_REJECT_EXT_IND = 0x11, 605 PDU_DATA_LLCTRL_TYPE_PING_REQ = 0x12, 606 PDU_DATA_LLCTRL_TYPE_PING_RSP = 0x13, 607 PDU_DATA_LLCTRL_TYPE_LENGTH_REQ = 0x14, 608 PDU_DATA_LLCTRL_TYPE_LENGTH_RSP = 0x15, 609 PDU_DATA_LLCTRL_TYPE_PHY_REQ = 0x16, 610 PDU_DATA_LLCTRL_TYPE_PHY_RSP = 0x17, 611 PDU_DATA_LLCTRL_TYPE_PHY_UPD_IND = 0x18, 612 PDU_DATA_LLCTRL_TYPE_MIN_USED_CHAN_IND = 0x19, 613 PDU_DATA_LLCTRL_TYPE_CTE_REQ = 0x1A, 614 PDU_DATA_LLCTRL_TYPE_CTE_RSP = 0x1B, 615 PDU_DATA_LLCTRL_TYPE_CLOCK_ACCURACY_REQ = 0x1D, 616 PDU_DATA_LLCTRL_TYPE_CLOCK_ACCURACY_RSP = 0x1E, 617 PDU_DATA_LLCTRL_TYPE_CIS_REQ = 0x1F, 618 PDU_DATA_LLCTRL_TYPE_CIS_RSP = 0x20, 619 PDU_DATA_LLCTRL_TYPE_CIS_IND = 0x21, 620 PDU_DATA_LLCTRL_TYPE_CIS_TERMINATE_IND = 0x22, 621 PDU_DATA_LLCTRL_TYPE_UNUSED = 0xFF 622 }; 623 624 struct pdu_data_llctrl_conn_update_ind { 625 uint8_t win_size; 626 uint16_t win_offset; 627 uint16_t interval; 628 uint16_t latency; 629 uint16_t timeout; 630 uint16_t instant; 631 } __packed; 632 633 struct pdu_data_llctrl_chan_map_ind { 634 uint8_t chm[PDU_CHANNEL_MAP_SIZE]; 635 uint16_t instant; 636 } __packed; 637 638 struct pdu_data_llctrl_terminate_ind { 639 uint8_t error_code; 640 } __packed; 641 642 struct pdu_data_llctrl_enc_req { 643 uint8_t rand[8]; 644 uint8_t ediv[2]; 645 uint8_t skdm[8]; 646 uint8_t ivm[4]; 647 } __packed; 648 649 struct pdu_data_llctrl_enc_rsp { 650 uint8_t skds[8]; 651 uint8_t ivs[4]; 652 } __packed; 653 654 struct pdu_data_llctrl_start_enc_req { 655 /* no members */ 656 } __packed; 657 658 struct pdu_data_llctrl_start_enc_rsp { 659 /* no members */ 660 } __packed; 661 662 struct pdu_data_llctrl_unknown_rsp { 663 uint8_t type; 664 } __packed; 665 666 struct pdu_data_llctrl_feature_req { 667 uint8_t features[8]; 668 } __packed; 669 670 struct pdu_data_llctrl_feature_rsp { 671 uint8_t features[8]; 672 } __packed; 673 674 struct pdu_data_llctrl_pause_enc_req { 675 /* no members */ 676 } __packed; 677 678 struct pdu_data_llctrl_pause_enc_rsp { 679 /* no members */ 680 } __packed; 681 682 struct pdu_data_llctrl_version_ind { 683 uint8_t version_number; 684 uint16_t company_id; 685 uint16_t sub_version_number; 686 } __packed; 687 688 struct pdu_data_llctrl_reject_ind { 689 uint8_t error_code; 690 } __packed; 691 692 struct pdu_data_llctrl_per_init_feat_xchg { 693 uint8_t features[8]; 694 } __packed; 695 696 struct pdu_data_llctrl_conn_param_req { 697 uint16_t interval_min; 698 uint16_t interval_max; 699 uint16_t latency; 700 uint16_t timeout; 701 uint8_t preferred_periodicity; 702 uint16_t reference_conn_event_count; 703 uint16_t offset0; 704 uint16_t offset1; 705 uint16_t offset2; 706 uint16_t offset3; 707 uint16_t offset4; 708 uint16_t offset5; 709 } __packed; 710 711 struct pdu_data_llctrl_conn_param_rsp { 712 uint16_t interval_min; 713 uint16_t interval_max; 714 uint16_t latency; 715 uint16_t timeout; 716 uint8_t preferred_periodicity; 717 uint16_t reference_conn_event_count; 718 uint16_t offset0; 719 uint16_t offset1; 720 uint16_t offset2; 721 uint16_t offset3; 722 uint16_t offset4; 723 uint16_t offset5; 724 } __packed; 725 726 /* 727 * According to Spec Core v5.3, section 2.4.2.17 728 * LL_CONNECTION_PARAM_RSP and LL_CONNECTION_PARAM_REQ are identical 729 * This is utilized in pdu encode/decode, and for this is needed a common struct 730 */ 731 struct pdu_data_llctrl_conn_param_req_rsp_common { 732 uint16_t interval_min; 733 uint16_t interval_max; 734 uint16_t latency; 735 uint16_t timeout; 736 uint8_t preferred_periodicity; 737 uint16_t reference_conn_event_count; 738 uint16_t offset0; 739 uint16_t offset1; 740 uint16_t offset2; 741 uint16_t offset3; 742 uint16_t offset4; 743 uint16_t offset5; 744 } __packed; 745 746 struct pdu_data_llctrl_reject_ext_ind { 747 uint8_t reject_opcode; 748 uint8_t error_code; 749 } __packed; 750 751 struct pdu_data_llctrl_ping_req { 752 /* no members */ 753 } __packed; 754 755 struct pdu_data_llctrl_ping_rsp { 756 /* no members */ 757 } __packed; 758 759 struct pdu_data_llctrl_length_req { 760 uint16_t max_rx_octets; 761 uint16_t max_rx_time; 762 uint16_t max_tx_octets; 763 uint16_t max_tx_time; 764 } __packed; 765 766 struct pdu_data_llctrl_length_rsp { 767 uint16_t max_rx_octets; 768 uint16_t max_rx_time; 769 uint16_t max_tx_octets; 770 uint16_t max_tx_time; 771 } __packed; 772 773 /* 774 * According to Spec Core v5.3, section 2.4.2.21 775 * LL_LENGTH_REQ and LL_LENGTH_RSP are identical 776 * This is utilized in pdu encode/decode, and for this is needed a common struct 777 */ 778 struct pdu_data_llctrl_length_req_rsp_common { 779 uint16_t max_rx_octets; 780 uint16_t max_rx_time; 781 uint16_t max_tx_octets; 782 uint16_t max_tx_time; 783 } __packed; 784 785 struct pdu_data_llctrl_phy_req { 786 uint8_t tx_phys; 787 uint8_t rx_phys; 788 } __packed; 789 790 struct pdu_data_llctrl_phy_rsp { 791 uint8_t tx_phys; 792 uint8_t rx_phys; 793 } __packed; 794 795 struct pdu_data_llctrl_phy_upd_ind { 796 uint8_t c_to_p_phy; 797 uint8_t p_to_c_phy; 798 uint16_t instant; 799 } __packed; 800 801 struct pdu_data_llctrl_min_used_chans_ind { 802 uint8_t phys; 803 uint8_t min_used_chans; 804 } __packed; 805 806 struct pdu_data_llctrl_cte_req { 807 #ifdef CONFIG_LITTLE_ENDIAN 808 uint8_t min_cte_len_req : 5; 809 uint8_t rfu : 1; 810 uint8_t cte_type_req : 2; 811 #else 812 uint8_t cte_type_req : 2; 813 uint8_t rfu : 1; 814 uint8_t min_cte_len_req : 5; 815 #endif /* CONFIG_LITTLE_ENDIAN */ 816 } __packed; 817 818 struct pdu_data_llctrl_cte_rsp { 819 /* no members */ 820 } __packed; 821 822 struct pdu_data_llctrl_clock_accuracy_req { 823 uint8_t sca; 824 } __packed; 825 826 struct pdu_data_llctrl_clock_accuracy_rsp { 827 uint8_t sca; 828 } __packed; 829 830 struct pdu_data_llctrl_cis_req { 831 uint8_t cig_id; 832 uint8_t cis_id; 833 uint8_t c_phy; 834 uint8_t p_phy; 835 /* c_max_sdu:12 836 * rfu:3 837 * framed:1 838 * NOTE: This layout as bitfields is not portable for BE using 839 * endianness conversion macros. 840 */ 841 uint8_t c_max_sdu_packed[2]; 842 /* p_max_sdu:12 843 * rfu:4 844 * NOTE: This layout as bitfields is not portable for BE using 845 * endianness conversion macros. 846 */ 847 uint8_t p_max_sdu[2]; 848 uint8_t c_sdu_interval[3]; 849 uint8_t p_sdu_interval[3]; 850 uint16_t c_max_pdu; 851 uint16_t p_max_pdu; 852 uint8_t nse; 853 uint8_t sub_interval[3]; 854 #ifdef CONFIG_LITTLE_ENDIAN 855 uint8_t c_bn:4; 856 uint8_t p_bn:4; 857 #else 858 uint8_t p_bn:4; 859 uint8_t c_bn:4; 860 #endif /* CONFIG_LITTLE_ENDIAN */ 861 uint8_t c_ft; 862 uint8_t p_ft; 863 uint16_t iso_interval; 864 uint8_t cis_offset_min[3]; 865 uint8_t cis_offset_max[3]; 866 uint16_t conn_event_count; 867 } __packed; 868 869 struct pdu_data_llctrl_cis_rsp { 870 uint8_t cis_offset_min[3]; 871 uint8_t cis_offset_max[3]; 872 uint16_t conn_event_count; 873 } __packed; 874 875 struct pdu_data_llctrl_cis_ind { 876 uint8_t aa[4]; 877 uint8_t cis_offset[3]; 878 uint8_t cig_sync_delay[3]; 879 uint8_t cis_sync_delay[3]; 880 uint16_t conn_event_count; 881 } __packed; 882 883 struct pdu_data_llctrl_cis_terminate_ind { 884 uint8_t cig_id; 885 uint8_t cis_id; 886 uint8_t error_code; 887 } __packed; 888 889 struct pdu_data_llctrl { 890 uint8_t opcode; 891 union { 892 struct pdu_data_llctrl_conn_update_ind conn_update_ind; 893 struct pdu_data_llctrl_chan_map_ind chan_map_ind; 894 struct pdu_data_llctrl_terminate_ind terminate_ind; 895 struct pdu_data_llctrl_enc_req enc_req; 896 struct pdu_data_llctrl_enc_rsp enc_rsp; 897 struct pdu_data_llctrl_start_enc_req start_enc_req; 898 struct pdu_data_llctrl_start_enc_rsp start_enc_rsp; 899 struct pdu_data_llctrl_unknown_rsp unknown_rsp; 900 struct pdu_data_llctrl_feature_req feature_req; 901 struct pdu_data_llctrl_feature_rsp feature_rsp; 902 struct pdu_data_llctrl_pause_enc_req pause_enc_req; 903 struct pdu_data_llctrl_pause_enc_rsp pause_enc_rsp; 904 struct pdu_data_llctrl_version_ind version_ind; 905 struct pdu_data_llctrl_reject_ind reject_ind; 906 struct pdu_data_llctrl_per_init_feat_xchg per_init_feat_xchg; 907 struct pdu_data_llctrl_conn_param_req conn_param_req; 908 struct pdu_data_llctrl_conn_param_rsp conn_param_rsp; 909 struct pdu_data_llctrl_reject_ext_ind reject_ext_ind; 910 struct pdu_data_llctrl_ping_req ping_req; 911 struct pdu_data_llctrl_ping_rsp ping_rsp; 912 struct pdu_data_llctrl_length_req length_req; 913 struct pdu_data_llctrl_length_rsp length_rsp; 914 struct pdu_data_llctrl_phy_req phy_req; 915 struct pdu_data_llctrl_phy_rsp phy_rsp; 916 struct pdu_data_llctrl_phy_upd_ind phy_upd_ind; 917 struct pdu_data_llctrl_min_used_chans_ind min_used_chans_ind; 918 struct pdu_data_llctrl_cte_req cte_req; 919 struct pdu_data_llctrl_cte_rsp cte_rsp; 920 struct pdu_data_llctrl_clock_accuracy_req clock_accuracy_req; 921 struct pdu_data_llctrl_clock_accuracy_rsp clock_accuracy_rsp; 922 struct pdu_data_llctrl_cis_req cis_req; 923 struct pdu_data_llctrl_cis_rsp cis_rsp; 924 struct pdu_data_llctrl_cis_ind cis_ind; 925 struct pdu_data_llctrl_cis_terminate_ind cis_terminate_ind; 926 } __packed; 927 } __packed; 928 929 #define PDU_DATA_LLCTRL_LEN(type) (offsetof(struct pdu_data_llctrl, type) + \ 930 sizeof(struct pdu_data_llctrl_ ## type)) 931 932 #if defined(CONFIG_BT_CTLR_PROFILE_ISR) 933 struct profile { 934 uint8_t lcur; 935 uint8_t lmin; 936 uint8_t lmax; 937 uint8_t cur; 938 uint8_t min; 939 uint8_t max; 940 uint8_t radio; 941 uint8_t lll; 942 uint8_t ull_high; 943 uint8_t ull_low; 944 } __packed; 945 #endif /* CONFIG_BT_CTLR_PROFILE_ISR */ 946 947 struct pdu_data { 948 #ifdef CONFIG_LITTLE_ENDIAN 949 uint8_t ll_id:2; 950 uint8_t nesn:1; 951 uint8_t sn:1; 952 uint8_t md:1; 953 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_TX) || defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX) 954 uint8_t cp:1; 955 uint8_t rfu:2; 956 #else 957 uint8_t rfu:3; 958 #endif 959 #else 960 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_TX) || defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX) 961 uint8_t rfu:2; 962 uint8_t cp:1; 963 #else 964 uint8_t rfu:3; 965 #endif 966 uint8_t md:1; 967 uint8_t sn:1; 968 uint8_t nesn:1; 969 uint8_t ll_id:2; 970 #endif /* CONFIG_LITTLE_ENDIAN */ 971 972 uint8_t len; 973 974 struct pdu_data_vnd_octet3 octet3; 975 976 union { 977 struct pdu_data_llctrl llctrl; 978 uint8_t lldata[0]; 979 980 #if defined(CONFIG_BT_CTLR_CONN_RSSI) 981 uint8_t rssi; 982 #endif /* CONFIG_BT_CTLR_CONN_RSSI */ 983 984 #if defined(CONFIG_BT_CTLR_PROFILE_ISR) 985 struct profile profile; 986 #endif /* CONFIG_BT_CTLR_PROFILE_ISR */ 987 } __packed; 988 } __packed; 989 990 /* Generic ISO pdu, could be CIS or BIS 991 * To be used when referring to component without knowing CIS or BIS type 992 */ 993 struct pdu_iso { 994 #ifdef CONFIG_LITTLE_ENDIAN 995 uint8_t ll_id:2; 996 uint8_t hdr_other:6; 997 #else 998 uint8_t hdr_other:6; 999 uint8_t ll_id:2; 1000 #endif /* CONFIG_LITTLE_ENDIAN */ 1001 1002 uint8_t len; 1003 1004 struct pdu_iso_vnd_octet3 octet3; 1005 1006 uint8_t payload[0]; 1007 } __packed; 1008 1009 /* ISO SDU segmentation header */ 1010 #define PDU_ISO_SEG_HDR_SIZE 2 1011 #define PDU_ISO_SEG_TIMEOFFSET_SIZE 3 1012 1013 struct pdu_iso_sdu_sh { 1014 #ifdef CONFIG_LITTLE_ENDIAN 1015 uint8_t sc:1; 1016 uint8_t cmplt:1; 1017 uint8_t rfu:6; 1018 1019 uint8_t len; 1020 /* Note, timeoffset only available in first segment of sdu */ 1021 uint32_t timeoffset:24; 1022 uint32_t payload:8; 1023 #else 1024 uint8_t rfu:6; 1025 uint8_t cmplt:1; 1026 uint8_t sc:1; 1027 1028 uint8_t len; 1029 1030 /* Note, timeoffset only available in first segment of sdu */ 1031 uint32_t timeoffset:24; 1032 uint32_t payload:8; 1033 #endif /* CONFIG_LITTLE_ENDIAN */ 1034 } __packed; 1035 1036 enum pdu_cis_llid { 1037 /** Unframed complete or end fragment */ 1038 PDU_CIS_LLID_COMPLETE_END = 0x00, 1039 /** Unframed start or continuation fragment */ 1040 PDU_CIS_LLID_START_CONTINUE = 0x01, 1041 /** Framed; one or more segments of a SDU */ 1042 PDU_CIS_LLID_FRAMED = 0x02 1043 }; 1044 1045 struct pdu_cis { 1046 #ifdef CONFIG_LITTLE_ENDIAN 1047 uint8_t ll_id:2; 1048 uint8_t nesn:1; 1049 uint8_t sn:1; 1050 uint8_t cie:1; 1051 uint8_t rfu0:1; 1052 uint8_t npi:1; 1053 uint8_t rfu1:1; 1054 #else 1055 uint8_t rfu1:1; 1056 uint8_t npi:1; 1057 uint8_t rfu0:1; 1058 uint8_t cie:1; 1059 uint8_t sn:1; 1060 uint8_t nesn:1; 1061 uint8_t ll_id:2; 1062 #endif /* CONFIG_LITTLE_ENDIAN */ 1063 1064 uint8_t len; 1065 1066 struct pdu_cis_vnd_octet3 octet3; 1067 1068 uint8_t payload[0]; 1069 } __packed; 1070 1071 enum pdu_big_ctrl_type { 1072 PDU_BIG_CTRL_TYPE_CHAN_MAP_IND = 0x00, 1073 PDU_BIG_CTRL_TYPE_TERM_IND = 0x01, 1074 }; 1075 1076 struct pdu_big_ctrl_chan_map_ind { 1077 uint8_t chm[PDU_CHANNEL_MAP_SIZE]; 1078 uint16_t instant; 1079 } __packed; 1080 1081 struct pdu_big_ctrl_term_ind { 1082 uint8_t reason; 1083 uint16_t instant; 1084 } __packed; 1085 1086 1087 struct pdu_big_ctrl { 1088 uint8_t opcode; 1089 union { 1090 uint8_t ctrl_data[0]; 1091 struct pdu_big_ctrl_chan_map_ind chan_map_ind; 1092 struct pdu_big_ctrl_term_ind term_ind; 1093 } __packed; 1094 } __packed; 1095 1096 enum pdu_bis_llid { 1097 /** Unframed complete or end fragment */ 1098 PDU_BIS_LLID_COMPLETE_END = 0x00, 1099 /** Unframed start or continuation fragment */ 1100 PDU_BIS_LLID_START_CONTINUE = 0x01, 1101 /** Framed; one or more segments of a SDU */ 1102 PDU_BIS_LLID_FRAMED = 0x02, 1103 /** BIG Control PDU */ 1104 PDU_BIS_LLID_CTRL = 0x03, 1105 }; 1106 1107 struct pdu_bis { 1108 #ifdef CONFIG_LITTLE_ENDIAN 1109 uint8_t ll_id:2; 1110 uint8_t cssn:3; 1111 uint8_t cstf:1; 1112 uint8_t rfu:2; 1113 #else 1114 uint8_t rfu:2; 1115 uint8_t cstf:1; 1116 uint8_t cssn:3; 1117 uint8_t ll_id:2; 1118 #endif /* CONFIG_LITTLE_ENDIAN */ 1119 1120 uint8_t len; 1121 1122 struct pdu_bis_vnd_octet3 octet3; 1123 1124 union { 1125 uint8_t payload[0]; 1126 struct pdu_big_ctrl ctrl; 1127 } __packed; 1128 } __packed; 1129 1130 struct pdu_big_info { 1131 #ifdef CONFIG_LITTLE_ENDIAN 1132 uint32_t offs:14; 1133 uint32_t offs_units:1; 1134 uint32_t iso_interval:12; 1135 uint32_t num_bis:5; 1136 1137 uint32_t nse:5; 1138 uint32_t bn:3; 1139 uint32_t sub_interval:20; 1140 uint32_t pto:4; 1141 1142 uint32_t spacing:20; 1143 uint32_t irc:4; 1144 uint32_t max_pdu:8; 1145 1146 uint8_t rfu; 1147 1148 uint32_t seed_access_addr; 1149 1150 uint32_t sdu_interval:20; 1151 uint32_t max_sdu:12; 1152 #else 1153 uint32_t num_bis:5; 1154 uint32_t iso_interval:12; 1155 uint32_t offs_units:1; 1156 uint32_t offs:14; 1157 1158 uint32_t pto:4; 1159 uint32_t sub_interval:20; 1160 uint32_t bn:3; 1161 uint32_t nse:5; 1162 1163 uint32_t max_pdu:8; 1164 uint32_t irc:4; 1165 uint32_t spacing:20; 1166 1167 uint8_t rfu; 1168 1169 uint32_t seed_access_addr; 1170 1171 uint32_t max_sdu:12; 1172 uint32_t sdu_interval:20; 1173 #endif /* CONFIG_LITTLE_ENDIAN */ 1174 1175 uint16_t base_crc_init; 1176 1177 uint8_t chm_phy[PDU_CHANNEL_MAP_SIZE]; /* 37 bit chm; 3 bit phy */ 1178 uint8_t payload_count_framing[5]; /* 39 bit count; 1 bit framing */ 1179 1180 uint8_t giv[8]; /* encryption required */ 1181 uint8_t gskd[16]; /* encryption required */ 1182 } __packed; 1183 #define PDU_BIG_INFO_CLEARTEXT_SIZE offsetof(struct pdu_big_info, giv) 1184 #define PDU_BIG_INFO_ENCRYPTED_SIZE sizeof(struct pdu_big_info) 1185 #define PDU_BIG_BN_MAX 0x07 1186 #define PDU_BIG_PAYLOAD_COUNT_MAX 28 1187 1188 struct pdu_dtm { 1189 #ifdef CONFIG_LITTLE_ENDIAN 1190 uint8_t type:4; 1191 uint8_t rfu0:1; 1192 #if defined(CONFIG_BT_CTLR_DF_CTE_TX) 1193 uint8_t cp:1; 1194 uint8_t rfu1:2; 1195 #else 1196 uint8_t rfu1:3; 1197 #endif 1198 #else 1199 #if defined(CONFIG_BT_CTLR_DF_CTE_TX) 1200 uint8_t rfu1:2; 1201 uint8_t cp:1; 1202 #else 1203 uint8_t rfu1:3; 1204 #endif 1205 uint8_t rfu0:1; 1206 uint8_t type:4; 1207 #endif /* CONFIG_LITTLE_ENDIAN */ 1208 1209 uint8_t len; 1210 1211 struct pdu_data_vnd_octet3 octet3; 1212 1213 uint8_t payload[0]; 1214 } __packed; 1215 1216 /* Direct Test Mode maximum payload size */ 1217 #define PDU_DTM_PAYLOAD_SIZE_MAX 255 1218
