1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /*******************************************************************************************************************//** 8 * @ingroup RENESAS_NETWORKING_INTERFACES 9 * @defgroup ETHER_PHY_API Ethernet PHY Interface 10 * @brief Interface for Ethernet PHY functions. 11 * 12 * @section ETHER_PHY_API_Summary Summary 13 * The Ethernet PHY module (r_ether_phy) provides an API for standard Ethernet PHY communications applications that use 14 * the ETHERC peripheral. 15 * 16 * The Ethernet PHY interface supports the following features: 17 * - Auto negotiation support 18 * - Flow control support 19 * - Link status check support 20 * 21 * 22 * @{ 23 **********************************************************************************************************************/ 24 25 #ifndef R_ETHER_PHY_API_H 26 #define R_ETHER_PHY_API_H 27 28 /*********************************************************************************************************************** 29 * Includes 30 **********************************************************************************************************************/ 31 32 /* Register definitions, common services and error codes. */ 33 #include "bsp_api.h" 34 35 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 36 FSP_HEADER 37 38 /********************************************************************************************************************** 39 * Macro definitions 40 **********************************************************************************************************************/ 41 42 /********************************************************************************************************************** 43 * Typedef definitions 44 **********************************************************************************************************************/ 45 46 #ifndef BSP_OVERRIDE_ETHER_PHY_LSI_TYPE_T 47 48 /** Phy LSI */ 49 typedef enum e_ether_phy_lsi_type 50 { 51 ETHER_PHY_LSI_TYPE_DEFAULT = 0, ///< Select default configuration. This type dose not change Phy LSI default setting by strapping option. 52 ETHER_PHY_LSI_TYPE_KSZ8091RNB = 1, ///< Select configuration for KSZ8091RNB. 53 ETHER_PHY_LSI_TYPE_KSZ8041 = 2, ///< Select configuration for KSZ8041. 54 ETHER_PHY_LSI_TYPE_DP83620 = 3, ///< Select configuration for DP83620. 55 ETHER_PHY_LSI_TYPE_ICS1894 = 4, ///< Select configuration for ICS1894. 56 ETHER_PHY_LSI_TYPE_CUSTOM = 0xFFU, ///< Select configuration for User custom. 57 } ether_phy_lsi_type_t; 58 #endif 59 60 /** Flow control functionality */ 61 typedef enum e_ether_phy_flow_control 62 { 63 ETHER_PHY_FLOW_CONTROL_DISABLE = 0, ///< Disable flow control functionality 64 ETHER_PHY_FLOW_CONTROL_ENABLE = 1, ///< Enable flow control functionality with pause frames 65 } ether_phy_flow_control_t; 66 67 /** Link speed */ 68 typedef enum e_ether_phy_link_speed 69 { 70 ETHER_PHY_LINK_SPEED_NO_LINK = 0, ///< Link is not established 71 ETHER_PHY_LINK_SPEED_10H = 1, ///< Link status is 10Mbit/s and half duplex 72 ETHER_PHY_LINK_SPEED_10F = 2, ///< Link status is 10Mbit/s and full duplex 73 ETHER_PHY_LINK_SPEED_100H = 3, ///< Link status is 100Mbit/s and half duplex 74 ETHER_PHY_LINK_SPEED_100F = 4, ///< Link status is 100Mbit/s and full duplex 75 ETHER_PHY_LINK_SPEED_1000H = 5, ///< Link status is 1000Mbit/s and half duplex 76 ETHER_PHY_LINK_SPEED_1000F = 6 ///< Link status is 1000Mbit/s and full duplex 77 } ether_phy_link_speed_t; 78 79 /** Media-independent interface */ 80 typedef enum e_ether_phy_mii_type 81 { 82 ETHER_PHY_MII_TYPE_MII = 0, ///< MII 83 ETHER_PHY_MII_TYPE_RMII = 1, ///< RMII 84 ETHER_PHY_MII_TYPE_GMII = 2, ///< GMII 85 ETHER_PHY_MII_TYPE_RGMII = 3 ///< RGMII 86 } ether_phy_mii_type_t; 87 88 /** Control block. Allocate an instance specific control block to pass into the API calls. 89 */ 90 typedef void ether_phy_ctrl_t; 91 92 /** Configuration parameters. */ 93 typedef struct st_ether_phy_cfg 94 { 95 uint8_t channel; ///< Channel 96 uint8_t phy_lsi_address; ///< Address of PHY-LSI 97 98 uint32_t phy_reset_wait_time; ///< Wait time for PHY-LSI reboot 99 int32_t mii_bit_access_wait_time; ///< Wait time for MII/RMII access 100 ether_phy_lsi_type_t phy_lsi_type; ///< Phy LSI type 101 102 ether_phy_flow_control_t flow_control; ///< Flow control functionally enable or disable 103 ether_phy_mii_type_t mii_type; ///< Interface type is MII or RMII 104 105 /** Placeholder for user data. Passed to the user callback in ether_phy_callback_args_t. */ 106 void const * p_context; 107 void const * p_extend; ///< Placeholder for user extension. 108 } ether_phy_cfg_t; 109 110 /** Functions implemented at the HAL layer will follow this API. */ 111 typedef struct st_ether_phy_api 112 { 113 /** Open driver. 114 * 115 * @param[in] p_ctrl Pointer to control structure. 116 * @param[in] p_cfg Pointer to pin configuration structure. 117 */ 118 fsp_err_t (* open)(ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg); 119 120 /** Close driver. 121 * 122 * @param[in] p_ctrl Pointer to control structure. 123 */ 124 fsp_err_t (* close)(ether_phy_ctrl_t * const p_ctrl); 125 126 /** Initialize PHY-LSI. 127 * 128 * @param[in] p_ctrl Pointer to control structure. 129 * @param[in] p_cfg Pointer to pin configuration structure. 130 */ 131 fsp_err_t (* chipInit)(ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t const * const p_cfg); 132 133 /** Read register value of PHY-LSI. 134 * 135 * @param[in] p_ctrl Pointer to control structure. 136 * @param[in] reg_addr Register address. 137 * @param[out] p_data Pointer to the location to store read data. 138 */ 139 fsp_err_t (* read)(ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t * const p_data); 140 141 /** Write data to register of PHY-LSI. 142 * 143 * @param[in] p_ctrl Pointer to control structure. 144 * @param[in] reg_addr Register address. 145 * @param[in] data Data written to register. 146 */ 147 fsp_err_t (* write)(ether_phy_ctrl_t * const p_ctrl, uint32_t reg_addr, uint32_t data); 148 149 /** Start auto negotiation. 150 * 151 * @param[in] p_ctrl Pointer to control structure. 152 */ 153 fsp_err_t (* startAutoNegotiate)(ether_phy_ctrl_t * const p_ctrl); 154 155 /** Get the partner ability. 156 * 157 * @param[in] p_ctrl Pointer to control structure. 158 * @param[out] p_line_speed_duplex Pointer to the location of both the line speed and the duplex. 159 * @param[out] p_local_pause Pointer to the location to store the local pause bits. 160 * @param[out] p_partner_pause Pointer to the location to store the partner pause bits. 161 */ 162 fsp_err_t (* linkPartnerAbilityGet)(ether_phy_ctrl_t * const p_ctrl, uint32_t * const p_line_speed_duplex, 163 uint32_t * const p_local_pause, uint32_t * const p_partner_pause); 164 165 /** Get Link status from PHY-LSI interface. 166 * 167 * @param[in] p_ctrl Pointer to control structure. 168 */ 169 fsp_err_t (* linkStatusGet)(ether_phy_ctrl_t * const p_ctrl); 170 } ether_phy_api_t; 171 172 /** This structure encompasses everything that is needed to use an instance of this interface. */ 173 typedef struct st_ether_phy_instance 174 { 175 ether_phy_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance 176 ether_phy_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance 177 ether_phy_api_t const * p_api; ///< Pointer to the API structure for this instance 178 } ether_phy_instance_t; 179 180 /*******************************************************************************************************************//** 181 * @} (end defgroup ETHER_PHY_API) 182 **********************************************************************************************************************/ 183 184 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 185 FSP_FOOTER 186 187 #endif /* R_ETHER_PHY_API_H */ 188
