1 /*
2 * Copyright (c) 2020 PHYTEC Messtechnik GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/logging/log.h>
8 LOG_MODULE_REGISTER(dw1000, LOG_LEVEL_INF);
9
10 #include <errno.h>
11 #include <zephyr/kernel.h>
12 #include <zephyr/arch/cpu.h>
13 #include <zephyr/debug/stack.h>
14 #include <zephyr/device.h>
15 #include <zephyr/init.h>
16 #include <zephyr/net/net_if.h>
17 #include <zephyr/net/net_pkt.h>
18
19 #include <zephyr/sys/byteorder.h>
20 #include <string.h>
21 #include <zephyr/random/random.h>
22 #include <zephyr/debug/stack.h>
23 #include <math.h>
24
25 #include <zephyr/drivers/gpio.h>
26 #include <zephyr/drivers/spi.h>
27
28 #include <zephyr/net/ieee802154_radio.h>
29 #include "ieee802154_dw1000_regs.h"
30
31 #define DT_DRV_COMPAT decawave_dw1000
32
33 #define DWT_FCS_LENGTH 2U
34 #define DWT_SPI_CSWAKEUP_FREQ 500000U
35 #define DWT_SPI_SLOW_FREQ 2000000U
36 #define DWT_SPI_TRANS_MAX_HDR_LEN 3
37 #define DWT_SPI_TRANS_REG_MAX_RANGE 0x3F
38 #define DWT_SPI_TRANS_SHORT_MAX_OFFSET 0x7F
39 #define DWT_SPI_TRANS_WRITE_OP BIT(7)
40 #define DWT_SPI_TRANS_SUB_ADDR BIT(6)
41 #define DWT_SPI_TRANS_EXTEND_ADDR BIT(7)
42
43 #define DWT_TS_TIME_UNITS_FS 15650U /* DWT_TIME_UNITS in fs */
44
45 #define DW1000_TX_ANT_DLY 16450
46 #define DW1000_RX_ANT_DLY 16450
47
48 /* SHR Symbol Duration in ns */
49 #define UWB_PHY_TPSYM_PRF64 IEEE802154_PHY_HRP_UWB_PRF64_TPSYM_SYMBOL_PERIOD_NS
50 #define UWB_PHY_TPSYM_PRF16 IEEE802154_PHY_HRP_UWB_PRF16_TPSYM_SYMBOL_PERIOD_NS
51
52 #define UWB_PHY_NUMOF_SYM_SHR_SFD 8
53
54 /* PHR Symbol Duration Tdsym in ns */
55 #define UWB_PHY_TDSYM_PHR_110K 8205.13
56 #define UWB_PHY_TDSYM_PHR_850K 1025.64
57 #define UWB_PHY_TDSYM_PHR_6M8 1025.64
58
59 #define UWB_PHY_NUMOF_SYM_PHR 18
60
61 /* Data Symbol Duration Tdsym in ns */
62 #define UWB_PHY_TDSYM_DATA_110K 8205.13
63 #define UWB_PHY_TDSYM_DATA_850K 1025.64
64 #define UWB_PHY_TDSYM_DATA_6M8 128.21
65
66 #define DWT_WORK_QUEUE_STACK_SIZE 512
67
68 static struct k_work_q dwt_work_queue;
69 static K_KERNEL_STACK_DEFINE(dwt_work_queue_stack,
70 DWT_WORK_QUEUE_STACK_SIZE);
71
72 struct dwt_phy_config {
73 uint8_t channel; /* Channel 1, 2, 3, 4, 5, 7 */
74 uint8_t dr; /* Data rate DWT_BR_110K, DWT_BR_850K, DWT_BR_6M8 */
75 uint8_t prf; /* PRF DWT_PRF_16M or DWT_PRF_64M */
76
77 uint8_t rx_pac_l; /* DWT_PAC8..DWT_PAC64 */
78 uint8_t rx_shr_code; /* RX SHR preamble code */
79 uint8_t rx_ns_sfd; /* non-standard SFD */
80 uint16_t rx_sfd_to; /* SFD timeout value (in symbols)
81 * (tx_shr_nsync + 1 + SFD_length - rx_pac_l)
82 */
83
84 uint8_t tx_shr_code; /* TX SHR preamble code */
85 uint32_t tx_shr_nsync; /* PLEN index, e.g. DWT_PLEN_64 */
86
87 float t_shr;
88 float t_phr;
89 float t_dsym;
90 };
91
92 struct dwt_hi_cfg {
93 struct spi_dt_spec bus;
94 struct gpio_dt_spec irq_gpio;
95 struct gpio_dt_spec rst_gpio;
96 };
97
98 #define DWT_STATE_TX 0
99 #define DWT_STATE_CCA 1
100 #define DWT_STATE_RX_DEF_ON 2
101
102 struct dwt_context {
103 const struct device *dev;
104 struct net_if *iface;
105 const struct spi_config *spi_cfg;
106 struct spi_config spi_cfg_slow;
107 struct gpio_callback gpio_cb;
108 struct k_sem dev_lock;
109 struct k_sem phy_sem;
110 struct k_work irq_cb_work;
111 struct k_thread thread;
112 struct dwt_phy_config rf_cfg;
113 atomic_t state;
114 bool cca_busy;
115 uint16_t sleep_mode;
116 uint8_t mac_addr[8];
117 };
118
119 static const struct dwt_hi_cfg dw1000_0_config = {
120 .bus = SPI_DT_SPEC_INST_GET(0, SPI_WORD_SET(8), 0),
121 .irq_gpio = GPIO_DT_SPEC_INST_GET(0, int_gpios),
122 .rst_gpio = GPIO_DT_SPEC_INST_GET(0, reset_gpios),
123 };
124
125 static struct dwt_context dwt_0_context = {
126 .dev_lock = Z_SEM_INITIALIZER(dwt_0_context.dev_lock, 1, 1),
127 .phy_sem = Z_SEM_INITIALIZER(dwt_0_context.phy_sem, 0, 1),
128 .rf_cfg = {
129 .channel = 5,
130 .dr = DWT_BR_6M8,
131 .prf = DWT_PRF_64M,
132
133 .rx_pac_l = DWT_PAC8,
134 .rx_shr_code = 10,
135 .rx_ns_sfd = 0,
136 .rx_sfd_to = (129 + 8 - 8),
137
138 .tx_shr_code = 10,
139 .tx_shr_nsync = DWT_PLEN_128,
140 },
141 };
142
143 /* This struct is used to read all additional RX frame info at one push */
144 struct dwt_rx_info_regs {
145 uint8_t rx_fqual[DWT_RX_FQUAL_LEN];
146 uint8_t rx_ttcki[DWT_RX_TTCKI_LEN];
147 uint8_t rx_ttcko[DWT_RX_TTCKO_LEN];
148 /* RX_TIME without RX_RAWST */
149 uint8_t rx_time[DWT_RX_TIME_FP_RAWST_OFFSET];
150 } _packed;
151
152 static int dwt_configure_rf_phy(const struct device *dev);
153
dwt_spi_read(const struct device * dev,uint16_t hdr_len,const uint8_t * hdr_buf,uint32_t data_len,uint8_t * data)154 static int dwt_spi_read(const struct device *dev,
155 uint16_t hdr_len, const uint8_t *hdr_buf,
156 uint32_t data_len, uint8_t *data)
157 {
158 struct dwt_context *ctx = dev->data;
159 const struct dwt_hi_cfg *hi_cfg = dev->config;
160 const struct spi_buf tx_buf = {
161 .buf = (uint8_t *)hdr_buf,
162 .len = hdr_len
163 };
164 const struct spi_buf_set tx = {
165 .buffers = &tx_buf,
166 .count = 1
167 };
168 struct spi_buf rx_buf[2] = {
169 {
170 .buf = NULL,
171 .len = hdr_len,
172 },
173 {
174 .buf = (uint8_t *)data,
175 .len = data_len,
176 },
177 };
178 const struct spi_buf_set rx = {
179 .buffers = rx_buf,
180 .count = 2
181 };
182
183 LOG_DBG("spi read, header length %u, data length %u",
184 (uint16_t)hdr_len, (uint32_t)data_len);
185 LOG_HEXDUMP_DBG(hdr_buf, (uint16_t)hdr_len, "rd: header");
186
187 if (spi_transceive(hi_cfg->bus.bus, ctx->spi_cfg, &tx, &rx)) {
188 LOG_ERR("SPI transfer failed");
189 return -EIO;
190 }
191
192 LOG_HEXDUMP_DBG(data, (uint32_t)data_len, "rd: data");
193
194 return 0;
195 }
196
197
dwt_spi_write(const struct device * dev,uint16_t hdr_len,const uint8_t * hdr_buf,uint32_t data_len,const uint8_t * data)198 static int dwt_spi_write(const struct device *dev,
199 uint16_t hdr_len, const uint8_t *hdr_buf,
200 uint32_t data_len, const uint8_t *data)
201 {
202 struct dwt_context *ctx = dev->data;
203 const struct dwt_hi_cfg *hi_cfg = dev->config;
204 struct spi_buf buf[2] = {
205 {.buf = (uint8_t *)hdr_buf, .len = hdr_len},
206 {.buf = (uint8_t *)data, .len = data_len}
207 };
208 struct spi_buf_set buf_set = {.buffers = buf, .count = 2};
209
210 LOG_DBG("spi write, header length %u, data length %u",
211 (uint16_t)hdr_len, (uint32_t)data_len);
212 LOG_HEXDUMP_DBG(hdr_buf, (uint16_t)hdr_len, "wr: header");
213 LOG_HEXDUMP_DBG(data, (uint32_t)data_len, "wr: data");
214
215 if (spi_write(hi_cfg->bus.bus, ctx->spi_cfg, &buf_set)) {
216 LOG_ERR("SPI read failed");
217 return -EIO;
218 }
219
220 return 0;
221 }
222
223 /* See 2.2.1.2 Transaction formats of the SPI interface */
dwt_spi_transfer(const struct device * dev,uint8_t reg,uint16_t offset,size_t buf_len,uint8_t * buf,bool write)224 static int dwt_spi_transfer(const struct device *dev,
225 uint8_t reg, uint16_t offset,
226 size_t buf_len, uint8_t *buf, bool write)
227 {
228 uint8_t hdr[DWT_SPI_TRANS_MAX_HDR_LEN] = {0};
229 size_t hdr_len = 0;
230
231 hdr[0] = reg & DWT_SPI_TRANS_REG_MAX_RANGE;
232 hdr_len += 1;
233
234 if (offset != 0) {
235 hdr[0] |= DWT_SPI_TRANS_SUB_ADDR;
236 hdr[1] = (uint8_t)offset & DWT_SPI_TRANS_SHORT_MAX_OFFSET;
237 hdr_len += 1;
238
239 if (offset > DWT_SPI_TRANS_SHORT_MAX_OFFSET) {
240 hdr[1] |= DWT_SPI_TRANS_EXTEND_ADDR;
241 hdr[2] = (uint8_t)(offset >> 7);
242 hdr_len += 1;
243 }
244
245 }
246
247 if (write) {
248 hdr[0] |= DWT_SPI_TRANS_WRITE_OP;
249 return dwt_spi_write(dev, hdr_len, hdr, buf_len, buf);
250 } else {
251 return dwt_spi_read(dev, hdr_len, hdr, buf_len, buf);
252 }
253 }
254
dwt_register_read(const struct device * dev,uint8_t reg,uint16_t offset,size_t buf_len,uint8_t * buf)255 static int dwt_register_read(const struct device *dev,
256 uint8_t reg, uint16_t offset, size_t buf_len, uint8_t *buf)
257 {
258 return dwt_spi_transfer(dev, reg, offset, buf_len, buf, false);
259 }
260
dwt_register_write(const struct device * dev,uint8_t reg,uint16_t offset,size_t buf_len,uint8_t * buf)261 static int dwt_register_write(const struct device *dev,
262 uint8_t reg, uint16_t offset, size_t buf_len, uint8_t *buf)
263 {
264 return dwt_spi_transfer(dev, reg, offset, buf_len, buf, true);
265 }
266
dwt_reg_read_u32(const struct device * dev,uint8_t reg,uint16_t offset)267 static inline uint32_t dwt_reg_read_u32(const struct device *dev,
268 uint8_t reg, uint16_t offset)
269 {
270 uint8_t buf[sizeof(uint32_t)];
271
272 dwt_spi_transfer(dev, reg, offset, sizeof(buf), buf, false);
273
274 return sys_get_le32(buf);
275 }
276
dwt_reg_read_u8(const struct device * dev,uint8_t reg,uint16_t offset)277 static inline uint8_t dwt_reg_read_u8(const struct device *dev,
278 uint8_t reg, uint16_t offset)
279 {
280 uint8_t buf;
281
282 dwt_spi_transfer(dev, reg, offset, sizeof(buf), &buf, false);
283
284 return buf;
285 }
286
dwt_reg_write_u32(const struct device * dev,uint8_t reg,uint16_t offset,uint32_t val)287 static inline void dwt_reg_write_u32(const struct device *dev,
288 uint8_t reg, uint16_t offset, uint32_t val)
289 {
290 uint8_t buf[sizeof(uint32_t)];
291
292 sys_put_le32(val, buf);
293 dwt_spi_transfer(dev, reg, offset, sizeof(buf), buf, true);
294 }
295
dwt_reg_write_u16(const struct device * dev,uint8_t reg,uint16_t offset,uint16_t val)296 static inline void dwt_reg_write_u16(const struct device *dev,
297 uint8_t reg, uint16_t offset, uint16_t val)
298 {
299 uint8_t buf[sizeof(uint16_t)];
300
301 sys_put_le16(val, buf);
302 dwt_spi_transfer(dev, reg, offset, sizeof(buf), buf, true);
303 }
304
dwt_reg_write_u8(const struct device * dev,uint8_t reg,uint16_t offset,uint8_t val)305 static inline void dwt_reg_write_u8(const struct device *dev,
306 uint8_t reg, uint16_t offset, uint8_t val)
307 {
308 dwt_spi_transfer(dev, reg, offset, sizeof(uint8_t), &val, true);
309 }
310
dwt_setup_int(const struct device * dev,bool enable)311 static ALWAYS_INLINE void dwt_setup_int(const struct device *dev,
312 bool enable)
313 {
314 const struct dwt_hi_cfg *hi_cfg = dev->config;
315
316 unsigned int flags = enable
317 ? GPIO_INT_EDGE_TO_ACTIVE
318 : GPIO_INT_DISABLE;
319
320 gpio_pin_interrupt_configure_dt(&hi_cfg->irq_gpio, flags);
321 }
322
dwt_reset_rfrx(const struct device * dev)323 static void dwt_reset_rfrx(const struct device *dev)
324 {
325 /*
326 * Apply a receiver-only soft reset,
327 * see SOFTRESET field description in DW1000 User Manual.
328 */
329 dwt_reg_write_u8(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_SOFTRESET_OFFSET,
330 DWT_PMSC_CTRL0_RESET_RX);
331 dwt_reg_write_u8(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_SOFTRESET_OFFSET,
332 DWT_PMSC_CTRL0_RESET_CLEAR);
333 }
334
dwt_disable_txrx(const struct device * dev)335 static void dwt_disable_txrx(const struct device *dev)
336 {
337 dwt_setup_int(dev, false);
338
339 dwt_reg_write_u8(dev, DWT_SYS_CTRL_ID, DWT_SYS_CTRL_OFFSET,
340 DWT_SYS_CTRL_TRXOFF);
341
342 dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, DWT_SYS_STATUS_OFFSET,
343 (DWT_SYS_STATUS_ALL_RX_GOOD |
344 DWT_SYS_STATUS_ALL_RX_TO |
345 DWT_SYS_STATUS_ALL_RX_ERR |
346 DWT_SYS_STATUS_ALL_TX));
347
348 dwt_setup_int(dev, true);
349 }
350
351 /* timeout time in units of 1.026 microseconds */
dwt_enable_rx(const struct device * dev,uint16_t timeout)352 static int dwt_enable_rx(const struct device *dev, uint16_t timeout)
353 {
354 uint32_t sys_cfg;
355 uint16_t sys_ctrl = DWT_SYS_CTRL_RXENAB;
356
357 sys_cfg = dwt_reg_read_u32(dev, DWT_SYS_CFG_ID, 0);
358
359 if (timeout != 0) {
360 dwt_reg_write_u16(dev, DWT_RX_FWTO_ID, DWT_RX_FWTO_OFFSET,
361 timeout);
362 sys_cfg |= DWT_SYS_CFG_RXWTOE;
363 } else {
364 sys_cfg &= ~DWT_SYS_CFG_RXWTOE;
365 }
366
367 dwt_reg_write_u32(dev, DWT_SYS_CFG_ID, 0, sys_cfg);
368 dwt_reg_write_u16(dev, DWT_SYS_CTRL_ID, DWT_SYS_CTRL_OFFSET, sys_ctrl);
369
370 return 0;
371 }
372
dwt_irq_handle_rx_cca(const struct device * dev)373 static inline void dwt_irq_handle_rx_cca(const struct device *dev)
374 {
375 struct dwt_context *ctx = dev->data;
376
377 k_sem_give(&ctx->phy_sem);
378 ctx->cca_busy = true;
379
380 /* Clear all RX event bits */
381 dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0,
382 DWT_SYS_STATUS_ALL_RX_GOOD);
383 }
384
dwt_irq_handle_rx(const struct device * dev,uint32_t sys_stat)385 static inline void dwt_irq_handle_rx(const struct device *dev, uint32_t sys_stat)
386 {
387 struct dwt_context *ctx = dev->data;
388 struct net_pkt *pkt = NULL;
389 struct dwt_rx_info_regs rx_inf_reg;
390 float a_const;
391 uint32_t rx_finfo;
392 uint32_t ttcki;
393 uint32_t rx_pacc;
394 uint32_t cir_pwr;
395 uint32_t flags_to_clear;
396 int32_t ttcko;
397 uint16_t pkt_len;
398 uint8_t *fctrl;
399 int8_t rx_level = INT8_MIN;
400
401 LOG_DBG("RX OK event, SYS_STATUS 0x%08x", sys_stat);
402 flags_to_clear = sys_stat & DWT_SYS_STATUS_ALL_RX_GOOD;
403
404 rx_finfo = dwt_reg_read_u32(dev, DWT_RX_FINFO_ID, DWT_RX_FINFO_OFFSET);
405 pkt_len = rx_finfo & DWT_RX_FINFO_RXFLEN_MASK;
406 rx_pacc = (rx_finfo & DWT_RX_FINFO_RXPACC_MASK) >>
407 DWT_RX_FINFO_RXPACC_SHIFT;
408
409 if (!IS_ENABLED(CONFIG_IEEE802154_L2_PKT_INCL_FCS)) {
410 pkt_len -= DWT_FCS_LENGTH;
411 }
412
413 pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, pkt_len,
414 AF_UNSPEC, 0, K_NO_WAIT);
415 if (!pkt) {
416 LOG_ERR("No buf available");
417 goto rx_out_enable_rx;
418 }
419
420 dwt_register_read(dev, DWT_RX_BUFFER_ID, 0, pkt_len, pkt->buffer->data);
421 dwt_register_read(dev, DWT_RX_FQUAL_ID, 0, sizeof(rx_inf_reg),
422 (uint8_t *)&rx_inf_reg);
423 net_buf_add(pkt->buffer, pkt_len);
424 fctrl = pkt->buffer->data;
425
426 /*
427 * Get Ranging tracking offset and tracking interval
428 * for Crystal characterization
429 */
430 ttcki = sys_get_le32(rx_inf_reg.rx_ttcki);
431 ttcko = sys_get_le32(rx_inf_reg.rx_ttcko) & DWT_RX_TTCKO_RXTOFS_MASK;
432 /* Tracking offset value is a 19-bit signed integer */
433 if (ttcko & BIT(18)) {
434 ttcko |= ~DWT_RX_TTCKO_RXTOFS_MASK;
435 }
436
437 /* TODO add:
438 * net_pkt_set_ieee802154_tcki(pkt, ttcki);
439 * net_pkt_set_ieee802154_tcko(pkt, ttcko);
440 */
441 LOG_DBG("ttcko %d ttcki: 0x%08x", ttcko, ttcki);
442
443 if (IS_ENABLED(CONFIG_NET_PKT_TIMESTAMP)) {
444 uint8_t ts_buf[sizeof(uint64_t)] = {0};
445 uint64_t ts_nsec;
446
447 memcpy(ts_buf, rx_inf_reg.rx_time, DWT_RX_TIME_RX_STAMP_LEN);
448 ts_nsec = (sys_get_le64(ts_buf) * DWT_TS_TIME_UNITS_FS) / 1000000U;
449 net_pkt_set_timestamp_ns(pkt, ts_nsec);
450 }
451
452 /* See 4.7.2 Estimating the receive signal power */
453 cir_pwr = sys_get_le16(&rx_inf_reg.rx_fqual[6]);
454 if (ctx->rf_cfg.prf == DWT_PRF_16M) {
455 a_const = DWT_RX_SIG_PWR_A_CONST_PRF16;
456 } else {
457 a_const = DWT_RX_SIG_PWR_A_CONST_PRF64;
458 }
459
460 if (rx_pacc != 0) {
461 #if defined(CONFIG_NEWLIB_LIBC)
462 /* From 4.7.2 Estimating the receive signal power */
463 rx_level = 10.0 * log10f(cir_pwr * BIT(17) /
464 (rx_pacc * rx_pacc)) - a_const;
465 #endif
466 }
467
468 net_pkt_set_ieee802154_rssi_dbm(pkt, rx_level);
469
470 /*
471 * Workaround for AAT status bit issue,
472 * From 5.3.5 Host Notification in DW1000 User Manual:
473 * "Note: there is a situation that can result in the AAT bit being set
474 * for the current frame as a result of a previous frame that was
475 * received and rejected due to frame filtering."
476 */
477 if ((sys_stat & DWT_SYS_STATUS_AAT) && ((fctrl[0] & 0x20) == 0)) {
478 flags_to_clear |= DWT_SYS_STATUS_AAT;
479 }
480
481 if (ieee802154_handle_ack(ctx->iface, pkt) == NET_OK) {
482 LOG_INF("ACK packet handled");
483 goto rx_out_unref_pkt;
484 }
485
486 /* LQI not implemented */
487 LOG_DBG("Caught a packet (%u) (RSSI: %d)", pkt_len, rx_level);
488 LOG_HEXDUMP_DBG(pkt->buffer->data, pkt_len, "RX buffer:");
489
490 if (net_recv_data(ctx->iface, pkt) == NET_OK) {
491 goto rx_out_enable_rx;
492 } else {
493 LOG_DBG("Packet dropped by NET stack");
494 }
495
496 rx_out_unref_pkt:
497 if (pkt) {
498 net_pkt_unref(pkt);
499 }
500
501 rx_out_enable_rx:
502 dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0, flags_to_clear);
503 LOG_DBG("Cleared SYS_STATUS flags 0x%08x", flags_to_clear);
504 if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
505 /*
506 * Re-enable reception but in contrast to dwt_enable_rx()
507 * without to read SYS_STATUS and set delayed option.
508 */
509 dwt_reg_write_u16(dev, DWT_SYS_CTRL_ID, DWT_SYS_CTRL_OFFSET,
510 DWT_SYS_CTRL_RXENAB);
511 }
512 }
513
dwt_irq_handle_tx(const struct device * dev,uint32_t sys_stat)514 static void dwt_irq_handle_tx(const struct device *dev, uint32_t sys_stat)
515 {
516 struct dwt_context *ctx = dev->data;
517
518 /* Clear TX event bits */
519 dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0,
520 DWT_SYS_STATUS_ALL_TX);
521
522 LOG_DBG("TX confirmed event");
523 k_sem_give(&ctx->phy_sem);
524 }
525
dwt_irq_handle_rxto(const struct device * dev,uint32_t sys_stat)526 static void dwt_irq_handle_rxto(const struct device *dev, uint32_t sys_stat)
527 {
528 struct dwt_context *ctx = dev->data;
529
530 /* Clear RX timeout event bits */
531 dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0,
532 DWT_SYS_STATUS_RXRFTO);
533
534 dwt_disable_txrx(dev);
535 /* Receiver reset necessary, see 4.1.6 RX Message timestamp */
536 dwt_reset_rfrx(dev);
537
538 LOG_DBG("RX timeout event");
539
540 if (atomic_test_bit(&ctx->state, DWT_STATE_CCA)) {
541 k_sem_give(&ctx->phy_sem);
542 ctx->cca_busy = false;
543 }
544 }
545
dwt_irq_handle_error(const struct device * dev,uint32_t sys_stat)546 static void dwt_irq_handle_error(const struct device *dev, uint32_t sys_stat)
547 {
548 struct dwt_context *ctx = dev->data;
549
550 /* Clear RX error event bits */
551 dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0, DWT_SYS_STATUS_ALL_RX_ERR);
552
553 dwt_disable_txrx(dev);
554 /* Receiver reset necessary, see 4.1.6 RX Message timestamp */
555 dwt_reset_rfrx(dev);
556
557 LOG_INF("RX error event");
558 if (atomic_test_bit(&ctx->state, DWT_STATE_CCA)) {
559 k_sem_give(&ctx->phy_sem);
560 ctx->cca_busy = true;
561 return;
562 }
563
564 if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
565 dwt_enable_rx(dev, 0);
566 }
567 }
568
dwt_irq_work_handler(struct k_work * item)569 static void dwt_irq_work_handler(struct k_work *item)
570 {
571 struct dwt_context *ctx = CONTAINER_OF(item, struct dwt_context,
572 irq_cb_work);
573 const struct device *dev = ctx->dev;
574 uint32_t sys_stat;
575
576 k_sem_take(&ctx->dev_lock, K_FOREVER);
577
578 sys_stat = dwt_reg_read_u32(dev, DWT_SYS_STATUS_ID, 0);
579
580 if (sys_stat & DWT_SYS_STATUS_RXFCG) {
581 if (atomic_test_bit(&ctx->state, DWT_STATE_CCA)) {
582 dwt_irq_handle_rx_cca(dev);
583 } else {
584 dwt_irq_handle_rx(dev, sys_stat);
585 }
586 }
587
588 if (sys_stat & DWT_SYS_STATUS_TXFRS) {
589 dwt_irq_handle_tx(dev, sys_stat);
590 }
591
592 if (sys_stat & DWT_SYS_STATUS_ALL_RX_TO) {
593 dwt_irq_handle_rxto(dev, sys_stat);
594 }
595
596 if (sys_stat & DWT_SYS_STATUS_ALL_RX_ERR) {
597 dwt_irq_handle_error(dev, sys_stat);
598 }
599
600 k_sem_give(&ctx->dev_lock);
601 }
602
dwt_gpio_callback(const struct device * dev,struct gpio_callback * cb,uint32_t pins)603 static void dwt_gpio_callback(const struct device *dev,
604 struct gpio_callback *cb, uint32_t pins)
605 {
606 struct dwt_context *ctx = CONTAINER_OF(cb, struct dwt_context, gpio_cb);
607
608 LOG_DBG("IRQ callback triggered %p", ctx);
609 k_work_submit_to_queue(&dwt_work_queue, &ctx->irq_cb_work);
610 }
611
dwt_get_capabilities(const struct device * dev)612 static enum ieee802154_hw_caps dwt_get_capabilities(const struct device *dev)
613 {
614 /* TODO: Implement HW-supported AUTOACK + frame pending bit handling. */
615 return IEEE802154_HW_FCS | IEEE802154_HW_FILTER |
616 IEEE802154_HW_TXTIME;
617 }
618
dwt_get_pkt_duration_ns(struct dwt_context * ctx,uint8_t psdu_len)619 static uint32_t dwt_get_pkt_duration_ns(struct dwt_context *ctx, uint8_t psdu_len)
620 {
621 struct dwt_phy_config *rf_cfg = &ctx->rf_cfg;
622 float t_psdu = rf_cfg->t_dsym * psdu_len * 8;
623
624 return (rf_cfg->t_shr + rf_cfg->t_phr + t_psdu);
625 }
626
dwt_cca(const struct device * dev)627 static int dwt_cca(const struct device *dev)
628 {
629 struct dwt_context *ctx = dev->data;
630 uint32_t cca_dur = (dwt_get_pkt_duration_ns(ctx, 127) +
631 dwt_get_pkt_duration_ns(ctx, 5)) /
632 UWB_PHY_TDSYM_PHR_6M8;
633
634 if (atomic_test_and_set_bit(&ctx->state, DWT_STATE_CCA)) {
635 LOG_ERR("Transceiver busy");
636 return -EBUSY;
637 }
638
639 /* Perform CCA Mode 5 */
640 k_sem_take(&ctx->dev_lock, K_FOREVER);
641 dwt_disable_txrx(dev);
642 LOG_DBG("CCA duration %u us", cca_dur);
643
644 dwt_enable_rx(dev, cca_dur);
645 k_sem_give(&ctx->dev_lock);
646
647 k_sem_take(&ctx->phy_sem, K_FOREVER);
648 LOG_DBG("CCA finished %p", ctx);
649
650 atomic_clear_bit(&ctx->state, DWT_STATE_CCA);
651 if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
652 k_sem_take(&ctx->dev_lock, K_FOREVER);
653 dwt_enable_rx(dev, 0);
654 k_sem_give(&ctx->dev_lock);
655 }
656
657 return ctx->cca_busy ? -EBUSY : 0;
658 }
659
dwt_ed(const struct device * dev,uint16_t duration,energy_scan_done_cb_t done_cb)660 static int dwt_ed(const struct device *dev, uint16_t duration,
661 energy_scan_done_cb_t done_cb)
662 {
663 /* TODO: see description Sub-Register 0x23:02 – AGC_CTRL1 */
664
665 return -ENOTSUP;
666 }
667
dwt_set_channel(const struct device * dev,uint16_t channel)668 static int dwt_set_channel(const struct device *dev, uint16_t channel)
669 {
670 struct dwt_context *ctx = dev->data;
671 struct dwt_phy_config *rf_cfg = &ctx->rf_cfg;
672
673 if (channel > 15) {
674 return -EINVAL;
675 }
676
677 if (channel == 0 || channel == 6 || channel > 7) {
678 return -ENOTSUP;
679 }
680
681 rf_cfg->channel = channel;
682 LOG_INF("Set channel %u", channel);
683
684 k_sem_take(&ctx->dev_lock, K_FOREVER);
685
686 dwt_disable_txrx(dev);
687 dwt_configure_rf_phy(dev);
688
689 if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
690 dwt_enable_rx(dev, 0);
691 }
692
693 k_sem_give(&ctx->dev_lock);
694
695 return 0;
696 }
697
dwt_set_pan_id(const struct device * dev,uint16_t pan_id)698 static int dwt_set_pan_id(const struct device *dev, uint16_t pan_id)
699 {
700 struct dwt_context *ctx = dev->data;
701
702 k_sem_take(&ctx->dev_lock, K_FOREVER);
703 dwt_reg_write_u16(dev, DWT_PANADR_ID, DWT_PANADR_PAN_ID_OFFSET, pan_id);
704 k_sem_give(&ctx->dev_lock);
705
706 LOG_INF("Set PAN ID 0x%04x %p", pan_id, ctx);
707
708 return 0;
709 }
710
dwt_set_short_addr(const struct device * dev,uint16_t short_addr)711 static int dwt_set_short_addr(const struct device *dev, uint16_t short_addr)
712 {
713 struct dwt_context *ctx = dev->data;
714
715 k_sem_take(&ctx->dev_lock, K_FOREVER);
716 dwt_reg_write_u16(dev, DWT_PANADR_ID, DWT_PANADR_SHORT_ADDR_OFFSET,
717 short_addr);
718 k_sem_give(&ctx->dev_lock);
719
720 LOG_INF("Set short 0x%x %p", short_addr, ctx);
721
722 return 0;
723 }
724
dwt_set_ieee_addr(const struct device * dev,const uint8_t * ieee_addr)725 static int dwt_set_ieee_addr(const struct device *dev,
726 const uint8_t *ieee_addr)
727 {
728 struct dwt_context *ctx = dev->data;
729
730 LOG_INF("IEEE address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x",
731 ieee_addr[7], ieee_addr[6], ieee_addr[5], ieee_addr[4],
732 ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0]);
733
734 k_sem_take(&ctx->dev_lock, K_FOREVER);
735 dwt_register_write(dev, DWT_EUI_64_ID, DWT_EUI_64_OFFSET,
736 DWT_EUI_64_LEN, (uint8_t *)ieee_addr);
737 k_sem_give(&ctx->dev_lock);
738
739 return 0;
740 }
741
dwt_filter(const struct device * dev,bool set,enum ieee802154_filter_type type,const struct ieee802154_filter * filter)742 static int dwt_filter(const struct device *dev,
743 bool set,
744 enum ieee802154_filter_type type,
745 const struct ieee802154_filter *filter)
746 {
747 if (!set) {
748 return -ENOTSUP;
749 }
750
751 if (type == IEEE802154_FILTER_TYPE_IEEE_ADDR) {
752 return dwt_set_ieee_addr(dev, filter->ieee_addr);
753 } else if (type == IEEE802154_FILTER_TYPE_SHORT_ADDR) {
754 return dwt_set_short_addr(dev, filter->short_addr);
755 } else if (type == IEEE802154_FILTER_TYPE_PAN_ID) {
756 return dwt_set_pan_id(dev, filter->pan_id);
757 }
758
759 return -ENOTSUP;
760 }
761
dwt_set_power(const struct device * dev,int16_t dbm)762 static int dwt_set_power(const struct device *dev, int16_t dbm)
763 {
764 struct dwt_context *ctx = dev->data;
765
766 LOG_INF("set_txpower not supported %p", ctx);
767
768 return 0;
769 }
770
dwt_tx(const struct device * dev,enum ieee802154_tx_mode tx_mode,struct net_pkt * pkt,struct net_buf * frag)771 static int dwt_tx(const struct device *dev, enum ieee802154_tx_mode tx_mode,
772 struct net_pkt *pkt, struct net_buf *frag)
773 {
774 struct dwt_context *ctx = dev->data;
775 size_t len = frag->len;
776 uint32_t tx_time = 0;
777 uint64_t tmp_fs;
778 uint32_t tx_fctrl;
779 uint8_t sys_ctrl = DWT_SYS_CTRL_TXSTRT;
780
781 if (atomic_test_and_set_bit(&ctx->state, DWT_STATE_TX)) {
782 LOG_ERR("Transceiver busy");
783 return -EBUSY;
784 }
785
786 k_sem_reset(&ctx->phy_sem);
787 k_sem_take(&ctx->dev_lock, K_FOREVER);
788
789 switch (tx_mode) {
790 case IEEE802154_TX_MODE_DIRECT:
791 break;
792 case IEEE802154_TX_MODE_TXTIME:
793 /*
794 * tx_time is the high 32-bit of the 40-bit system
795 * time value at which to send the message.
796 */
797 tmp_fs = net_pkt_timestamp_ns(pkt);
798 tmp_fs *= 1000U * 1000U;
799
800 tx_time = (tmp_fs / DWT_TS_TIME_UNITS_FS) >> 8;
801 sys_ctrl |= DWT_SYS_CTRL_TXDLYS;
802 /* DX_TIME is 40-bit register */
803 dwt_reg_write_u32(dev, DWT_DX_TIME_ID, 1, tx_time);
804
805 LOG_DBG("ntx hi32 %x", tx_time);
806 LOG_DBG("sys hi32 %x",
807 dwt_reg_read_u32(dev, DWT_SYS_TIME_ID, 1));
808 break;
809 default:
810 LOG_ERR("TX mode %d not supported", tx_mode);
811 goto error;
812 }
813
814 LOG_HEXDUMP_DBG(frag->data, len, "TX buffer:");
815
816 /*
817 * See "3 Message Transmission" in DW1000 User Manual for
818 * more details about transmission configuration.
819 */
820 if (dwt_register_write(dev, DWT_TX_BUFFER_ID, 0, len, frag->data)) {
821 LOG_ERR("Failed to write TX data");
822 goto error;
823 }
824
825 tx_fctrl = dwt_reg_read_u32(dev, DWT_TX_FCTRL_ID, 0);
826 /* Clear TX buffer index offset, frame length, and length extension */
827 tx_fctrl &= ~(DWT_TX_FCTRL_TFLEN_MASK | DWT_TX_FCTRL_TFLE_MASK |
828 DWT_TX_FCTRL_TXBOFFS_MASK);
829 /* Set frame length and ranging flag */
830 tx_fctrl |= (len + DWT_FCS_LENGTH) & DWT_TX_FCTRL_TFLEN_MASK;
831 tx_fctrl |= DWT_TX_FCTRL_TR;
832 /* Update Transmit Frame Control register */
833 dwt_reg_write_u32(dev, DWT_TX_FCTRL_ID, 0, tx_fctrl);
834
835 dwt_disable_txrx(dev);
836
837 /* Begin transmission */
838 dwt_reg_write_u8(dev, DWT_SYS_CTRL_ID, DWT_SYS_CTRL_OFFSET, sys_ctrl);
839
840 if (sys_ctrl & DWT_SYS_CTRL_TXDLYS) {
841 uint32_t sys_stat = dwt_reg_read_u32(dev, DWT_SYS_STATUS_ID, 0);
842
843 if (sys_stat & DWT_SYS_STATUS_HPDWARN) {
844 LOG_WRN("Half Period Delay Warning");
845 }
846 }
847
848 k_sem_give(&ctx->dev_lock);
849 /* Wait for the TX confirmed event */
850 k_sem_take(&ctx->phy_sem, K_FOREVER);
851
852 if (IS_ENABLED(CONFIG_NET_PKT_TIMESTAMP)) {
853 uint8_t ts_buf[sizeof(uint64_t)] = {0};
854
855 k_sem_take(&ctx->dev_lock, K_FOREVER);
856 dwt_register_read(dev, DWT_TX_TIME_ID,
857 DWT_TX_TIME_TX_STAMP_OFFSET,
858 DWT_TX_TIME_TX_STAMP_LEN,
859 ts_buf);
860 LOG_DBG("ts hi32 %x", (uint32_t)(sys_get_le64(ts_buf) >> 8));
861 LOG_DBG("sys hi32 %x",
862 dwt_reg_read_u32(dev, DWT_SYS_TIME_ID, 1));
863 k_sem_give(&ctx->dev_lock);
864
865 tmp_fs = sys_get_le64(ts_buf) * DWT_TS_TIME_UNITS_FS;
866 net_pkt_set_timestamp_ns(pkt, tmp_fs / 1000000U);
867 }
868
869 atomic_clear_bit(&ctx->state, DWT_STATE_TX);
870
871 if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
872 k_sem_take(&ctx->dev_lock, K_FOREVER);
873 dwt_enable_rx(dev, 0);
874 k_sem_give(&ctx->dev_lock);
875 }
876
877 return 0;
878
879 error:
880 atomic_clear_bit(&ctx->state, DWT_STATE_TX);
881 k_sem_give(&ctx->dev_lock);
882
883 return -EIO;
884 }
885
dwt_set_frame_filter(const struct device * dev,bool ff_enable,uint8_t ff_type)886 static void dwt_set_frame_filter(const struct device *dev,
887 bool ff_enable, uint8_t ff_type)
888 {
889 uint32_t sys_cfg_ff = ff_enable ? DWT_SYS_CFG_FFE : 0;
890
891 sys_cfg_ff |= ff_type & DWT_SYS_CFG_FF_ALL_EN;
892
893 dwt_reg_write_u8(dev, DWT_SYS_CFG_ID, 0, (uint8_t)sys_cfg_ff);
894 }
895
dwt_configure(const struct device * dev,enum ieee802154_config_type type,const struct ieee802154_config * config)896 static int dwt_configure(const struct device *dev,
897 enum ieee802154_config_type type,
898 const struct ieee802154_config *config)
899 {
900 struct dwt_context *ctx = dev->data;
901
902 LOG_DBG("API configure %p", ctx);
903
904 switch (type) {
905 case IEEE802154_CONFIG_AUTO_ACK_FPB:
906 LOG_DBG("IEEE802154_CONFIG_AUTO_ACK_FPB");
907 break;
908
909 case IEEE802154_CONFIG_ACK_FPB:
910 LOG_DBG("IEEE802154_CONFIG_ACK_FPB");
911 break;
912
913 case IEEE802154_CONFIG_PAN_COORDINATOR:
914 LOG_DBG("IEEE802154_CONFIG_PAN_COORDINATOR");
915 break;
916
917 case IEEE802154_CONFIG_PROMISCUOUS:
918 LOG_DBG("IEEE802154_CONFIG_PROMISCUOUS");
919 break;
920
921 case IEEE802154_CONFIG_EVENT_HANDLER:
922 LOG_DBG("IEEE802154_CONFIG_EVENT_HANDLER");
923 break;
924
925 default:
926 return -EINVAL;
927 }
928
929 return -ENOTSUP;
930 }
931
932 /* driver-allocated attribute memory - constant across all driver instances */
933 static const struct {
934 const struct ieee802154_phy_channel_range phy_channel_range[2];
935 const struct ieee802154_phy_supported_channels phy_supported_channels;
936 } drv_attr = {
937 .phy_channel_range = {
938 { .from_channel = 1, .to_channel = 5 },
939 { .from_channel = 7, .to_channel = 7 },
940 },
941 .phy_supported_channels = {
942 .ranges = drv_attr.phy_channel_range,
943 .num_ranges = 2U,
944 },
945 };
946
dwt_attr_get(const struct device * dev,enum ieee802154_attr attr,struct ieee802154_attr_value * value)947 static int dwt_attr_get(const struct device *dev, enum ieee802154_attr attr,
948 struct ieee802154_attr_value *value)
949 {
950 if (ieee802154_attr_get_channel_page_and_range(
951 attr, IEEE802154_ATTR_PHY_CHANNEL_PAGE_FOUR_HRP_UWB,
952 &drv_attr.phy_supported_channels, value) == 0) {
953 return 0;
954 }
955
956 switch (attr) {
957 case IEEE802154_ATTR_PHY_HRP_UWB_SUPPORTED_PRFS: {
958 struct dwt_context *ctx = dev->data;
959 struct dwt_phy_config *rf_cfg = &ctx->rf_cfg;
960
961 value->phy_hrp_uwb_supported_nominal_prfs =
962 rf_cfg->prf == DWT_PRF_64M ? IEEE802154_PHY_HRP_UWB_NOMINAL_64_M
963 : IEEE802154_PHY_HRP_UWB_NOMINAL_16_M;
964 return 0;
965 }
966
967 default:
968 return -ENOENT;
969 }
970 }
971
972 /*
973 * Note, the DW_RESET pin should not be driven high externally.
974 */
dwt_hw_reset(const struct device * dev)975 static int dwt_hw_reset(const struct device *dev)
976 {
977 const struct dwt_hi_cfg *hi_cfg = dev->config;
978
979 if (gpio_pin_configure_dt(&hi_cfg->rst_gpio, GPIO_OUTPUT_ACTIVE)) {
980 LOG_ERR("Failed to configure GPIO pin %u", hi_cfg->rst_gpio.pin);
981 return -EINVAL;
982 }
983
984 k_sleep(K_MSEC(1));
985 gpio_pin_set_dt(&hi_cfg->rst_gpio, 0);
986 k_sleep(K_MSEC(5));
987
988 if (gpio_pin_configure_dt(&hi_cfg->rst_gpio, GPIO_INPUT)) {
989 LOG_ERR("Failed to configure GPIO pin %u", hi_cfg->rst_gpio.pin);
990 return -EINVAL;
991 }
992
993 return 0;
994 }
995
996 /*
997 * SPI speed in INIT state or for wake-up sequence,
998 * see 2.3.2 Overview of main operational states
999 */
dwt_set_spi_slow(const struct device * dev,const uint32_t freq)1000 static void dwt_set_spi_slow(const struct device *dev, const uint32_t freq)
1001 {
1002 struct dwt_context *ctx = dev->data;
1003
1004 ctx->spi_cfg_slow.frequency = freq;
1005 ctx->spi_cfg = &ctx->spi_cfg_slow;
1006 }
1007
1008 /* SPI speed in IDLE, RX, and TX state */
dwt_set_spi_fast(const struct device * dev)1009 static void dwt_set_spi_fast(const struct device *dev)
1010 {
1011 const struct dwt_hi_cfg *hi_cfg = dev->config;
1012 struct dwt_context *ctx = dev->data;
1013
1014 ctx->spi_cfg = &hi_cfg->bus.config;
1015 }
1016
dwt_set_rx_mode(const struct device * dev)1017 static void dwt_set_rx_mode(const struct device *dev)
1018 {
1019 struct dwt_context *ctx = dev->data;
1020 struct dwt_phy_config *rf_cfg = &ctx->rf_cfg;
1021 uint32_t pmsc_ctrl0;
1022 uint32_t t_on_us;
1023 uint8_t rx_sniff[2];
1024
1025 /* SNIFF Mode ON time in units of PAC */
1026 rx_sniff[0] = CONFIG_IEEE802154_DW1000_SNIFF_ONT &
1027 DWT_RX_SNIFF_SNIFF_ONT_MASK;
1028 /* SNIFF Mode OFF time in microseconds */
1029 rx_sniff[1] = CONFIG_IEEE802154_DW1000_SNIFF_OFFT;
1030
1031 t_on_us = (rx_sniff[0] + 1) * (BIT(3) << rf_cfg->rx_pac_l);
1032 LOG_INF("RX duty cycle %u%%", t_on_us * 100 / (t_on_us + rx_sniff[1]));
1033
1034 dwt_register_write(dev, DWT_RX_SNIFF_ID, DWT_RX_SNIFF_OFFSET,
1035 sizeof(rx_sniff), rx_sniff);
1036
1037 pmsc_ctrl0 = dwt_reg_read_u32(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_OFFSET);
1038 /* Enable PLL2 on/off sequencing for SNIFF mode */
1039 pmsc_ctrl0 |= DWT_PMSC_CTRL0_PLL2_SEQ_EN;
1040 dwt_reg_write_u32(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_OFFSET, pmsc_ctrl0);
1041 }
1042
dwt_start(const struct device * dev)1043 static int dwt_start(const struct device *dev)
1044 {
1045 struct dwt_context *ctx = dev->data;
1046 uint8_t cswakeup_buf[32] = {0};
1047
1048 k_sem_take(&ctx->dev_lock, K_FOREVER);
1049
1050 /* Set SPI clock to lowest frequency */
1051 dwt_set_spi_slow(dev, DWT_SPI_CSWAKEUP_FREQ);
1052
1053 if (dwt_reg_read_u32(dev, DWT_DEV_ID_ID, 0) != DWT_DEVICE_ID) {
1054 /* Keep SPI CS line low for 500 microseconds */
1055 dwt_register_read(dev, 0, 0, sizeof(cswakeup_buf),
1056 cswakeup_buf);
1057 /* Give device time to initialize */
1058 k_sleep(K_MSEC(5));
1059
1060 if (dwt_reg_read_u32(dev, DWT_DEV_ID_ID, 0) != DWT_DEVICE_ID) {
1061 LOG_ERR("Failed to wake-up %p", dev);
1062 k_sem_give(&ctx->dev_lock);
1063 return -1;
1064 }
1065 } else {
1066 LOG_WRN("Device not in a sleep mode");
1067 }
1068
1069 /* Restore SPI clock settings */
1070 dwt_set_spi_slow(dev, DWT_SPI_SLOW_FREQ);
1071 dwt_set_spi_fast(dev);
1072
1073 dwt_setup_int(dev, true);
1074 dwt_disable_txrx(dev);
1075 dwt_reset_rfrx(dev);
1076
1077 if (CONFIG_IEEE802154_DW1000_SNIFF_ONT != 0) {
1078 dwt_set_rx_mode(dev);
1079 }
1080
1081 /* Re-enable RX after packet reception */
1082 atomic_set_bit(&ctx->state, DWT_STATE_RX_DEF_ON);
1083 dwt_enable_rx(dev, 0);
1084 k_sem_give(&ctx->dev_lock);
1085
1086 LOG_INF("Started %p", dev);
1087
1088 return 0;
1089 }
1090
dwt_stop(const struct device * dev)1091 static int dwt_stop(const struct device *dev)
1092 {
1093 struct dwt_context *ctx = dev->data;
1094
1095 k_sem_take(&ctx->dev_lock, K_FOREVER);
1096 dwt_disable_txrx(dev);
1097 dwt_reset_rfrx(dev);
1098 dwt_setup_int(dev, false);
1099
1100 /* Copy the user configuration and enter sleep mode */
1101 dwt_reg_write_u8(dev, DWT_AON_ID, DWT_AON_CTRL_OFFSET,
1102 DWT_AON_CTRL_SAVE);
1103 k_sem_give(&ctx->dev_lock);
1104
1105 LOG_INF("Stopped %p", dev);
1106
1107 return 0;
1108 }
1109
dwt_set_sysclks_xti(const struct device * dev,bool ldeload)1110 static inline void dwt_set_sysclks_xti(const struct device *dev, bool ldeload)
1111 {
1112 uint16_t clks = BIT(9) | DWT_PMSC_CTRL0_SYSCLKS_19M;
1113
1114 /*
1115 * See Table 4: Register accesses required to load LDE microcode,
1116 * set PMSC_CTRL0 0x0301, load LDE, set PMSC_CTRL0 0x0200.
1117 */
1118 if (ldeload) {
1119 clks |= BIT(8);
1120 }
1121
1122 /* Force system clock to be the 19.2 MHz XTI clock */
1123 dwt_reg_write_u16(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_OFFSET, clks);
1124 }
1125
dwt_set_sysclks_auto(const struct device * dev)1126 static inline void dwt_set_sysclks_auto(const struct device *dev)
1127 {
1128 uint8_t sclks = DWT_PMSC_CTRL0_SYSCLKS_AUTO |
1129 DWT_PMSC_CTRL0_RXCLKS_AUTO |
1130 DWT_PMSC_CTRL0_TXCLKS_AUTO;
1131
1132 dwt_reg_write_u8(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_OFFSET, sclks);
1133 }
1134
dwt_otpmem_read(const struct device * dev,uint16_t otp_addr)1135 static uint32_t dwt_otpmem_read(const struct device *dev, uint16_t otp_addr)
1136 {
1137 dwt_reg_write_u16(dev, DWT_OTP_IF_ID, DWT_OTP_ADDR, otp_addr);
1138
1139 dwt_reg_write_u8(dev, DWT_OTP_IF_ID, DWT_OTP_CTRL,
1140 DWT_OTP_CTRL_OTPREAD | DWT_OTP_CTRL_OTPRDEN);
1141 /* OTPREAD is self clearing but OTPRDEN is not */
1142 dwt_reg_write_u8(dev, DWT_OTP_IF_ID, DWT_OTP_CTRL, 0x00);
1143
1144 /* Read read data, available 40ns after rising edge of OTP_READ */
1145 return dwt_reg_read_u32(dev, DWT_OTP_IF_ID, DWT_OTP_RDAT);
1146 }
1147
dwt_initialise_dev(const struct device * dev)1148 static int dwt_initialise_dev(const struct device *dev)
1149 {
1150 struct dwt_context *ctx = dev->data;
1151 uint32_t otp_val = 0;
1152 uint8_t xtal_trim;
1153
1154 dwt_set_sysclks_xti(dev, false);
1155 ctx->sleep_mode = 0;
1156
1157 /* Disable PMSC control of analog RF subsystem */
1158 dwt_reg_write_u16(dev, DWT_PMSC_ID, DWT_PMSC_CTRL1_OFFSET,
1159 DWT_PMSC_CTRL1_PKTSEQ_DISABLE);
1160
1161 /* Clear all status flags */
1162 dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0, DWT_SYS_STATUS_MASK_32);
1163
1164 /*
1165 * Apply soft reset,
1166 * see SOFTRESET field description in DW1000 User Manual.
1167 */
1168 dwt_reg_write_u8(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_SOFTRESET_OFFSET,
1169 DWT_PMSC_CTRL0_RESET_ALL);
1170 k_sleep(K_MSEC(1));
1171 dwt_reg_write_u8(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_SOFTRESET_OFFSET,
1172 DWT_PMSC_CTRL0_RESET_CLEAR);
1173
1174 dwt_set_sysclks_xti(dev, false);
1175
1176 /*
1177 * This bit (a.k.a PLLLDT) should be set to ensure reliable
1178 * operation of the CPLOCK bit.
1179 */
1180 dwt_reg_write_u8(dev, DWT_EXT_SYNC_ID, DWT_EC_CTRL_OFFSET,
1181 DWT_EC_CTRL_PLLLCK);
1182
1183 /* Kick LDO if there is a value programmed. */
1184 otp_val = dwt_otpmem_read(dev, DWT_OTP_LDOTUNE_ADDR);
1185 if ((otp_val & 0xFF) != 0) {
1186 dwt_reg_write_u8(dev, DWT_OTP_IF_ID, DWT_OTP_SF,
1187 DWT_OTP_SF_LDO_KICK);
1188 ctx->sleep_mode |= DWT_AON_WCFG_ONW_LLDO;
1189 LOG_INF("Load LDOTUNE_CAL parameter");
1190 }
1191
1192 otp_val = dwt_otpmem_read(dev, DWT_OTP_XTRIM_ADDR);
1193 xtal_trim = otp_val & DWT_FS_XTALT_MASK;
1194 LOG_INF("OTP Revision 0x%02x, XTAL Trim 0x%02x",
1195 (uint8_t)(otp_val >> 8), xtal_trim);
1196
1197 LOG_DBG("CHIP ID 0x%08x", dwt_otpmem_read(dev, DWT_OTP_PARTID_ADDR));
1198 LOG_DBG("LOT ID 0x%08x", dwt_otpmem_read(dev, DWT_OTP_LOTID_ADDR));
1199 LOG_DBG("Vbat 0x%02x", dwt_otpmem_read(dev, DWT_OTP_VBAT_ADDR));
1200 LOG_DBG("Vtemp 0x%02x", dwt_otpmem_read(dev, DWT_OTP_VTEMP_ADDR));
1201
1202 if (xtal_trim == 0) {
1203 /* Set to default */
1204 xtal_trim = DWT_FS_XTALT_MIDRANGE;
1205 }
1206
1207 /* For FS_XTALT bits 7:5 must always be set to binary “011” */
1208 xtal_trim |= BIT(6) | BIT(5);
1209 dwt_reg_write_u8(dev, DWT_FS_CTRL_ID, DWT_FS_XTALT_OFFSET, xtal_trim);
1210
1211 /* Load LDE microcode into RAM, see 2.5.5.10 LDELOAD */
1212 dwt_set_sysclks_xti(dev, true);
1213 dwt_reg_write_u16(dev, DWT_OTP_IF_ID, DWT_OTP_CTRL,
1214 DWT_OTP_CTRL_LDELOAD);
1215 k_sleep(K_MSEC(1));
1216 dwt_set_sysclks_xti(dev, false);
1217 ctx->sleep_mode |= DWT_AON_WCFG_ONW_LLDE;
1218
1219 dwt_set_sysclks_auto(dev);
1220
1221 if (!(dwt_reg_read_u8(dev, DWT_SYS_STATUS_ID, 0) &
1222 DWT_SYS_STATUS_CPLOCK)) {
1223 LOG_WRN("PLL has not locked");
1224 return -EIO;
1225 }
1226
1227 dwt_set_spi_fast(dev);
1228
1229 /* Setup antenna delay values */
1230 dwt_reg_write_u16(dev, DWT_LDE_IF_ID, DWT_LDE_RXANTD_OFFSET,
1231 DW1000_RX_ANT_DLY);
1232 dwt_reg_write_u16(dev, DWT_TX_ANTD_ID, DWT_TX_ANTD_OFFSET,
1233 DW1000_TX_ANT_DLY);
1234
1235 /* Clear AON_CFG1 register */
1236 dwt_reg_write_u8(dev, DWT_AON_ID, DWT_AON_CFG1_OFFSET, 0);
1237 /*
1238 * Configure sleep mode:
1239 * - On wake-up load configurations from the AON memory
1240 * - preserve sleep mode configuration
1241 * - On Wake-up load the LDE microcode
1242 * - When available, on wake-up load the LDO tune value
1243 */
1244 ctx->sleep_mode |= DWT_AON_WCFG_ONW_LDC |
1245 DWT_AON_WCFG_PRES_SLEEP;
1246 dwt_reg_write_u16(dev, DWT_AON_ID, DWT_AON_WCFG_OFFSET,
1247 ctx->sleep_mode);
1248 LOG_DBG("sleep mode 0x%04x", ctx->sleep_mode);
1249 /* Enable sleep and wake using SPI CSn */
1250 dwt_reg_write_u8(dev, DWT_AON_ID, DWT_AON_CFG0_OFFSET,
1251 DWT_AON_CFG0_WAKE_SPI | DWT_AON_CFG0_SLEEP_EN);
1252
1253 return 0;
1254 }
1255
1256 /*
1257 * RF PHY configuration. Must be carried out as part of initialization and
1258 * for every channel change. See also 2.5 Default Configuration on Power Up.
1259 */
dwt_configure_rf_phy(const struct device * dev)1260 static int dwt_configure_rf_phy(const struct device *dev)
1261 {
1262 struct dwt_context *ctx = dev->data;
1263 struct dwt_phy_config *rf_cfg = &ctx->rf_cfg;
1264 uint8_t chan = rf_cfg->channel;
1265 uint8_t prf_idx = rf_cfg->prf;
1266 uint32_t chan_ctrl = 0;
1267 uint8_t rxctrlh;
1268 uint8_t pll_tune;
1269 uint8_t tune4h;
1270 uint8_t pgdelay;
1271 uint16_t lde_repc;
1272 uint16_t agc_tune1;
1273 uint16_t sfdto;
1274 uint16_t tune1a;
1275 uint16_t tune0b;
1276 uint16_t tune1b;
1277 uint32_t txctrl;
1278 uint32_t pll_cfg;
1279 uint32_t tune2;
1280 uint32_t sys_cfg;
1281 uint32_t tx_fctrl;
1282 uint32_t power;
1283
1284 if ((chan < 1) || (chan > 7) || (chan == 6)) {
1285 LOG_ERR("Channel not supported %u", chan);
1286 return -ENOTSUP;
1287 }
1288
1289 if (rf_cfg->rx_shr_code >= ARRAY_SIZE(dwt_lde_repc_defs)) {
1290 LOG_ERR("Preamble code not supported %u",
1291 rf_cfg->rx_shr_code);
1292 return -ENOTSUP;
1293 }
1294
1295 if (prf_idx >= DWT_NUMOF_PRFS) {
1296 LOG_ERR("PRF not supported %u", prf_idx);
1297 return -ENOTSUP;
1298 }
1299
1300 if (rf_cfg->rx_pac_l >= DWT_NUMOF_PACS) {
1301 LOG_ERR("RX PAC not supported %u", rf_cfg->rx_pac_l);
1302 return -ENOTSUP;
1303 }
1304
1305 if (rf_cfg->rx_ns_sfd > 1) {
1306 LOG_ERR("Wrong NS SFD configuration");
1307 return -ENOTSUP;
1308 }
1309
1310 if (rf_cfg->tx_shr_nsync >= DWT_NUM_OF_PLEN) {
1311 LOG_ERR("Wrong SHR configuration");
1312 return -ENOTSUP;
1313 }
1314
1315 lde_repc = dwt_lde_repc_defs[rf_cfg->rx_shr_code];
1316 agc_tune1 = dwt_agc_tune1_defs[prf_idx];
1317 sfdto = rf_cfg->rx_sfd_to;
1318 rxctrlh = dwt_rxctrlh_defs[dwt_ch_to_cfg[chan]];
1319 txctrl = dwt_txctrl_defs[dwt_ch_to_cfg[chan]];
1320 pll_tune = dwt_plltune_defs[dwt_ch_to_cfg[chan]];
1321 pll_cfg = dwt_pllcfg_defs[dwt_ch_to_cfg[chan]];
1322 tune2 = dwt_tune2_defs[prf_idx][rf_cfg->rx_pac_l];
1323 tune1a = dwt_tune1a_defs[prf_idx];
1324 tune0b = dwt_tune0b_defs[rf_cfg->dr][rf_cfg->rx_ns_sfd];
1325 pgdelay = dwt_pgdelay_defs[dwt_ch_to_cfg[chan]];
1326
1327 sys_cfg = dwt_reg_read_u32(dev, DWT_SYS_CFG_ID, 0);
1328 tx_fctrl = dwt_reg_read_u32(dev, DWT_TX_FCTRL_ID, 0);
1329
1330 /* Don't allow 0 - SFD timeout will always be enabled */
1331 if (sfdto == 0) {
1332 sfdto = DWT_SFDTOC_DEF;
1333 }
1334
1335 /* Set IEEE 802.15.4 compliant mode */
1336 sys_cfg &= ~DWT_SYS_CFG_PHR_MODE_11;
1337
1338 if (rf_cfg->dr == DWT_BR_110K) {
1339 /* Set Receiver Mode 110 kbps data rate */
1340 sys_cfg |= DWT_SYS_CFG_RXM110K;
1341 lde_repc = lde_repc >> 3;
1342 tune1b = DWT_DRX_TUNE1b_110K;
1343 tune4h = DWT_DRX_TUNE4H_PRE64;
1344 } else {
1345 sys_cfg &= ~DWT_SYS_CFG_RXM110K;
1346 if (rf_cfg->tx_shr_nsync == DWT_PLEN_64) {
1347 tune1b = DWT_DRX_TUNE1b_6M8_PRE64;
1348 tune4h = DWT_DRX_TUNE4H_PRE64;
1349 } else {
1350 tune1b = DWT_DRX_TUNE1b_850K_6M8;
1351 tune4h = DWT_DRX_TUNE4H_PRE128PLUS;
1352 }
1353 }
1354
1355 if (sys_cfg & DWT_SYS_CFG_DIS_STXP) {
1356 if (rf_cfg->prf == DWT_PRF_64M) {
1357 power = dwt_txpwr_stxp1_64[dwt_ch_to_cfg[chan]];
1358 } else {
1359 power = dwt_txpwr_stxp1_16[dwt_ch_to_cfg[chan]];
1360 }
1361 } else {
1362 if (rf_cfg->prf == DWT_PRF_64M) {
1363 power = dwt_txpwr_stxp0_64[dwt_ch_to_cfg[chan]];
1364 } else {
1365 power = dwt_txpwr_stxp0_16[dwt_ch_to_cfg[chan]];
1366 }
1367 }
1368
1369 dwt_reg_write_u32(dev, DWT_SYS_CFG_ID, 0, sys_cfg);
1370 LOG_DBG("SYS_CFG: 0x%08x", sys_cfg);
1371
1372 dwt_reg_write_u16(dev, DWT_LDE_IF_ID, DWT_LDE_REPC_OFFSET, lde_repc);
1373 LOG_DBG("LDE_REPC: 0x%04x", lde_repc);
1374
1375 dwt_reg_write_u8(dev, DWT_LDE_IF_ID, DWT_LDE_CFG1_OFFSET,
1376 DWT_DEFAULT_LDE_CFG1);
1377
1378 if (rf_cfg->prf == DWT_PRF_64M) {
1379 dwt_reg_write_u16(dev, DWT_LDE_IF_ID, DWT_LDE_CFG2_OFFSET,
1380 DWT_DEFAULT_LDE_CFG2_PRF64);
1381 LOG_DBG("LDE_CFG2: 0x%04x", DWT_DEFAULT_LDE_CFG2_PRF64);
1382 } else {
1383 dwt_reg_write_u16(dev, DWT_LDE_IF_ID, DWT_LDE_CFG2_OFFSET,
1384 DWT_DEFAULT_LDE_CFG2_PRF16);
1385 LOG_DBG("LDE_CFG2: 0x%04x", DWT_DEFAULT_LDE_CFG2_PRF16);
1386 }
1387
1388 /* Configure PLL2/RF PLL block CFG/TUNE (for a given channel) */
1389 dwt_reg_write_u32(dev, DWT_FS_CTRL_ID, DWT_FS_PLLCFG_OFFSET, pll_cfg);
1390 LOG_DBG("PLLCFG: 0x%08x", pll_cfg);
1391 dwt_reg_write_u8(dev, DWT_FS_CTRL_ID, DWT_FS_PLLTUNE_OFFSET, pll_tune);
1392 LOG_DBG("PLLTUNE: 0x%02x", pll_tune);
1393 /* Configure RF RX blocks (for specified channel/bandwidth) */
1394 dwt_reg_write_u8(dev, DWT_RF_CONF_ID, DWT_RF_RXCTRLH_OFFSET, rxctrlh);
1395 LOG_DBG("RXCTRLH: 0x%02x", rxctrlh);
1396 /* Configure RF/TX blocks for specified channel and PRF */
1397 dwt_reg_write_u32(dev, DWT_RF_CONF_ID, DWT_RF_TXCTRL_OFFSET, txctrl);
1398 LOG_DBG("TXCTRL: 0x%08x", txctrl);
1399
1400 /* Digital receiver configuration, DRX_CONF */
1401 dwt_reg_write_u16(dev, DWT_DRX_CONF_ID, DWT_DRX_TUNE0b_OFFSET, tune0b);
1402 LOG_DBG("DRX_TUNE0b: 0x%04x", tune0b);
1403 dwt_reg_write_u16(dev, DWT_DRX_CONF_ID, DWT_DRX_TUNE1a_OFFSET, tune1a);
1404 LOG_DBG("DRX_TUNE1a: 0x%04x", tune1a);
1405 dwt_reg_write_u16(dev, DWT_DRX_CONF_ID, DWT_DRX_TUNE1b_OFFSET, tune1b);
1406 LOG_DBG("DRX_TUNE1b: 0x%04x", tune1b);
1407 dwt_reg_write_u32(dev, DWT_DRX_CONF_ID, DWT_DRX_TUNE2_OFFSET, tune2);
1408 LOG_DBG("DRX_TUNE2: 0x%08x", tune2);
1409 dwt_reg_write_u8(dev, DWT_DRX_CONF_ID, DWT_DRX_TUNE4H_OFFSET, tune4h);
1410 LOG_DBG("DRX_TUNE4H: 0x%02x", tune4h);
1411 dwt_reg_write_u16(dev, DWT_DRX_CONF_ID, DWT_DRX_SFDTOC_OFFSET, sfdto);
1412 LOG_DBG("DRX_SFDTOC: 0x%04x", sfdto);
1413
1414 /* Automatic Gain Control configuration and control, AGC_CTRL */
1415 dwt_reg_write_u16(dev, DWT_AGC_CTRL_ID, DWT_AGC_TUNE1_OFFSET,
1416 agc_tune1);
1417 LOG_DBG("AGC_TUNE1: 0x%04x", agc_tune1);
1418 dwt_reg_write_u32(dev, DWT_AGC_CTRL_ID, DWT_AGC_TUNE2_OFFSET,
1419 DWT_AGC_TUNE2_VAL);
1420
1421 if (rf_cfg->rx_ns_sfd) {
1422 /*
1423 * SFD_LENGTH, length of the SFD sequence used when
1424 * the data rate is 850 kbps or 6.8 Mbps,
1425 * must be set to either 8 or 16.
1426 */
1427 dwt_reg_write_u8(dev, DWT_USR_SFD_ID, 0x00,
1428 dwt_ns_sfdlen[rf_cfg->dr]);
1429 LOG_DBG("USR_SFDLEN: 0x%02x", dwt_ns_sfdlen[rf_cfg->dr]);
1430 chan_ctrl |= DWT_CHAN_CTRL_DWSFD;
1431 }
1432
1433 /* Set RX_CHAN and TX CHAN */
1434 chan_ctrl |= (chan & DWT_CHAN_CTRL_TX_CHAN_MASK) |
1435 ((chan << DWT_CHAN_CTRL_RX_CHAN_SHIFT) &
1436 DWT_CHAN_CTRL_RX_CHAN_MASK);
1437
1438 /* Set RXPRF */
1439 chan_ctrl |= (BIT(rf_cfg->prf) << DWT_CHAN_CTRL_RXFPRF_SHIFT) &
1440 DWT_CHAN_CTRL_RXFPRF_MASK;
1441
1442 /* Set TX_PCOD */
1443 chan_ctrl |= (rf_cfg->tx_shr_code << DWT_CHAN_CTRL_TX_PCOD_SHIFT) &
1444 DWT_CHAN_CTRL_TX_PCOD_MASK;
1445
1446 /* Set RX_PCOD */
1447 chan_ctrl |= (rf_cfg->rx_shr_code << DWT_CHAN_CTRL_RX_PCOD_SHIFT) &
1448 DWT_CHAN_CTRL_RX_PCOD_MASK;
1449
1450 /* Set Channel Control */
1451 dwt_reg_write_u32(dev, DWT_CHAN_CTRL_ID, 0, chan_ctrl);
1452 LOG_DBG("CHAN_CTRL 0x%08x", chan_ctrl);
1453
1454 /* Set up TX Preamble Size, PRF and Data Rate */
1455 tx_fctrl = dwt_plen_cfg[rf_cfg->tx_shr_nsync] |
1456 (BIT(rf_cfg->prf) << DWT_TX_FCTRL_TXPRF_SHFT) |
1457 (rf_cfg->dr << DWT_TX_FCTRL_TXBR_SHFT);
1458
1459 dwt_reg_write_u32(dev, DWT_TX_FCTRL_ID, 0, tx_fctrl);
1460 LOG_DBG("TX_FCTRL 0x%08x", tx_fctrl);
1461
1462 /* Set the Pulse Generator Delay */
1463 dwt_reg_write_u8(dev, DWT_TX_CAL_ID, DWT_TC_PGDELAY_OFFSET, pgdelay);
1464 LOG_DBG("PGDELAY 0x%02x", pgdelay);
1465 /* Set Transmit Power Control */
1466 dwt_reg_write_u32(dev, DWT_TX_POWER_ID, 0, power);
1467 LOG_DBG("TX_POWER 0x%08x", power);
1468
1469 /*
1470 * From 5.3.1.2 SFD Initialisation,
1471 * SFD sequence initialisation for Auto ACK frame.
1472 */
1473 dwt_reg_write_u8(dev, DWT_SYS_CTRL_ID, DWT_SYS_CTRL_OFFSET,
1474 DWT_SYS_CTRL_TXSTRT | DWT_SYS_CTRL_TRXOFF);
1475
1476 /*
1477 * Calculate PHY timing parameters
1478 *
1479 * From (9.4) Std 802.15.4-2011
1480 * Tshr = Tpsym * (NSYNC + NSFD )
1481 * Tphr = NPHR * Tdsym1m
1482 * Tpsdu = Tdsym * NPSDU * NSYMPEROCTET / Rfec
1483 *
1484 * PRF: pulse repetition frequency
1485 * PSR: preamble symbol repetitions
1486 * SFD: start of frame delimiter
1487 * SHR: synchronisation header (SYNC + SFD)
1488 * PHR: PHY header
1489 */
1490 uint16_t nsync = BIT(rf_cfg->tx_shr_nsync + 6);
1491
1492 if (rf_cfg->prf == DWT_PRF_64M) {
1493 rf_cfg->t_shr = UWB_PHY_TPSYM_PRF64 *
1494 (nsync + UWB_PHY_NUMOF_SYM_SHR_SFD);
1495 } else {
1496 rf_cfg->t_shr = UWB_PHY_TPSYM_PRF16 *
1497 (nsync + UWB_PHY_NUMOF_SYM_SHR_SFD);
1498 }
1499
1500 if (rf_cfg->dr == DWT_BR_6M8) {
1501 rf_cfg->t_phr = UWB_PHY_NUMOF_SYM_PHR * UWB_PHY_TDSYM_PHR_6M8;
1502 rf_cfg->t_dsym = UWB_PHY_TDSYM_DATA_6M8 / 0.44;
1503 } else if (rf_cfg->dr == DWT_BR_850K) {
1504 rf_cfg->t_phr = UWB_PHY_NUMOF_SYM_PHR * UWB_PHY_TDSYM_PHR_850K;
1505 rf_cfg->t_dsym = UWB_PHY_TDSYM_DATA_850K / 0.44;
1506 } else {
1507 rf_cfg->t_phr = UWB_PHY_NUMOF_SYM_PHR * UWB_PHY_TDSYM_PHR_110K;
1508 rf_cfg->t_dsym = UWB_PHY_TDSYM_DATA_110K / 0.44;
1509 }
1510
1511 return 0;
1512 }
1513
dw1000_init(const struct device * dev)1514 static int dw1000_init(const struct device *dev)
1515 {
1516 struct dwt_context *ctx = dev->data;
1517 const struct dwt_hi_cfg *hi_cfg = dev->config;
1518
1519 LOG_INF("Initialize DW1000 Transceiver");
1520 k_sem_init(&ctx->phy_sem, 0, 1);
1521
1522 /* slow SPI config */
1523 memcpy(&ctx->spi_cfg_slow, &hi_cfg->bus.config, sizeof(ctx->spi_cfg_slow));
1524 ctx->spi_cfg_slow.frequency = DWT_SPI_SLOW_FREQ;
1525
1526 if (!spi_is_ready_dt(&hi_cfg->bus)) {
1527 LOG_ERR("SPI device not ready");
1528 return -ENODEV;
1529 }
1530
1531 dwt_set_spi_slow(dev, DWT_SPI_SLOW_FREQ);
1532
1533 /* Initialize IRQ GPIO */
1534 if (!gpio_is_ready_dt(&hi_cfg->irq_gpio)) {
1535 LOG_ERR("IRQ GPIO device not ready");
1536 return -ENODEV;
1537 }
1538
1539 if (gpio_pin_configure_dt(&hi_cfg->irq_gpio, GPIO_INPUT)) {
1540 LOG_ERR("Unable to configure GPIO pin %u", hi_cfg->irq_gpio.pin);
1541 return -EINVAL;
1542 }
1543
1544 gpio_init_callback(&(ctx->gpio_cb), dwt_gpio_callback,
1545 BIT(hi_cfg->irq_gpio.pin));
1546
1547 if (gpio_add_callback(hi_cfg->irq_gpio.port, &(ctx->gpio_cb))) {
1548 LOG_ERR("Failed to add IRQ callback");
1549 return -EINVAL;
1550 }
1551
1552 /* Initialize RESET GPIO */
1553 if (!gpio_is_ready_dt(&hi_cfg->rst_gpio)) {
1554 LOG_ERR("Reset GPIO device not ready");
1555 return -ENODEV;
1556 }
1557
1558 if (gpio_pin_configure_dt(&hi_cfg->rst_gpio, GPIO_INPUT)) {
1559 LOG_ERR("Unable to configure GPIO pin %u", hi_cfg->rst_gpio.pin);
1560 return -EINVAL;
1561 }
1562
1563 LOG_INF("GPIO and SPI configured");
1564
1565 dwt_hw_reset(dev);
1566
1567 if (dwt_reg_read_u32(dev, DWT_DEV_ID_ID, 0) != DWT_DEVICE_ID) {
1568 LOG_ERR("Failed to read device ID %p", dev);
1569 return -ENODEV;
1570 }
1571
1572 if (dwt_initialise_dev(dev)) {
1573 LOG_ERR("Failed to initialize DW1000");
1574 return -EIO;
1575 }
1576
1577 if (dwt_configure_rf_phy(dev)) {
1578 LOG_ERR("Failed to configure RF PHY");
1579 return -EIO;
1580 }
1581
1582 /* Allow Beacon, Data, Acknowledgement, MAC command */
1583 dwt_set_frame_filter(dev, true, DWT_SYS_CFG_FFAB | DWT_SYS_CFG_FFAD |
1584 DWT_SYS_CFG_FFAA | DWT_SYS_CFG_FFAM);
1585
1586 /*
1587 * Enable system events:
1588 * - transmit frame sent,
1589 * - receiver FCS good,
1590 * - receiver PHY header error,
1591 * - receiver FCS error,
1592 * - receiver Reed Solomon Frame Sync Loss,
1593 * - receive Frame Wait Timeout,
1594 * - preamble detection timeout,
1595 * - receive SFD timeout
1596 */
1597 dwt_reg_write_u32(dev, DWT_SYS_MASK_ID, 0,
1598 DWT_SYS_MASK_MTXFRS |
1599 DWT_SYS_MASK_MRXFCG |
1600 DWT_SYS_MASK_MRXPHE |
1601 DWT_SYS_MASK_MRXFCE |
1602 DWT_SYS_MASK_MRXRFSL |
1603 DWT_SYS_MASK_MRXRFTO |
1604 DWT_SYS_MASK_MRXPTO |
1605 DWT_SYS_MASK_MRXSFDTO);
1606
1607 /* Initialize IRQ event work queue */
1608 ctx->dev = dev;
1609
1610 k_work_queue_start(&dwt_work_queue, dwt_work_queue_stack,
1611 K_KERNEL_STACK_SIZEOF(dwt_work_queue_stack),
1612 CONFIG_SYSTEM_WORKQUEUE_PRIORITY, NULL);
1613
1614 k_work_init(&ctx->irq_cb_work, dwt_irq_work_handler);
1615
1616 dwt_setup_int(dev, true);
1617
1618 LOG_INF("DW1000 device initialized and configured");
1619
1620 return 0;
1621 }
1622
get_mac(const struct device * dev)1623 static inline uint8_t *get_mac(const struct device *dev)
1624 {
1625 struct dwt_context *dw1000 = dev->data;
1626
1627 sys_rand_get(dw1000->mac_addr, sizeof(dw1000->mac_addr));
1628
1629 dw1000->mac_addr[0] = (dw1000->mac_addr[0] & ~0x01) | 0x02;
1630
1631 return dw1000->mac_addr;
1632 }
1633
dwt_iface_api_init(struct net_if * iface)1634 static void dwt_iface_api_init(struct net_if *iface)
1635 {
1636 const struct device *dev = net_if_get_device(iface);
1637 struct dwt_context *dw1000 = dev->data;
1638 uint8_t *mac = get_mac(dev);
1639
1640 net_if_set_link_addr(iface, mac, 8, NET_LINK_IEEE802154);
1641
1642 dw1000->iface = iface;
1643
1644 ieee802154_init(iface);
1645
1646 LOG_INF("Iface initialized");
1647 }
1648
1649 static const struct ieee802154_radio_api dwt_radio_api = {
1650 .iface_api.init = dwt_iface_api_init,
1651
1652 .get_capabilities = dwt_get_capabilities,
1653 .cca = dwt_cca,
1654 .set_channel = dwt_set_channel,
1655 .filter = dwt_filter,
1656 .set_txpower = dwt_set_power,
1657 .start = dwt_start,
1658 .stop = dwt_stop,
1659 .configure = dwt_configure,
1660 .ed_scan = dwt_ed,
1661 .tx = dwt_tx,
1662 .attr_get = dwt_attr_get,
1663 };
1664
1665 #define DWT_PSDU_LENGTH (127 - DWT_FCS_LENGTH)
1666
1667 #if defined(CONFIG_IEEE802154_RAW_MODE)
1668 DEVICE_DT_INST_DEFINE(0, dw1000_init, NULL,
1669 &dwt_0_context, &dw1000_0_config,
1670 POST_KERNEL, CONFIG_IEEE802154_DW1000_INIT_PRIO,
1671 &dwt_radio_api);
1672 #else
1673 NET_DEVICE_DT_INST_DEFINE(0,
1674 dw1000_init,
1675 NULL,
1676 &dwt_0_context,
1677 &dw1000_0_config,
1678 CONFIG_IEEE802154_DW1000_INIT_PRIO,
1679 &dwt_radio_api,
1680 IEEE802154_L2,
1681 NET_L2_GET_CTX_TYPE(IEEE802154_L2),
1682 DWT_PSDU_LENGTH);
1683 #endif
1684
