1/* 2 * Copyright (c) 2019 Linaro Limited 3 * Copyright (c) 2019 Centaur Analytics, Inc 4 * Copyright (c) 2020 Teslabs Engineering S.L. 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9#include <arm/armv7-m.dtsi> 10#include <zephyr/dt-bindings/clock/stm32h7_clock.h> 11#include <zephyr/dt-bindings/gpio/gpio.h> 12#include <zephyr/dt-bindings/i2c/i2c.h> 13#include <zephyr/dt-bindings/pwm/pwm.h> 14#include <zephyr/dt-bindings/pwm/stm32_pwm.h> 15#include <zephyr/dt-bindings/dma/stm32_dma.h> 16#include <zephyr/dt-bindings/adc/stm32h7_adc.h> 17#include <zephyr/dt-bindings/reset/stm32h7_reset.h> 18#include <zephyr/dt-bindings/adc/adc.h> 19#include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h> 20#include <zephyr/dt-bindings/memory-attr/memory-attr.h> 21#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> 22#include <freq.h> 23 24/ { 25 chosen { 26 zephyr,entropy = &rng; 27 zephyr,flash-controller = &flash; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-m7"; 37 reg = <0>; 38 #address-cells = <1>; 39 #size-cells = <1>; 40 41 mpu: mpu@e000ed90 { 42 compatible = "arm,armv7m-mpu"; 43 reg = <0xe000ed90 0x40>; 44 arm,num-mpu-regions = <16>; 45 }; 46 }; 47 }; 48 49 quadspi_memory: memory@90000000 { 50 compatible = "zephyr,memory-region", "mmio-sram"; 51 reg = <0x90000000 DT_SIZE_M(256)>; 52 zephyr,memory-region = "QSPI"; 53 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; 54 }; 55 56 clocks { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 clk_hse: clk-hse { 61 #clock-cells = <0>; 62 compatible = "st,stm32-hse-clock"; 63 status = "disabled"; 64 }; 65 66 clk_hsi: clk-hsi { 67 #clock-cells = <0>; 68 compatible = "st,stm32h7-hsi-clock"; 69 clock-frequency = <DT_FREQ_M(64)>; 70 status = "disabled"; 71 }; 72 73 clk_hsi48: clk-hsi48 { 74 #clock-cells = <0>; 75 compatible = "fixed-clock"; 76 clock-frequency = <DT_FREQ_M(48)>; 77 status = "disabled"; 78 }; 79 80 clk_csi: clk-csi { 81 #clock-cells = <0>; 82 compatible = "fixed-clock"; 83 clock-frequency = <DT_FREQ_M(4)>; 84 status = "disabled"; 85 }; 86 87 clk_lse: clk-lse { 88 #clock-cells = <0>; 89 compatible = "st,stm32-lse-clock"; 90 clock-frequency = <32768>; 91 driving-capability = <0>; 92 status = "disabled"; 93 }; 94 95 clk_lsi: clk-lsi { 96 #clock-cells = <0>; 97 compatible = "fixed-clock"; 98 clock-frequency = <DT_FREQ_K(32)>; 99 status = "disabled"; 100 }; 101 102 pll: pll@0 { 103 #clock-cells = <0>; 104 compatible = "st,stm32h7-pll-clock"; 105 reg = <0>; 106 status = "disabled"; 107 }; 108 109 pll2: pll@1 { 110 #clock-cells = <0>; 111 compatible = "st,stm32h7-pll-clock"; 112 reg = <1>; 113 status = "disabled"; 114 }; 115 116 pll3: pll@2 { 117 #clock-cells = <0>; 118 compatible = "st,stm32h7-pll-clock"; 119 reg = <2>; 120 status = "disabled"; 121 }; 122 123 perck: perck { 124 #clock-cells = <0>; 125 compatible = "st,stm32-clock-mux"; 126 status = "disabled"; 127 }; 128 }; 129 130 soc { 131 flash: flash-controller@52002000 { 132 compatible = "st,stm32-flash-controller", "st,stm32h7-flash-controller"; 133 reg = <0x52002000 0x400>; 134 interrupts = <4 0>; 135 clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>; 136 137 #address-cells = <1>; 138 #size-cells = <1>; 139 }; 140 141 rcc: rcc@58024400 { 142 compatible = "st,stm32h7-rcc"; 143 #clock-cells = <2>; 144 reg = <0x58024400 0x400>; 145 146 rctl: reset-controller { 147 compatible = "st,stm32-rcc-rctl"; 148 #reset-cells = <1>; 149 }; 150 }; 151 152 exti: interrupt-controller@58000000 { 153 compatible = "st,stm32-exti"; 154 interrupt-controller; 155 #interrupt-cells = <1>; 156 #address-cells = <1>; 157 reg = <0x58000000 0x400>; 158 num-lines = <16>; 159 interrupts = <6 0>, <7 0>, <8 0>, <9 0>, 160 <10 0>, <23 0>, <40 0>; 161 interrupt-names = "line0", "line1", "line2", "line3", 162 "line4", "line5-9", "line10-15"; 163 line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, 164 <4 1>, <5 5>, <10 6>; 165 }; 166 167 pinctrl: pin-controller@58020000 { 168 compatible = "st,stm32-pinctrl"; 169 #address-cells = <1>; 170 #size-cells = <1>; 171 reg = <0x58020000 0x2400>; 172 173 gpioa: gpio@58020000 { 174 compatible = "st,stm32-gpio"; 175 gpio-controller; 176 #gpio-cells = <2>; 177 reg = <0x58020000 0x400>; 178 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>; 179 }; 180 181 gpiob: gpio@58020400 { 182 compatible = "st,stm32-gpio"; 183 gpio-controller; 184 #gpio-cells = <2>; 185 reg = <0x58020400 0x400>; 186 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>; 187 }; 188 189 gpioc: gpio@58020800 { 190 compatible = "st,stm32-gpio"; 191 gpio-controller; 192 #gpio-cells = <2>; 193 reg = <0x58020800 0x400>; 194 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>; 195 }; 196 197 gpiod: gpio@58020C00 { 198 compatible = "st,stm32-gpio"; 199 gpio-controller; 200 #gpio-cells = <2>; 201 reg = <0x58020C00 0x400>; 202 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>; 203 }; 204 205 gpioe: gpio@58021000 { 206 compatible = "st,stm32-gpio"; 207 gpio-controller; 208 #gpio-cells = <2>; 209 reg = <0x58021000 0x400>; 210 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>; 211 }; 212 213 gpiof: gpio@58021400 { 214 compatible = "st,stm32-gpio"; 215 gpio-controller; 216 #gpio-cells = <2>; 217 reg = <0x58021400 0x400>; 218 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>; 219 }; 220 221 gpiog: gpio@58021800 { 222 compatible = "st,stm32-gpio"; 223 gpio-controller; 224 #gpio-cells = <2>; 225 reg = <0x58021800 0x400>; 226 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>; 227 }; 228 229 gpioh: gpio@58021C00 { 230 compatible = "st,stm32-gpio"; 231 gpio-controller; 232 #gpio-cells = <2>; 233 reg = <0x58021C00 0x400>; 234 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>; 235 }; 236 237 gpioi: gpio@58022000 { 238 compatible = "st,stm32-gpio"; 239 gpio-controller; 240 #gpio-cells = <2>; 241 reg = <0x58022000 0x400>; 242 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000100>; 243 }; 244 245 gpioj: gpio@58022400 { 246 compatible = "st,stm32-gpio"; 247 gpio-controller; 248 #gpio-cells = <2>; 249 reg = <0x58022400 0x400>; 250 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000200>; 251 }; 252 253 gpiok: gpio@58022800 { 254 compatible = "st,stm32-gpio"; 255 gpio-controller; 256 #gpio-cells = <2>; 257 reg = <0x58022800 0x400>; 258 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000400>; 259 }; 260 }; 261 262 iwdg: iwdg1: watchdog@58004800 { 263 compatible = "st,stm32-watchdog"; 264 reg = <0x58004800 0x400>; 265 status = "disabled"; 266 }; 267 268 wwdg: wwdg1: watchdog@50003000 { 269 compatible = "st,stm32-window-watchdog"; 270 reg = <0x50003000 0x1000>; 271 clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000040>; 272 interrupts = <0 7>; 273 status = "disabled"; 274 }; 275 276 usart1: serial@40011000 { 277 compatible = "st,stm32-usart", "st,stm32-uart"; 278 reg = <0x40011000 0x400>; 279 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>; 280 resets = <&rctl STM32_RESET(APB2, 4U)>; 281 interrupts = <37 0>; 282 status = "disabled"; 283 }; 284 usart2: serial@40004400 { 285 compatible = "st,stm32-usart", "st,stm32-uart"; 286 reg = <0x40004400 0x400>; 287 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; 288 resets = <&rctl STM32_RESET(APB1L, 17U)>; 289 interrupts = <38 0>; 290 status = "disabled"; 291 }; 292 usart3: serial@40004800 { 293 compatible = "st,stm32-usart", "st,stm32-uart"; 294 reg = <0x40004800 0x400>; 295 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; 296 resets = <&rctl STM32_RESET(APB1L, 18U)>; 297 interrupts = <39 0>; 298 status = "disabled"; 299 }; 300 uart4: serial@40004c00 { 301 compatible ="st,stm32-uart"; 302 reg = <0x40004c00 0x400>; 303 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; 304 resets = <&rctl STM32_RESET(APB1L, 19U)>; 305 interrupts = <52 0>; 306 status = "disabled"; 307 }; 308 uart5: serial@40005000 { 309 compatible = "st,stm32-uart"; 310 reg = <0x40005000 0x400>; 311 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>; 312 resets = <&rctl STM32_RESET(APB1L, 20U)>; 313 interrupts = <53 0>; 314 status = "disabled"; 315 }; 316 usart6: serial@40011400 { 317 compatible = "st,stm32-usart", "st,stm32-uart"; 318 reg = <0x40011400 0x400>; 319 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>; 320 resets = <&rctl STM32_RESET(APB2, 5U)>; 321 interrupts = <71 0>; 322 status = "disabled"; 323 }; 324 uart7: serial@40007800 { 325 compatible = "st,stm32-uart"; 326 reg = <0x40007800 0x400>; 327 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>; 328 resets = <&rctl STM32_RESET(APB1L, 30U)>; 329 interrupts = <82 0>; 330 status = "disabled"; 331 }; 332 uart8: serial@40007c00 { 333 compatible = "st,stm32-uart"; 334 reg = <0x40007c00 0x400>; 335 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>; 336 resets = <&rctl STM32_RESET(APB1L, 31U)>; 337 interrupts = <83 0>; 338 status = "disabled"; 339 }; 340 341 lpuart1: serial@58000c00 { 342 compatible = "st,stm32-lpuart", "st,stm32-uart"; 343 reg = <0x58000c00 0x400>; 344 clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000008>; 345 resets = <&rctl STM32_RESET(APB4, 3U)>; 346 interrupts = <142 0>; 347 status = "disabled"; 348 }; 349 350 rtc: rtc@58004000 { 351 compatible = "st,stm32-rtc"; 352 reg = <0x58004000 0x400>; 353 interrupts = <41 0>; 354 clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>; 355 prescaler = <32768>; 356 status = "disabled"; 357 }; 358 359 i2c1: i2c@40005400 { 360 compatible = "st,stm32-i2c-v2"; 361 clock-frequency = <I2C_BITRATE_STANDARD>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 reg = <0x40005400 0x400>; 365 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>; 366 interrupts = <31 0>, <32 0>; 367 interrupt-names = "event", "error"; 368 status = "disabled"; 369 }; 370 371 i2c2: i2c@40005800 { 372 compatible = "st,stm32-i2c-v2"; 373 clock-frequency = <I2C_BITRATE_STANDARD>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 reg = <0x40005800 0x400>; 377 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; 378 interrupts = <33 0>, <34 0>; 379 interrupt-names = "event", "error"; 380 status = "disabled"; 381 }; 382 383 i2c3: i2c@40005c00 { 384 compatible = "st,stm32-i2c-v2"; 385 clock-frequency = <I2C_BITRATE_STANDARD>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 reg = <0x40005c00 0x400>; 389 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>; 390 interrupts = <72 0>, <73 0>; 391 interrupt-names = "event", "error"; 392 status = "disabled"; 393 }; 394 395 i2c4: i2c@58001c00 { 396 compatible = "st,stm32-i2c-v2"; 397 clock-frequency = <I2C_BITRATE_STANDARD>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 reg = <0x58001c00 0x400>; 401 clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000080>; 402 interrupts = <95 0>, <96 0>; 403 interrupt-names = "event", "error"; 404 status = "disabled"; 405 }; 406 407 spi1: spi@40013000 { 408 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 reg = <0x40013000 0x400>; 412 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>, 413 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; 414 interrupts = <35 0>; 415 status = "disabled"; 416 }; 417 418 spi2: spi@40003800 { 419 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 reg = <0x40003800 0x400>; 423 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>, 424 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; 425 interrupts = <36 0>; 426 status = "disabled"; 427 }; 428 429 spi3: spi@40003c00 { 430 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 reg = <0x40003c00 0x400>; 434 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>, 435 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; 436 interrupts = <51 0>; 437 status = "disabled"; 438 }; 439 440 spi4: spi@40013400 { 441 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 reg = <0x40013400 0x400>; 445 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>; 446 interrupts = <84 0>; 447 status = "disabled"; 448 }; 449 450 spi5: spi@40015000 { 451 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 reg = <0x40015000 0x400>; 455 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>; 456 interrupts = <85 0>; 457 status = "disabled"; 458 }; 459 460 spi6: spi@58001400 { 461 compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 reg = <0x58001400 0x400>; 465 clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000020>; 466 interrupts = <86 0>; 467 status = "disabled"; 468 }; 469 470 fdcan1: can@4000a000 { 471 compatible = "st,stm32h7-fdcan"; 472 reg = <0x4000a000 0x400>, <0x4000ac00 0x350>; 473 reg-names = "m_can", "message_ram"; 474 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>; 475 interrupts = <19 0>, <21 0>, <63 0>; 476 interrupt-names = "LINE_0", "LINE_1", "CALIB"; 477 bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>; 478 sample-point = <875>; 479 sample-point-data = <875>; 480 status = "disabled"; 481 }; 482 483 fdcan2: can@4000a400 { 484 compatible = "st,stm32h7-fdcan"; 485 reg = <0x4000a400 0x400>, <0x4000ac00 0x6a0>; 486 reg-names = "m_can", "message_ram"; 487 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>; 488 interrupts = <20 0>, <22 0>, <63 0>; 489 interrupt-names = "LINE_0", "LINE_1", "CALIB"; 490 bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>; 491 sample-point = <875>; 492 sample-point-data = <875>; 493 status = "disabled"; 494 }; 495 496 timers1: timers@40010000 { 497 compatible = "st,stm32-timers"; 498 reg = <0x40010000 0x400>; 499 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>; 500 resets = <&rctl STM32_RESET(APB2, 0U)>; 501 interrupts = <24 0>, <25 0>, <26 0>, <27 0>; 502 interrupt-names = "brk", "up", "trgcom", "cc"; 503 st,prescaler = <0>; 504 status = "disabled"; 505 506 pwm { 507 compatible = "st,stm32-pwm"; 508 status = "disabled"; 509 #pwm-cells = <3>; 510 }; 511 }; 512 513 timers2: timers@40000000 { 514 compatible = "st,stm32-timers"; 515 reg = <0x40000000 0x400>; 516 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>; 517 resets = <&rctl STM32_RESET(APB1L, 0U)>; 518 interrupts = <28 0>; 519 interrupt-names = "global"; 520 st,prescaler = <0>; 521 status = "disabled"; 522 523 pwm { 524 compatible = "st,stm32-pwm"; 525 status = "disabled"; 526 #pwm-cells = <3>; 527 }; 528 529 counter { 530 compatible = "st,stm32-counter"; 531 status = "disabled"; 532 }; 533 }; 534 535 timers3: timers@40000400 { 536 compatible = "st,stm32-timers"; 537 reg = <0x40000400 0x400>; 538 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; 539 resets = <&rctl STM32_RESET(APB1L, 1U)>; 540 interrupts = <29 0>; 541 interrupt-names = "global"; 542 st,prescaler = <0>; 543 status = "disabled"; 544 545 pwm { 546 compatible = "st,stm32-pwm"; 547 status = "disabled"; 548 #pwm-cells = <3>; 549 }; 550 551 counter { 552 compatible = "st,stm32-counter"; 553 status = "disabled"; 554 }; 555 }; 556 557 timers4: timers@40000800 { 558 compatible = "st,stm32-timers"; 559 reg = <0x40000800 0x400>; 560 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>; 561 resets = <&rctl STM32_RESET(APB1L, 2U)>; 562 interrupts = <30 0>; 563 interrupt-names = "global"; 564 st,prescaler = <0>; 565 status = "disabled"; 566 567 pwm { 568 compatible = "st,stm32-pwm"; 569 status = "disabled"; 570 #pwm-cells = <3>; 571 }; 572 573 counter { 574 compatible = "st,stm32-counter"; 575 status = "disabled"; 576 }; 577 }; 578 579 timers5: timers@40000c00 { 580 compatible = "st,stm32-timers"; 581 reg = <0x40000c00 0x400>; 582 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>; 583 resets = <&rctl STM32_RESET(APB1L, 3U)>; 584 interrupts = <50 0>; 585 interrupt-names = "global"; 586 st,prescaler = <0>; 587 status = "disabled"; 588 589 pwm { 590 compatible = "st,stm32-pwm"; 591 status = "disabled"; 592 #pwm-cells = <3>; 593 }; 594 595 counter { 596 compatible = "st,stm32-counter"; 597 status = "disabled"; 598 }; 599 }; 600 601 timers6: timers@40001000 { 602 compatible = "st,stm32-timers"; 603 reg = <0x40001000 0x400>; 604 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>; 605 resets = <&rctl STM32_RESET(APB1L, 4U)>; 606 interrupts = <54 0>; 607 interrupt-names = "global"; 608 st,prescaler = <0>; 609 status = "disabled"; 610 611 counter { 612 compatible = "st,stm32-counter"; 613 status = "disabled"; 614 }; 615 }; 616 617 timers7: timers@40001400 { 618 compatible = "st,stm32-timers"; 619 reg = <0x40001400 0x400>; 620 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>; 621 resets = <&rctl STM32_RESET(APB1L, 5U)>; 622 interrupts = <55 0>; 623 interrupt-names = "global"; 624 st,prescaler = <0>; 625 status = "disabled"; 626 627 counter { 628 compatible = "st,stm32-counter"; 629 status = "disabled"; 630 }; 631 }; 632 633 timers8: timers@40010400 { 634 compatible = "st,stm32-timers"; 635 reg = <0x40010400 0x400>; 636 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>; 637 resets = <&rctl STM32_RESET(APB2, 1U)>; 638 interrupts = <43 0>, <44 0>, <45 0>, <46 0>; 639 interrupt-names = "brk", "up", "trgcom", "cc"; 640 st,prescaler = <0>; 641 status = "disabled"; 642 643 pwm { 644 compatible = "st,stm32-pwm"; 645 status = "disabled"; 646 #pwm-cells = <3>; 647 }; 648 }; 649 650 timers12: timers@40001800 { 651 compatible = "st,stm32-timers"; 652 reg = <0x40001800 0x400>; 653 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>; 654 resets = <&rctl STM32_RESET(APB1L, 6U)>; 655 interrupts = <43 0>; 656 interrupt-names = "global"; 657 st,prescaler = <0>; 658 status = "disabled"; 659 660 pwm { 661 compatible = "st,stm32-pwm"; 662 status = "disabled"; 663 #pwm-cells = <3>; 664 }; 665 666 counter { 667 compatible = "st,stm32-counter"; 668 status = "disabled"; 669 }; 670 }; 671 672 timers13: timers@40001c00 { 673 compatible = "st,stm32-timers"; 674 reg = <0x40001c00 0x400>; 675 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>; 676 resets = <&rctl STM32_RESET(APB1L, 7U)>; 677 interrupts = <44 0>; 678 interrupt-names = "global"; 679 st,prescaler = <0>; 680 status = "disabled"; 681 682 pwm { 683 compatible = "st,stm32-pwm"; 684 status = "disabled"; 685 #pwm-cells = <3>; 686 }; 687 688 counter { 689 compatible = "st,stm32-counter"; 690 status = "disabled"; 691 }; 692 }; 693 694 timers14: timers@40002000 { 695 compatible = "st,stm32-timers"; 696 reg = <0x40002000 0x400>; 697 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>; 698 resets = <&rctl STM32_RESET(APB1L, 8U)>; 699 interrupts = <45 0>; 700 interrupt-names = "global"; 701 st,prescaler = <0>; 702 status = "disabled"; 703 704 pwm { 705 compatible = "st,stm32-pwm"; 706 status = "disabled"; 707 #pwm-cells = <3>; 708 }; 709 710 counter { 711 compatible = "st,stm32-counter"; 712 status = "disabled"; 713 }; 714 }; 715 716 timers15: timers@40014000 { 717 compatible = "st,stm32-timers"; 718 reg = <0x40014000 0x400>; 719 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>; 720 resets = <&rctl STM32_RESET(APB2, 16U)>; 721 interrupts = <116 0>; 722 interrupt-names = "global"; 723 st,prescaler = <0>; 724 status = "disabled"; 725 726 pwm { 727 compatible = "st,stm32-pwm"; 728 status = "disabled"; 729 #pwm-cells = <3>; 730 }; 731 732 counter { 733 compatible = "st,stm32-counter"; 734 status = "disabled"; 735 }; 736 }; 737 738 timers16: timers@40014400 { 739 compatible = "st,stm32-timers"; 740 reg = <0x40014400 0x400>; 741 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>; 742 resets = <&rctl STM32_RESET(APB2, 17U)>; 743 interrupts = <117 0>; 744 interrupt-names = "global"; 745 st,prescaler = <0>; 746 status = "disabled"; 747 748 pwm { 749 compatible = "st,stm32-pwm"; 750 status = "disabled"; 751 #pwm-cells = <3>; 752 }; 753 754 counter { 755 compatible = "st,stm32-counter"; 756 status = "disabled"; 757 }; 758 }; 759 760 timers17: timers@40014800 { 761 compatible = "st,stm32-timers"; 762 reg = <0x40014800 0x400>; 763 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>; 764 resets = <&rctl STM32_RESET(APB2, 18U)>; 765 interrupts = <118 0>; 766 interrupt-names = "global"; 767 st,prescaler = <0>; 768 status = "disabled"; 769 770 pwm { 771 compatible = "st,stm32-pwm"; 772 status = "disabled"; 773 #pwm-cells = <3>; 774 }; 775 776 counter { 777 compatible = "st,stm32-counter"; 778 status = "disabled"; 779 }; 780 }; 781 782 lptim1: timers@40002400 { 783 compatible = "st,stm32-lptim"; 784 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 reg = <0x40002400 0x400>; 788 interrupts = <93 1>; 789 interrupt-names = "wakeup"; 790 status = "disabled"; 791 }; 792 793 /* 794 * For devices STM32H742, H743, H750 & H753, revision Y only, 795 * resolution 14 and 12 shall be replaced, respectively, by 796 * STM32_ADC_RES(14, 0x01) and STM32_ADC_RES(12, 0x02) 797 * for all ADCs 798 * See RM0433 for more details 799 */ 800 adc1: adc@40022000 { 801 compatible = "st,stm32-adc"; 802 reg = <0x40022000 0x400>; 803 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>; 804 interrupts = <18 0>; 805 status = "disabled"; 806 #io-channel-cells = <1>; 807 resolutions = <STM32_ADC_RES(16, 0x00) 808 STM32_ADC_RES(14, 0x05) 809 STM32_ADC_RES(12, 0x06) 810 STM32_ADC_RES(10, 0x03) 811 STM32_ADC_RES(8, 0x07)>; 812 sampling-times = <2 3 9 17 33 65 388 811>; 813 st,adc-sequencer = <FULLY_CONFIGURABLE>; 814 }; 815 816 adc2: adc@40022100 { 817 compatible = "st,stm32-adc"; 818 reg = <0x40022100 0x400>; 819 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>; 820 interrupts = <18 0>; 821 status = "disabled"; 822 #io-channel-cells = <1>; 823 resolutions = <STM32_ADC_RES(16, 0x00) 824 STM32_ADC_RES(14, 0x05) 825 STM32_ADC_RES(12, 0x06) 826 STM32_ADC_RES(10, 0x03) 827 STM32_ADC_RES(8, 0x07)>; 828 sampling-times = <2 3 9 17 33 65 388 811>; 829 st,adc-sequencer = <FULLY_CONFIGURABLE>; 830 }; 831 832 /* dual mode: adc1 and adc2 coupled */ 833 adc1_2: adc@40022300 { 834 compatible = "st,stm32-adc"; 835 reg = <0x40022300 0x400>; 836 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>; 837 interrupts = <18 0>; 838 status = "disabled"; 839 #io-channel-cells = <1>; 840 resolutions = <STM32_ADC_RES(16, 0x00) 841 STM32_ADC_RES(14, 0x05) 842 STM32_ADC_RES(12, 0x06) 843 STM32_ADC_RES(10, 0x03) 844 STM32_ADC_RES(8, 0x07)>; 845 sampling-times = <2 3 9 17 33 65 388 811>; 846 st,adc-sequencer = <FULLY_CONFIGURABLE>; 847 }; 848 849 adc3: adc@58026000 { 850 compatible = "st,stm32-adc"; 851 reg = <0x58026000 0x400>; 852 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x01000000>; 853 interrupts = <127 0>; 854 status = "disabled"; 855 #io-channel-cells = <1>; 856 resolutions = <STM32_ADC_RES(16, 0x00) 857 STM32_ADC_RES(14, 0x05) 858 STM32_ADC_RES(12, 0x06) 859 STM32_ADC_RES(10, 0x03) 860 STM32_ADC_RES(8, 0x07)>; 861 sampling-times = <2 3 9 17 33 65 388 811>; 862 st,adc-sequencer = <FULLY_CONFIGURABLE>; 863 }; 864 865 dac1: dac@40007400 { 866 compatible = "st,stm32-dac"; 867 reg = <0x40007400 0x400>; 868 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>; 869 status = "disabled"; 870 #io-channel-cells = <1>; 871 }; 872 873 dma1: dma@40020000 { 874 compatible = "st,stm32-dma-v1"; 875 #dma-cells = <4>; 876 reg = <0x40020000 0x400>; 877 interrupts = <11 0>, <12 0>, <13 0>, <14 0>, <15 0>, <16 0>, 878 <17 0>, <47 0>; 879 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>; 880 st,mem2mem; 881 dma-offset = <0>; 882 dma-requests = <8>; 883 status = "disabled"; 884 }; 885 886 dma2: dma@40020400 { 887 compatible = "st,stm32-dma-v1"; 888 #dma-cells = <4>; 889 reg = <0x40020400 0x400>; 890 interrupts = <56 0>, <57 0>, <58 0>, <59 0>, <60 0>, <68 0>, 891 <69 0>, <70 0>; 892 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>; 893 st,mem2mem; 894 dma-offset = <8>; 895 dma-requests = <8>; 896 status = "disabled"; 897 }; 898 899 bdma1: bdma@58025400 { 900 compatible = "st,stm32-bdma"; 901 #dma-cells = <4>; 902 reg = <0x58025400 0x400>; 903 interrupts = <129 0>, <130 0>, <131 0>, <132 0>, <133 0>, <134 0>, 904 <135 0>, <136 0>; 905 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00200000>; 906 st,mem2mem; 907 dma-offset = <0>; 908 dma-requests = <8>; 909 status = "disabled"; 910 }; 911 912 dmamux1: dmamux@40020800 { 913 compatible = "st,stm32-dmamux"; 914 #dma-cells = <3>; 915 reg = <0x40020800 0x400>; 916 interrupts = <102 0>; 917 /* dmamux1 has no dedicated clock, so we enable dma1 clock */ 918 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>; 919 dma-channels = <16>; 920 dma-generators = <8>; 921 status = "disabled"; 922 /* 923 * dma-requests is different among h7 socs, 924 * so we set in specific dtsi files 925 */ 926 }; 927 928 dmamux2: dmamux@58025800 { 929 compatible = "st,stm32-dmamux"; 930 #dma-cells = <3>; 931 reg = <0x58025800 0x400>; 932 interrupts = <128 0>; 933 /* dmamux2 has no dedicated clock, so we enable bdma clock */ 934 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00200000>; 935 dma-channels = <8>; 936 dma-generators = <8>; 937 status = "disabled"; 938 /* 939 * dma-requests is different among h7 socs, 940 * so we set in specific dtsi files 941 */ 942 }; 943 944 rng: rng@48021800 { 945 compatible = "st,stm32-rng"; 946 reg = <0x48021800 0x400>; 947 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>; 948 interrupts = <80 0>; 949 status = "disabled"; 950 }; 951 952 sdmmc1: sdmmc@52007000 { 953 compatible = "st,stm32-sdmmc"; 954 reg = <0x52007000 0x400>; 955 clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00010000>, 956 <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>; 957 resets = <&rctl STM32_RESET(AHB3, 16U)>; 958 interrupts = <49 0>; 959 status = "disabled"; 960 }; 961 962 sdmmc2: sdmmc@48022400 { 963 compatible = "st,stm32-sdmmc"; 964 reg = <0x48022400 0x400>; 965 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000200>, 966 <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>; 967 resets = <&rctl STM32_RESET(AHB2, 9U)>; 968 interrupts = <124 0>; 969 status = "disabled"; 970 }; 971 972 mac: ethernet@40028000 { 973 compatible = "st,stm32-ethernet"; 974 reg = <0x40028000 0x8000>; 975 interrupts = <61 0>; 976 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; 977 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00008000>, 978 <&rcc STM32_CLOCK_BUS_AHB1 0x00010000>, 979 <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>; 980 status = "disabled"; 981 }; 982 983 fmc: memory-controller@52004000 { 984 compatible = "st,stm32h7-fmc"; 985 reg = <0x52004000 0x400>; 986 clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00001000>; 987 status = "disabled"; 988 989 sdram: sdram { 990 compatible = "st,stm32-fmc-sdram"; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 status = "disabled"; 994 }; 995 }; 996 997 backup_sram: memory@38800000 { 998 compatible = "zephyr,memory-region", "st,stm32-backup-sram"; 999 reg = <0x38800000 DT_SIZE_K(4)>; 1000 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x10000000>; 1001 zephyr,memory-region = "BACKUP_SRAM"; 1002 status = "disabled"; 1003 }; 1004 1005 quadspi: quadspi@52005000 { 1006 compatible = "st,stm32-qspi"; 1007 #address-cells = <0x1>; 1008 #size-cells = <0x0>; 1009 reg = <0x52005000 0x34>; 1010 interrupts = <92 0>; 1011 clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00004000>; 1012 status = "disabled"; 1013 }; 1014 }; 1015 1016 die_temp: dietemp { 1017 compatible = "st,stm32-temp-cal"; 1018 ts-cal1-addr = <0x1FF1E820>; 1019 ts-cal2-addr = <0x1FF1E840>; 1020 ts-cal1-temp = <30>; 1021 ts-cal2-temp = <110>; 1022 ts-cal-vrefanalog = <3300>; 1023 ts-cal-resolution = <16>; 1024 io-channels = <&adc3 18>; 1025 status = "disabled"; 1026 }; 1027 1028 vbat: vbat { 1029 compatible = "st,stm32-vbat"; 1030 ratio = <4>; 1031 status = "disabled"; 1032 }; 1033 1034 vref: vref { 1035 compatible = "st,stm32-vref"; 1036 vrefint-cal-addr = <0x1FF1E860>; 1037 vrefint-cal-mv = <3300>; 1038 status = "disabled"; 1039 }; 1040}; 1041 1042&nvic { 1043 arm,num-irq-priority-bits = <4>; 1044}; 1045
