1 /* 2 * Copyright (c) 2016 Nordic Semiconductor ASA 3 * Copyright (c) 2016 Vinayak Kariappa Chettimada 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 /* 9 * PDU fields sizes 10 */ 11 12 #define PDU_PREAMBLE_SIZE(phy) (phy&0x3) 13 #define PDU_ACCESS_ADDR_SIZE 4 14 #define PDU_HEADER_SIZE 2 15 #define PDU_MIC_SIZE 4 16 #define PDU_CRC_SIZE 3 17 #define PDU_OVERHEAD_SIZE(phy) (PDU_PREAMBLE_SIZE(phy) + \ 18 PDU_ACCESS_ADDR_SIZE + \ 19 PDU_HEADER_SIZE + \ 20 PDU_CRC_SIZE) 21 22 #define BDADDR_SIZE 6 23 #define ADVA_SIZE BDADDR_SIZE 24 #define SCANA_SIZE BDADDR_SIZE 25 #define INITA_SIZE BDADDR_SIZE 26 #define TARGETA_SIZE BDADDR_SIZE 27 #define LLDATA_SIZE 22 28 29 /* Constant offsets in extended header (TargetA is present in PDUs with AdvA) */ 30 #define ADVA_OFFSET 0 31 #define TGTA_OFFSET (ADVA_OFFSET + BDADDR_SIZE) 32 33 #define BYTES2US(bytes, phy) (((bytes)<<3)/BIT((phy&0x3)>>1)) 34 35 /* Advertisement channel minimum payload size */ 36 #define PDU_AC_PAYLOAD_SIZE_MIN 1 37 /* Advertisement channel maximum legacy payload size */ 38 #define PDU_AC_LEG_PAYLOAD_SIZE_MAX 37 39 /* Advertisement channel maximum legacy advertising/scan data size */ 40 #define PDU_AC_LEG_DATA_SIZE_MAX 31 41 42 #if defined(CONFIG_BT_CTLR_ADV_EXT) 43 /* Advertisement channel maximum extended payload size */ 44 #define PDU_AC_EXT_PAYLOAD_SIZE_MAX 255 45 46 /* Extended Scan and Periodic Sync Rx PDU time reservation */ 47 #if defined(CONFIG_BT_CTLR_SCAN_AUX_SYNC_RESERVE_MIN) 48 #define PDU_AC_EXT_PAYLOAD_RX_SIZE 0U 49 #else /* !CONFIG_BT_CTLR_SCAN_AUX_SYNC_RESERVE_MIN */ 50 #define PDU_AC_EXT_PAYLOAD_RX_SIZE PDU_AC_EXT_PAYLOAD_SIZE_MAX 51 #endif /* !CONFIG_BT_CTLR_SCAN_AUX_SYNC_RESERVE_MIN */ 52 53 #define PDU_AC_EXT_HEADER_SIZE_MIN offsetof(struct pdu_adv_com_ext_adv, \ 54 ext_hdr_adv_data) 55 #define PDU_AC_EXT_HEADER_SIZE_MAX 63 56 /* TODO: PDU_AC_EXT_PAYLOAD_OVERHEAD can be reduced based on supported 57 * features, like omitting support for periodic advertising will reduce 58 * 18 octets in the Common Extended Advertising Payload Format. 59 */ 60 #define PDU_AC_EXT_PAYLOAD_OVERHEAD (PDU_AC_EXT_HEADER_SIZE_MIN + \ 61 PDU_AC_EXT_HEADER_SIZE_MAX) 62 #endif /* CONFIG_BT_CTLR_ADV_EXT */ 63 64 #if defined(CONFIG_BT_CTLR_ADV_EXT) && defined(CONFIG_BT_BROADCASTER) 65 #define PDU_AC_PAYLOAD_SIZE_MAX MAX(MIN((PDU_AC_EXT_PAYLOAD_OVERHEAD + \ 66 CONFIG_BT_CTLR_ADV_DATA_LEN_MAX), \ 67 PDU_AC_EXT_PAYLOAD_SIZE_MAX), \ 68 PDU_AC_LEG_PAYLOAD_SIZE_MAX) 69 #define PDU_AC_EXT_AD_DATA_LEN_MAX (PDU_AC_PAYLOAD_SIZE_MAX - \ 70 PDU_AC_EXT_PAYLOAD_OVERHEAD) 71 #else /* !CONFIG_BT_CTLR_ADV_EXT || !CONFIG_BT_BROADCASTER */ 72 #define PDU_AC_PAYLOAD_SIZE_MAX PDU_AC_LEG_PAYLOAD_SIZE_MAX 73 #endif /* !CONFIG_BT_CTLR_ADV_EXT || !CONFIG_BT_BROADCASTER */ 74 75 /* Link Layer header size of Adv PDU. Assumes pdu_adv is packed */ 76 #define PDU_AC_LL_HEADER_SIZE (offsetof(struct pdu_adv, payload)) 77 78 /* Link Layer Advertisement channel maximum PDU buffer size */ 79 #define PDU_AC_LL_SIZE_MAX (PDU_AC_LL_HEADER_SIZE + PDU_AC_PAYLOAD_SIZE_MAX) 80 81 /* Advertisement channel Access Address */ 82 #define PDU_AC_ACCESS_ADDR 0x8e89bed6 83 84 /* Advertisement channel CRC init value */ 85 #define PDU_AC_CRC_IV 0x555555 86 87 /* CRC polynomial */ 88 #define PDU_CRC_POLYNOMIAL ((0x5bUL) | ((0x06UL) << 8) | ((0x00UL) << 16)) 89 90 /* Data channel minimum payload size and time in us */ 91 #define PDU_DC_PAYLOAD_SIZE_MIN 27 92 #define PDU_DC_PAYLOAD_TIME_MIN 328 93 #define PDU_DC_PAYLOAD_TIME_MIN_CODED 2704 94 95 /* Data channel maximum payload size and time in us */ 96 #define PDU_DC_PAYLOAD_SIZE_MAX 251 97 #define PDU_DC_PAYLOAD_TIME_MAX_CODED 17040 98 99 #if defined(CONFIG_BT_CTLR_DF) 100 #define PDU_DC_PAYLOAD_TIME_MAX 2128 101 #else /* !CONFIG_BT_CTLR_DF */ 102 #define PDU_DC_PAYLOAD_TIME_MAX 2120 103 #endif /* !CONFIG_BT_CTLR_DF */ 104 105 /* Data channel control PDU maximum payload size */ 106 #if defined(CONFIG_BT_CONN) 107 #if defined(CONFIG_BT_CTLR_CONN_ISO) 108 #if defined(CONFIG_BT_CENTRAL) && defined(CONFIG_BT_PERIPHERAL) 109 /* Isochronous Central and Peripheral */ 110 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(cis_req) 111 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(cis_req) 112 #elif defined(CONFIG_BT_CENTRAL) 113 /* Isochronous Central */ 114 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(cis_req) 115 #if defined(CONFIG_BT_CTLR_CONN_PARAM_REQ) 116 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_param_req) 117 #elif defined(CONFIG_BT_CTLR_LE_ENC) 118 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_rsp) 119 #else /* !CONFIG_BT_CTLR_LE_ENC */ 120 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(cis_rsp) 121 #endif /* !CONFIG_BT_CTLR_LE_ENC */ 122 #elif defined(CONFIG_BT_PERIPHERAL) 123 /* Isochronous Peripheral */ 124 #if defined(CONFIG_BT_CTLR_CONN_PARAM_REQ) 125 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_param_req) 126 #elif defined(CONFIG_BT_CTLR_LE_ENC) 127 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_rsp) 128 #else /* !CONFIG_BT_CTLR_LE_ENC */ 129 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(cis_rsp) 130 #endif /* !CONFIG_BT_CTLR_LE_ENC */ 131 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(cis_req) 132 #endif /* !CONFIG_BT_PERIPHERAL */ 133 134 #elif defined(CONFIG_BT_CTLR_CONN_PARAM_REQ) 135 /* Central and Peripheral with Connection Parameter Request */ 136 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_param_req) 137 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_param_req) 138 139 #elif defined(CONFIG_BT_CTLR_LE_ENC) 140 #if defined(CONFIG_BT_CENTRAL) && defined(CONFIG_BT_PERIPHERAL) 141 /* Central and Peripheral with encryption */ 142 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_req) 143 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_req) 144 #elif defined(CONFIG_BT_CENTRAL) 145 /* Central with encryption */ 146 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_req) 147 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_rsp) 148 #elif defined(CONFIG_BT_PERIPHERAL) 149 /* Peripheral with encryption */ 150 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_rsp) 151 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(enc_req) 152 #endif /* !CONFIG_BT_PERIPHERAL */ 153 154 #else /* !CONFIG_BT_CTLR_LE_ENC */ 155 #if defined(CONFIG_BT_CENTRAL) && defined(CONFIG_BT_PERIPHERAL) 156 /* Central and Peripheral without encryption */ 157 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_update_ind) 158 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_update_ind) 159 #elif defined(CONFIG_BT_CENTRAL) 160 /* Central without encryption */ 161 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_update_ind) 162 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(feature_rsp) 163 #elif defined(CONFIG_BT_PERIPHERAL) 164 /* Peripheral without encryption */ 165 #define PDU_DC_CTRL_TX_SIZE_MAX PDU_DATA_LLCTRL_LEN(feature_rsp) 166 #define PDU_DC_CTRL_RX_SIZE_MAX PDU_DATA_LLCTRL_LEN(conn_update_ind) 167 #endif /* !CONFIG_BT_PERIPHERAL */ 168 #endif /* !CONFIG_BT_CTLR_LE_ENC */ 169 170 #else /* !CONFIG_BT_CONN */ 171 #define PDU_DC_CTRL_TX_SIZE_MAX 0U 172 #define PDU_DC_CTRL_RX_SIZE_MAX 0U 173 #endif /* !CONFIG_BT_CONN */ 174 175 /* Link Layer header size of Data PDU. Assumes pdu_data is packed */ 176 #define PDU_DC_LL_HEADER_SIZE (offsetof(struct pdu_data, lldata)) 177 178 /* Link Layer Max size of an empty PDU. TODO: Remove; only used in Nordic LLL */ 179 #define PDU_EM_LL_SIZE_MAX (PDU_DC_LL_HEADER_SIZE) 180 181 /* Link Layer header size of BIS PDU. Assumes pdu_bis is packed */ 182 #define PDU_BIS_LL_HEADER_SIZE (offsetof(struct pdu_bis, payload)) 183 184 /* Event Active Clock Jitter */ 185 #define EVENT_CLOCK_JITTER_US 2 186 /* Event interframe timings */ 187 #define EVENT_IFS_US 150 188 /* Standard allows 2 us timing uncertainty inside the event */ 189 #define EVENT_IFS_MAX_US (EVENT_IFS_US + EVENT_CLOCK_JITTER_US) 190 /* Controller will layout extended adv with minimum separation */ 191 #define EVENT_MAFS_US 300 192 /* Standard allows 2 us timing uncertainty inside the event */ 193 #define EVENT_MAFS_MAX_US (EVENT_MAFS_US + EVENT_CLOCK_JITTER_US) 194 /* Controller defined back to back transmit MAFS for extended advertising */ 195 #define EVENT_B2B_MAFS_US (CONFIG_BT_CTLR_ADV_AUX_PDU_BACK2BACK_AFS) 196 /* Controller defined back to back transmit MAFS for periodic advertising */ 197 #define EVENT_SYNC_B2B_MAFS_US (CONFIG_BT_CTLR_ADV_SYNC_PDU_BACK2BACK_AFS) 198 /* Minimum Subevent Space timings */ 199 #define EVENT_MSS_US 150 200 /* Standard allows 2 us timing uncertainty inside the event */ 201 #define EVENT_MSS_MAX_US (EVENT_MSS_US + EVENT_CLOCK_JITTER_US) 202 203 /* Instant maximum value and maximum latency (or delta) past the instant */ 204 #define EVENT_INSTANT_MAX 0xffff 205 #define EVENT_INSTANT_LATENCY_MAX 0x7fff 206 207 /* Channel Map Unused channels count minimum */ 208 #define CHM_USED_COUNT_MIN 2U 209 210 /* Channel Map hop count minimum and maximum */ 211 #define CHM_HOP_COUNT_MIN 5U 212 #define CHM_HOP_COUNT_MAX 16U 213 214 /* Offset Units field encoding */ 215 #define OFFS_UNIT_BITS 13 216 #define OFFS_UNIT_30_US 30 217 #define OFFS_UNIT_300_US 300 218 #define OFFS_UNIT_VALUE_30_US 0 219 #define OFFS_UNIT_VALUE_300_US 1 220 /* Value specified in BT Spec. Vol 6, Part B, section 2.3.4.6 */ 221 #define OFFS_ADJUST_US 2457600UL 222 223 /* Macros for getting offset/phy from pdu_adv_aux_ptr */ 224 #define PDU_ADV_AUX_PTR_OFFSET_GET(aux_ptr) ((aux_ptr)->offs_phy_packed[0] | \ 225 (((aux_ptr)->offs_phy_packed[1] & 0x1F) << 8)) 226 #define PDU_ADV_AUX_PTR_PHY_GET(aux_ptr) (((aux_ptr)->offs_phy_packed[1] >> 5) & 0x07) 227 228 /* Advertiser's Sleep Clock Accuracy Value */ 229 #define SCA_500_PPM 500 /* 51 ppm to 500 ppm */ 230 #define SCA_50_PPM 50 /* 0 ppm to 50 ppm */ 231 #define SCA_VALUE_500_PPM 0 /* 51 ppm to 500 ppm */ 232 #define SCA_VALUE_50_PPM 1 /* 0 ppm to 50 ppm */ 233 234 /* Sleep Clock Accuracy, calculate drift in microseconds */ 235 #define SCA_DRIFT_50_PPM_US(t) (((t) * 50UL) / 1000000UL) 236 #define SCA_DRIFT_500_PPM_US(t) (((t) * 500UL) / 1000000UL) 237 238 /* transmitWindowDelay times (us) */ 239 #define WIN_DELAY_LEGACY 1250 240 #define WIN_DELAY_UNCODED 2500 241 #define WIN_DELAY_CODED 3750 242 243 /* Channel Map Size */ 244 #define PDU_CHANNEL_MAP_SIZE 5 245 246 /* Advertising Data */ 247 #define PDU_ADV_DATA_HEADER_SIZE 2U 248 #define PDU_ADV_DATA_HEADER_LEN_SIZE 1U 249 #define PDU_ADV_DATA_HEADER_TYPE_SIZE 1U 250 #define PDU_ADV_DATA_HEADER_LEN_OFFSET 0U 251 #define PDU_ADV_DATA_HEADER_TYPE_OFFSET 1U 252 #define PDU_ADV_DATA_HEADER_DATA_OFFSET 2U 253 254 /* Advertising Data Types in ACAD */ 255 #define PDU_ADV_DATA_TYPE_CHANNEL_MAP_UPDATE_IND 0x28 256 257 /* 258 * Macros to return correct Data Channel PDU time 259 * Note: formula is valid for 1M, 2M and Coded S8 260 * see BT spec Version 5.1 Vol 6. Part B, chapters 2.1 and 2.2 261 * for packet formats and thus lengths 262 */ 263 264 #define PHY_LEGACY 0 265 #define PHY_1M BIT(0) 266 #define PHY_2M BIT(1) 267 #define PHY_CODED BIT(2) 268 #define PHY_FLAGS_S2 0 269 #define PHY_FLAGS_S8 BIT(0) 270 271 /* Macros for getting/setting did/sid from pdu_adv_adi */ 272 #define PDU_ADV_ADI_DID_GET(adi) ((adi)->did_sid_packed[0] | \ 273 (((adi)->did_sid_packed[1] & 0x0F) << 8)) 274 #define PDU_ADV_ADI_SID_GET(adi) (((adi)->did_sid_packed[1] >> 4) & 0x0F) 275 #define PDU_ADV_ADI_SID_SET(adi, sid) (adi)->did_sid_packed[1] = (((sid) << 4) + \ 276 ((adi)->did_sid_packed[1] & 0x0F)) 277 #define PDU_ADV_ADI_DID_SID_SET(adi, did, sid) \ 278 do { \ 279 (adi)->did_sid_packed[0] = (did) & 0xFF; \ 280 (adi)->did_sid_packed[1] = (((did) >> 8) & 0x0F) + ((sid) << 4); \ 281 } while (0) 282 283 #if defined(CONFIG_BT_CTLR_PHY_CODED) 284 #define CODED_PHY_PREAMBLE_TIME_US 80 285 #define CODED_PHY_ACCESS_ADDRESS_TIME_US 256 286 #define CODED_PHY_CI_TIME_US 16 287 #define CODED_PHY_TERM1_TIME_US 24 288 #define CODED_PHY_CRC_SIZE 24 289 #define CODED_PHY_TERM2_SIZE 3 290 291 #define FEC_BLOCK1_US ((CODED_PHY_ACCESS_ADDRESS_TIME_US) + \ 292 (CODED_PHY_CI_TIME_US) + \ 293 (CODED_PHY_TERM1_TIME_US)) 294 295 /* cs = 0, S2 coding scheme, use PHY_FLAGS_S2 296 * cs = 1, S8 coding scheme, use PHY_FLAGS_S8 297 * 298 * Not using the term CI, Coding Indicator, where in the Spec its defined value 299 * of 0 is S8 encoding, 1 is S2 encoding. 300 */ 301 #define FEC_BLOCK2_US(octets, mic, cs) (((((PDU_HEADER_SIZE) + \ 302 (octets) + \ 303 (mic)) << 3) + \ 304 (CODED_PHY_CRC_SIZE) + \ 305 (CODED_PHY_TERM2_SIZE)) << \ 306 (1 + (((cs) & 0x01) << 1))) 307 308 #define PDU_US(octets, mic, phy, cs) (((phy) & PHY_CODED) ? \ 309 ((CODED_PHY_PREAMBLE_TIME_US) + \ 310 (FEC_BLOCK1_US) + \ 311 FEC_BLOCK2_US((octets), (mic), \ 312 (cs))) : \ 313 (((PDU_PREAMBLE_SIZE(phy) + \ 314 (PDU_ACCESS_ADDR_SIZE) + \ 315 (PDU_HEADER_SIZE) + \ 316 (octets) + \ 317 (mic) + \ 318 (PDU_CRC_SIZE)) << 3) / \ 319 BIT(((phy) & 0x03) >> 1))) 320 321 #define PDU_MAX_US(octets, mic, phy) PDU_US((octets), (mic), (phy), \ 322 PHY_FLAGS_S8) 323 324 #else /* !CONFIG_BT_CTLR_PHY_CODED */ 325 #define PDU_US(octets, mic, phy, cs) (((PDU_PREAMBLE_SIZE(phy) + \ 326 (PDU_ACCESS_ADDR_SIZE) + \ 327 (PDU_HEADER_SIZE) + \ 328 (octets) + \ 329 (mic) + \ 330 (PDU_CRC_SIZE)) << 3) / \ 331 BIT(((phy) & 0x03) >> 1)) 332 333 #define PDU_MAX_US(octets, mic, phy) PDU_US((octets), (mic), (phy), 0) 334 #endif /* !CONFIG_BT_CTLR_PHY_CODED */ 335 336 #define PDU_DC_MAX_US(octets, phy) PDU_MAX_US((octets), (PDU_MIC_SIZE), (phy)) 337 338 #define PDU_DC_US(octets, mic, phy, cs) PDU_US((octets), (mic), (phy), (cs)) 339 340 #define PDU_AC_MAX_US(octets, phy) PDU_MAX_US((octets), 0, (phy)) 341 342 #define PDU_AC_US(octets, phy, cs) PDU_US((octets), 0, (phy), (cs)) 343 344 #define PDU_BIS_MAX_US(octets, enc, phy) PDU_MAX_US((octets), \ 345 ((enc) ? \ 346 (PDU_MIC_SIZE) : 0), \ 347 (phy)) 348 349 #define PDU_BIS_US(octets, enc, phy, s8) PDU_US((octets), \ 350 ((enc) ? (PDU_MIC_SIZE) : 0), \ 351 (phy), (s8)) 352 353 #define PDU_CIS_MAX_US(octets, enc, phy) PDU_MAX_US((octets), \ 354 ((enc) ? \ 355 (PDU_MIC_SIZE) : 0), \ 356 (phy)) 357 #define PDU_CIS_OFFSET_MIN_US 500U 358 359 struct pdu_adv_adv_ind { 360 uint8_t addr[BDADDR_SIZE]; 361 uint8_t data[PDU_AC_LEG_DATA_SIZE_MAX]; 362 } __packed; 363 364 struct pdu_adv_direct_ind { 365 uint8_t adv_addr[BDADDR_SIZE]; 366 uint8_t tgt_addr[BDADDR_SIZE]; 367 } __packed; 368 369 struct pdu_adv_scan_rsp { 370 uint8_t addr[BDADDR_SIZE]; 371 uint8_t data[PDU_AC_LEG_DATA_SIZE_MAX]; 372 } __packed; 373 374 struct pdu_adv_scan_req { 375 uint8_t scan_addr[BDADDR_SIZE]; 376 uint8_t adv_addr[BDADDR_SIZE]; 377 } __packed; 378 379 struct pdu_adv_connect_ind { 380 uint8_t init_addr[BDADDR_SIZE]; 381 uint8_t adv_addr[BDADDR_SIZE]; 382 struct { 383 uint8_t access_addr[4]; 384 uint8_t crc_init[3]; 385 uint8_t win_size; 386 uint16_t win_offset; 387 uint16_t interval; 388 uint16_t latency; 389 uint16_t timeout; 390 uint8_t chan_map[PDU_CHANNEL_MAP_SIZE]; 391 #ifdef CONFIG_LITTLE_ENDIAN 392 uint8_t hop:5; 393 uint8_t sca:3; 394 #else 395 uint8_t sca:3; 396 uint8_t hop:5; 397 #endif /* CONFIG_LITTLE_ENDIAN */ 398 399 } __packed; 400 } __packed; 401 402 struct pdu_adv_ext_hdr { 403 #ifdef CONFIG_LITTLE_ENDIAN 404 uint8_t adv_addr:1; 405 uint8_t tgt_addr:1; 406 uint8_t cte_info:1; 407 uint8_t adi:1; 408 uint8_t aux_ptr:1; 409 uint8_t sync_info:1; 410 uint8_t tx_pwr:1; 411 uint8_t rfu:1; 412 #else 413 uint8_t rfu:1; 414 uint8_t tx_pwr:1; 415 uint8_t sync_info:1; 416 uint8_t aux_ptr:1; 417 uint8_t adi:1; 418 uint8_t cte_info:1; 419 uint8_t tgt_addr:1; 420 uint8_t adv_addr:1; 421 #endif /* CONFIG_LITTLE_ENDIAN */ 422 uint8_t data[0]; 423 } __packed; 424 425 struct pdu_adv_com_ext_adv { 426 #ifdef CONFIG_LITTLE_ENDIAN 427 uint8_t ext_hdr_len:6; 428 uint8_t adv_mode:2; 429 #else 430 uint8_t adv_mode:2; 431 uint8_t ext_hdr_len:6; 432 #endif /* CONFIG_LITTLE_ENDIAN */ 433 union { 434 struct pdu_adv_ext_hdr ext_hdr; 435 uint8_t ext_hdr_adv_data[0]; 436 }; 437 } __packed; 438 439 enum pdu_adv_mode { 440 EXT_ADV_MODE_NON_CONN_NON_SCAN = 0x00, 441 EXT_ADV_MODE_CONN_NON_SCAN = 0x01, 442 EXT_ADV_MODE_NON_CONN_SCAN = 0x02, 443 }; 444 445 #define PDU_ADV_SID_COUNT 16 446 447 struct pdu_adv_adi { 448 /* did:12 449 * sid:4 450 * NOTE: This layout as bitfields is not portable for BE using 451 * endianness conversion macros. 452 */ 453 uint8_t did_sid_packed[2]; 454 } __packed; 455 456 struct pdu_adv_aux_ptr { 457 #ifdef CONFIG_LITTLE_ENDIAN 458 uint8_t chan_idx:6; 459 uint8_t ca:1; 460 uint8_t offs_units:1; 461 #else 462 uint8_t offs_units:1; 463 uint8_t ca:1; 464 uint8_t chan_idx:6; 465 #endif /* CONFIG_LITTLE_ENDIAN */ 466 /* offs:13 467 * phy:3 468 * NOTE: This layout as bitfields is not portable for BE using 469 * endianness conversion macros. 470 */ 471 uint8_t offs_phy_packed[2]; 472 } __packed; 473 474 enum pdu_adv_aux_ptr_ca { 475 EXT_ADV_AUX_PTR_CA_500_PPM = 0x00, 476 EXT_ADV_AUX_PTR_CA_50_PPM = 0x01, 477 }; 478 479 enum pdu_adv_offs_units { 480 EXT_ADV_AUX_PTR_OFFS_UNITS_30 = 0x00, 481 EXT_ADV_AUX_PTR_OFFS_UNITS_300 = 0x01, 482 }; 483 484 enum pdu_adv_aux_phy { 485 EXT_ADV_AUX_PHY_LE_1M = 0x00, 486 EXT_ADV_AUX_PHY_LE_2M = 0x01, 487 EXT_ADV_AUX_PHY_LE_CODED = 0x02, 488 }; 489 490 struct pdu_adv_sync_info { 491 #ifdef CONFIG_LITTLE_ENDIAN 492 uint16_t offs:13; 493 uint16_t offs_units:1; 494 uint16_t offs_adjust:1; 495 uint16_t rfu:1; 496 #else 497 uint16_t rfu:1; 498 uint16_t offs_adjust:1; 499 uint16_t offs_units:1; 500 uint16_t offs:13; 501 #endif /* CONFIG_LITTLE_ENDIAN */ 502 uint16_t interval; 503 uint8_t sca_chm[PDU_CHANNEL_MAP_SIZE]; 504 uint32_t aa; 505 uint8_t crc_init[3]; 506 uint16_t evt_cntr; 507 } __packed; 508 509 #define PDU_SYNC_INFO_SCA_CHM_SCA_BYTE_OFFSET 4 510 #define PDU_SYNC_INFO_SCA_CHM_SCA_BIT_POS 5 511 #define PDU_SYNC_INFO_SCA_CHM_SCA_BIT_MASK \ 512 (0x07 << (PDU_SYNC_INFO_SCA_CHM_SCA_BIT_POS)) 513 514 struct pdu_adv_sync_chm_upd_ind { 515 uint8_t chm[PDU_CHANNEL_MAP_SIZE]; 516 uint16_t instant; 517 } __packed; 518 519 enum pdu_adv_type { 520 PDU_ADV_TYPE_ADV_IND = 0x00, 521 PDU_ADV_TYPE_DIRECT_IND = 0x01, 522 PDU_ADV_TYPE_NONCONN_IND = 0x02, 523 PDU_ADV_TYPE_SCAN_REQ = 0x03, 524 PDU_ADV_TYPE_AUX_SCAN_REQ = PDU_ADV_TYPE_SCAN_REQ, 525 PDU_ADV_TYPE_SCAN_RSP = 0x04, 526 PDU_ADV_TYPE_ADV_IND_SCAN_RSP = 0x05, 527 PDU_ADV_TYPE_CONNECT_IND = 0x05, 528 PDU_ADV_TYPE_AUX_CONNECT_REQ = PDU_ADV_TYPE_CONNECT_IND, 529 PDU_ADV_TYPE_SCAN_IND = 0x06, 530 PDU_ADV_TYPE_EXT_IND = 0x07, 531 PDU_ADV_TYPE_AUX_ADV_IND = PDU_ADV_TYPE_EXT_IND, 532 PDU_ADV_TYPE_AUX_SCAN_RSP = PDU_ADV_TYPE_EXT_IND, 533 PDU_ADV_TYPE_AUX_SYNC_IND = PDU_ADV_TYPE_EXT_IND, 534 PDU_ADV_TYPE_AUX_CHAIN_IND = PDU_ADV_TYPE_EXT_IND, 535 PDU_ADV_TYPE_AUX_CONNECT_RSP = 0x08, 536 } __packed; 537 538 struct pdu_adv { 539 #ifdef CONFIG_LITTLE_ENDIAN 540 uint8_t type:4; 541 uint8_t rfu:1; 542 uint8_t chan_sel:1; 543 uint8_t tx_addr:1; 544 uint8_t rx_addr:1; 545 #else 546 uint8_t rx_addr:1; 547 uint8_t tx_addr:1; 548 uint8_t chan_sel:1; 549 uint8_t rfu:1; 550 uint8_t type:4; 551 #endif /* CONFIG_LITTLE_ENDIAN */ 552 553 uint8_t len; 554 555 union { 556 uint8_t payload[0]; 557 struct pdu_adv_adv_ind adv_ind; 558 struct pdu_adv_direct_ind direct_ind; 559 struct pdu_adv_scan_req scan_req; 560 struct pdu_adv_scan_rsp scan_rsp; 561 struct pdu_adv_connect_ind connect_ind; 562 563 #if defined(CONFIG_BT_CTLR_ADV_EXT) 564 struct pdu_adv_com_ext_adv adv_ext_ind; 565 #endif /* CONFIG_BT_CTLR_ADV_EXT */ 566 } __packed; 567 } __packed; 568 569 enum pdu_data_llid { 570 PDU_DATA_LLID_RESV = 0x00, 571 PDU_DATA_LLID_DATA_CONTINUE = 0x01, 572 PDU_DATA_LLID_DATA_START = 0x02, 573 PDU_DATA_LLID_CTRL = 0x03, 574 }; 575 576 enum pdu_data_llctrl_type { 577 PDU_DATA_LLCTRL_TYPE_CONN_UPDATE_IND = 0x00, 578 PDU_DATA_LLCTRL_TYPE_CHAN_MAP_IND = 0x01, 579 PDU_DATA_LLCTRL_TYPE_TERMINATE_IND = 0x02, 580 PDU_DATA_LLCTRL_TYPE_ENC_REQ = 0x03, 581 PDU_DATA_LLCTRL_TYPE_ENC_RSP = 0x04, 582 PDU_DATA_LLCTRL_TYPE_START_ENC_REQ = 0x05, 583 PDU_DATA_LLCTRL_TYPE_START_ENC_RSP = 0x06, 584 PDU_DATA_LLCTRL_TYPE_UNKNOWN_RSP = 0x07, 585 PDU_DATA_LLCTRL_TYPE_FEATURE_REQ = 0x08, 586 PDU_DATA_LLCTRL_TYPE_FEATURE_RSP = 0x09, 587 PDU_DATA_LLCTRL_TYPE_PAUSE_ENC_REQ = 0x0A, 588 PDU_DATA_LLCTRL_TYPE_PAUSE_ENC_RSP = 0x0B, 589 PDU_DATA_LLCTRL_TYPE_VERSION_IND = 0x0C, 590 PDU_DATA_LLCTRL_TYPE_REJECT_IND = 0x0D, 591 PDU_DATA_LLCTRL_TYPE_PER_INIT_FEAT_XCHG = 0x0E, 592 PDU_DATA_LLCTRL_TYPE_CONN_PARAM_REQ = 0x0F, 593 PDU_DATA_LLCTRL_TYPE_CONN_PARAM_RSP = 0x10, 594 PDU_DATA_LLCTRL_TYPE_REJECT_EXT_IND = 0x11, 595 PDU_DATA_LLCTRL_TYPE_PING_REQ = 0x12, 596 PDU_DATA_LLCTRL_TYPE_PING_RSP = 0x13, 597 PDU_DATA_LLCTRL_TYPE_LENGTH_REQ = 0x14, 598 PDU_DATA_LLCTRL_TYPE_LENGTH_RSP = 0x15, 599 PDU_DATA_LLCTRL_TYPE_PHY_REQ = 0x16, 600 PDU_DATA_LLCTRL_TYPE_PHY_RSP = 0x17, 601 PDU_DATA_LLCTRL_TYPE_PHY_UPD_IND = 0x18, 602 PDU_DATA_LLCTRL_TYPE_MIN_USED_CHAN_IND = 0x19, 603 PDU_DATA_LLCTRL_TYPE_CTE_REQ = 0x1A, 604 PDU_DATA_LLCTRL_TYPE_CTE_RSP = 0x1B, 605 PDU_DATA_LLCTRL_TYPE_CLOCK_ACCURACY_REQ = 0x1D, 606 PDU_DATA_LLCTRL_TYPE_CLOCK_ACCURACY_RSP = 0x1E, 607 PDU_DATA_LLCTRL_TYPE_CIS_REQ = 0x1F, 608 PDU_DATA_LLCTRL_TYPE_CIS_RSP = 0x20, 609 PDU_DATA_LLCTRL_TYPE_CIS_IND = 0x21, 610 PDU_DATA_LLCTRL_TYPE_CIS_TERMINATE_IND = 0x22, 611 PDU_DATA_LLCTRL_TYPE_UNUSED = 0xFF 612 }; 613 614 struct pdu_data_llctrl_conn_update_ind { 615 uint8_t win_size; 616 uint16_t win_offset; 617 uint16_t interval; 618 uint16_t latency; 619 uint16_t timeout; 620 uint16_t instant; 621 } __packed; 622 623 struct pdu_data_llctrl_chan_map_ind { 624 uint8_t chm[PDU_CHANNEL_MAP_SIZE]; 625 uint16_t instant; 626 } __packed; 627 628 struct pdu_data_llctrl_terminate_ind { 629 uint8_t error_code; 630 } __packed; 631 632 struct pdu_data_llctrl_enc_req { 633 uint8_t rand[8]; 634 uint8_t ediv[2]; 635 uint8_t skdm[8]; 636 uint8_t ivm[4]; 637 } __packed; 638 639 struct pdu_data_llctrl_enc_rsp { 640 uint8_t skds[8]; 641 uint8_t ivs[4]; 642 } __packed; 643 644 struct pdu_data_llctrl_start_enc_req { 645 /* no members */ 646 } __packed; 647 648 struct pdu_data_llctrl_start_enc_rsp { 649 /* no members */ 650 } __packed; 651 652 struct pdu_data_llctrl_unknown_rsp { 653 uint8_t type; 654 } __packed; 655 656 struct pdu_data_llctrl_feature_req { 657 uint8_t features[8]; 658 } __packed; 659 660 struct pdu_data_llctrl_feature_rsp { 661 uint8_t features[8]; 662 } __packed; 663 664 struct pdu_data_llctrl_pause_enc_req { 665 /* no members */ 666 } __packed; 667 668 struct pdu_data_llctrl_pause_enc_rsp { 669 /* no members */ 670 } __packed; 671 672 struct pdu_data_llctrl_version_ind { 673 uint8_t version_number; 674 uint16_t company_id; 675 uint16_t sub_version_number; 676 } __packed; 677 678 struct pdu_data_llctrl_reject_ind { 679 uint8_t error_code; 680 } __packed; 681 682 struct pdu_data_llctrl_per_init_feat_xchg { 683 uint8_t features[8]; 684 } __packed; 685 686 struct pdu_data_llctrl_conn_param_req { 687 uint16_t interval_min; 688 uint16_t interval_max; 689 uint16_t latency; 690 uint16_t timeout; 691 uint8_t preferred_periodicity; 692 uint16_t reference_conn_event_count; 693 uint16_t offset0; 694 uint16_t offset1; 695 uint16_t offset2; 696 uint16_t offset3; 697 uint16_t offset4; 698 uint16_t offset5; 699 } __packed; 700 701 struct pdu_data_llctrl_conn_param_rsp { 702 uint16_t interval_min; 703 uint16_t interval_max; 704 uint16_t latency; 705 uint16_t timeout; 706 uint8_t preferred_periodicity; 707 uint16_t reference_conn_event_count; 708 uint16_t offset0; 709 uint16_t offset1; 710 uint16_t offset2; 711 uint16_t offset3; 712 uint16_t offset4; 713 uint16_t offset5; 714 } __packed; 715 716 /* 717 * According to Spec Core v5.3, section 2.4.2.17 718 * LL_CONNECTION_PARAM_RSP and LL_CONNECTION_PARAM_REQ are identical 719 * This is utilized in pdu encode/decode, and for this is needed a common struct 720 */ 721 struct pdu_data_llctrl_conn_param_req_rsp_common { 722 uint16_t interval_min; 723 uint16_t interval_max; 724 uint16_t latency; 725 uint16_t timeout; 726 uint8_t preferred_periodicity; 727 uint16_t reference_conn_event_count; 728 uint16_t offset0; 729 uint16_t offset1; 730 uint16_t offset2; 731 uint16_t offset3; 732 uint16_t offset4; 733 uint16_t offset5; 734 } __packed; 735 736 struct pdu_data_llctrl_reject_ext_ind { 737 uint8_t reject_opcode; 738 uint8_t error_code; 739 } __packed; 740 741 struct pdu_data_llctrl_ping_req { 742 /* no members */ 743 } __packed; 744 745 struct pdu_data_llctrl_ping_rsp { 746 /* no members */ 747 } __packed; 748 749 struct pdu_data_llctrl_length_req { 750 uint16_t max_rx_octets; 751 uint16_t max_rx_time; 752 uint16_t max_tx_octets; 753 uint16_t max_tx_time; 754 } __packed; 755 756 struct pdu_data_llctrl_length_rsp { 757 uint16_t max_rx_octets; 758 uint16_t max_rx_time; 759 uint16_t max_tx_octets; 760 uint16_t max_tx_time; 761 } __packed; 762 763 /* 764 * According to Spec Core v5.3, section 2.4.2.21 765 * LL_LENGTH_REQ and LL_LENGTH_RSP are identical 766 * This is utilized in pdu encode/decode, and for this is needed a common struct 767 */ 768 struct pdu_data_llctrl_length_req_rsp_common { 769 uint16_t max_rx_octets; 770 uint16_t max_rx_time; 771 uint16_t max_tx_octets; 772 uint16_t max_tx_time; 773 } __packed; 774 775 struct pdu_data_llctrl_phy_req { 776 uint8_t tx_phys; 777 uint8_t rx_phys; 778 } __packed; 779 780 struct pdu_data_llctrl_phy_rsp { 781 uint8_t tx_phys; 782 uint8_t rx_phys; 783 } __packed; 784 785 struct pdu_data_llctrl_phy_upd_ind { 786 uint8_t c_to_p_phy; 787 uint8_t p_to_c_phy; 788 uint16_t instant; 789 } __packed; 790 791 struct pdu_data_llctrl_min_used_chans_ind { 792 uint8_t phys; 793 uint8_t min_used_chans; 794 } __packed; 795 796 struct pdu_data_llctrl_cte_req { 797 #ifdef CONFIG_LITTLE_ENDIAN 798 uint8_t min_cte_len_req : 5; 799 uint8_t rfu : 1; 800 uint8_t cte_type_req : 2; 801 #else 802 uint8_t cte_type_req : 2; 803 uint8_t rfu : 1; 804 uint8_t min_cte_len_req : 5; 805 #endif /* CONFIG_LITTLE_ENDIAN */ 806 } __packed; 807 808 struct pdu_data_llctrl_cte_rsp { 809 /* no members */ 810 } __packed; 811 812 struct pdu_data_llctrl_clock_accuracy_req { 813 uint8_t sca; 814 } __packed; 815 816 struct pdu_data_llctrl_clock_accuracy_rsp { 817 uint8_t sca; 818 } __packed; 819 820 struct pdu_data_llctrl_cis_req { 821 uint8_t cig_id; 822 uint8_t cis_id; 823 uint8_t c_phy; 824 uint8_t p_phy; 825 /* c_max_sdu:12 826 * rfu:3 827 * framed:1 828 * NOTE: This layout as bitfields is not portable for BE using 829 * endianness conversion macros. 830 */ 831 uint8_t c_max_sdu_packed[2]; 832 /* p_max_sdu:12 833 * rfu:4 834 * NOTE: This layout as bitfields is not portable for BE using 835 * endianness conversion macros. 836 */ 837 uint8_t p_max_sdu[2]; 838 uint8_t c_sdu_interval[3]; 839 uint8_t p_sdu_interval[3]; 840 uint16_t c_max_pdu; 841 uint16_t p_max_pdu; 842 uint8_t nse; 843 uint8_t sub_interval[3]; 844 #ifdef CONFIG_LITTLE_ENDIAN 845 uint8_t c_bn:4; 846 uint8_t p_bn:4; 847 #else 848 uint8_t p_bn:4; 849 uint8_t c_bn:4; 850 #endif /* CONFIG_LITTLE_ENDIAN */ 851 uint8_t c_ft; 852 uint8_t p_ft; 853 uint16_t iso_interval; 854 uint8_t cis_offset_min[3]; 855 uint8_t cis_offset_max[3]; 856 uint16_t conn_event_count; 857 } __packed; 858 859 struct pdu_data_llctrl_cis_rsp { 860 uint8_t cis_offset_min[3]; 861 uint8_t cis_offset_max[3]; 862 uint16_t conn_event_count; 863 } __packed; 864 865 struct pdu_data_llctrl_cis_ind { 866 uint8_t aa[4]; 867 uint8_t cis_offset[3]; 868 uint8_t cig_sync_delay[3]; 869 uint8_t cis_sync_delay[3]; 870 uint16_t conn_event_count; 871 } __packed; 872 873 struct pdu_data_llctrl_cis_terminate_ind { 874 uint8_t cig_id; 875 uint8_t cis_id; 876 uint8_t error_code; 877 } __packed; 878 879 struct pdu_data_llctrl { 880 uint8_t opcode; 881 union { 882 struct pdu_data_llctrl_conn_update_ind conn_update_ind; 883 struct pdu_data_llctrl_chan_map_ind chan_map_ind; 884 struct pdu_data_llctrl_terminate_ind terminate_ind; 885 struct pdu_data_llctrl_enc_req enc_req; 886 struct pdu_data_llctrl_enc_rsp enc_rsp; 887 struct pdu_data_llctrl_start_enc_req start_enc_req; 888 struct pdu_data_llctrl_start_enc_rsp start_enc_rsp; 889 struct pdu_data_llctrl_unknown_rsp unknown_rsp; 890 struct pdu_data_llctrl_feature_req feature_req; 891 struct pdu_data_llctrl_feature_rsp feature_rsp; 892 struct pdu_data_llctrl_pause_enc_req pause_enc_req; 893 struct pdu_data_llctrl_pause_enc_rsp pause_enc_rsp; 894 struct pdu_data_llctrl_version_ind version_ind; 895 struct pdu_data_llctrl_reject_ind reject_ind; 896 struct pdu_data_llctrl_per_init_feat_xchg per_init_feat_xchg; 897 struct pdu_data_llctrl_conn_param_req conn_param_req; 898 struct pdu_data_llctrl_conn_param_rsp conn_param_rsp; 899 struct pdu_data_llctrl_reject_ext_ind reject_ext_ind; 900 struct pdu_data_llctrl_ping_req ping_req; 901 struct pdu_data_llctrl_ping_rsp ping_rsp; 902 struct pdu_data_llctrl_length_req length_req; 903 struct pdu_data_llctrl_length_rsp length_rsp; 904 struct pdu_data_llctrl_phy_req phy_req; 905 struct pdu_data_llctrl_phy_rsp phy_rsp; 906 struct pdu_data_llctrl_phy_upd_ind phy_upd_ind; 907 struct pdu_data_llctrl_min_used_chans_ind min_used_chans_ind; 908 struct pdu_data_llctrl_cte_req cte_req; 909 struct pdu_data_llctrl_cte_rsp cte_rsp; 910 struct pdu_data_llctrl_clock_accuracy_req clock_accuracy_req; 911 struct pdu_data_llctrl_clock_accuracy_rsp clock_accuracy_rsp; 912 struct pdu_data_llctrl_cis_req cis_req; 913 struct pdu_data_llctrl_cis_rsp cis_rsp; 914 struct pdu_data_llctrl_cis_ind cis_ind; 915 struct pdu_data_llctrl_cis_terminate_ind cis_terminate_ind; 916 } __packed; 917 } __packed; 918 919 #define PDU_DATA_LLCTRL_LEN(type) (offsetof(struct pdu_data_llctrl, type) + \ 920 sizeof(struct pdu_data_llctrl_ ## type)) 921 922 #if defined(CONFIG_BT_CTLR_PROFILE_ISR) 923 struct profile { 924 uint8_t lcur; 925 uint8_t lmin; 926 uint8_t lmax; 927 uint8_t cur; 928 uint8_t min; 929 uint8_t max; 930 uint8_t radio; 931 uint8_t lll; 932 uint8_t ull_high; 933 uint8_t ull_low; 934 } __packed; 935 #endif /* CONFIG_BT_CTLR_PROFILE_ISR */ 936 937 struct pdu_data { 938 #ifdef CONFIG_LITTLE_ENDIAN 939 uint8_t ll_id:2; 940 uint8_t nesn:1; 941 uint8_t sn:1; 942 uint8_t md:1; 943 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_TX) || defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX) 944 uint8_t cp:1; 945 uint8_t rfu:2; 946 #else 947 uint8_t rfu:3; 948 #endif 949 #else 950 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_TX) || defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX) 951 uint8_t rfu:2; 952 uint8_t cp:1; 953 #else 954 uint8_t rfu:3; 955 #endif 956 uint8_t md:1; 957 uint8_t sn:1; 958 uint8_t nesn:1; 959 uint8_t ll_id:2; 960 #endif /* CONFIG_LITTLE_ENDIAN */ 961 962 uint8_t len; 963 964 struct pdu_data_vnd_octet3 octet3; 965 966 union { 967 struct pdu_data_llctrl llctrl; 968 uint8_t lldata[0]; 969 970 #if defined(CONFIG_BT_CTLR_CONN_RSSI) 971 uint8_t rssi; 972 #endif /* CONFIG_BT_CTLR_CONN_RSSI */ 973 974 #if defined(CONFIG_BT_CTLR_PROFILE_ISR) 975 struct profile profile; 976 #endif /* CONFIG_BT_CTLR_PROFILE_ISR */ 977 } __packed; 978 } __packed; 979 980 /* Generic ISO pdu, could be CIS or BIS 981 * To be used when referring to component without knowing CIS or BIS type 982 */ 983 struct pdu_iso { 984 #ifdef CONFIG_LITTLE_ENDIAN 985 uint8_t ll_id:2; 986 uint8_t hdr_other:6; 987 #else 988 uint8_t hdr_other:6; 989 uint8_t ll_id:2; 990 #endif /* CONFIG_LITTLE_ENDIAN */ 991 992 uint8_t len; 993 994 struct pdu_iso_vnd_octet3 octet3; 995 996 uint8_t payload[0]; 997 } __packed; 998 999 /* ISO SDU segmentation header */ 1000 #define PDU_ISO_SEG_HDR_SIZE 2 1001 #define PDU_ISO_SEG_TIMEOFFSET_SIZE 3 1002 1003 struct pdu_iso_sdu_sh { 1004 #ifdef CONFIG_LITTLE_ENDIAN 1005 uint8_t sc:1; 1006 uint8_t cmplt:1; 1007 uint8_t rfu:6; 1008 1009 uint8_t len; 1010 /* Note, timeoffset only available in first segment of sdu */ 1011 uint32_t timeoffset:24; 1012 uint32_t payload:8; 1013 #else 1014 uint8_t rfu:6; 1015 uint8_t cmplt:1; 1016 uint8_t sc:1; 1017 1018 uint8_t len; 1019 1020 /* Note, timeoffset only available in first segment of sdu */ 1021 uint32_t timeoffset:24; 1022 uint32_t payload:8; 1023 #endif /* CONFIG_LITTLE_ENDIAN */ 1024 } __packed; 1025 1026 enum pdu_cis_llid { 1027 /** Unframed complete or end fragment */ 1028 PDU_CIS_LLID_COMPLETE_END = 0x00, 1029 /** Unframed start or continuation fragment */ 1030 PDU_CIS_LLID_START_CONTINUE = 0x01, 1031 /** Framed; one or more segments of a SDU */ 1032 PDU_CIS_LLID_FRAMED = 0x02 1033 }; 1034 1035 struct pdu_cis { 1036 #ifdef CONFIG_LITTLE_ENDIAN 1037 uint8_t ll_id:2; 1038 uint8_t nesn:1; 1039 uint8_t sn:1; 1040 uint8_t cie:1; 1041 uint8_t rfu0:1; 1042 uint8_t npi:1; 1043 uint8_t rfu1:1; 1044 #else 1045 uint8_t rfu1:1; 1046 uint8_t npi:1; 1047 uint8_t rfu0:1; 1048 uint8_t cie:1; 1049 uint8_t sn:1; 1050 uint8_t nesn:1; 1051 uint8_t ll_id:2; 1052 #endif /* CONFIG_LITTLE_ENDIAN */ 1053 1054 uint8_t len; 1055 1056 struct pdu_cis_vnd_octet3 octet3; 1057 1058 uint8_t payload[0]; 1059 } __packed; 1060 1061 enum pdu_big_ctrl_type { 1062 PDU_BIG_CTRL_TYPE_CHAN_MAP_IND = 0x00, 1063 PDU_BIG_CTRL_TYPE_TERM_IND = 0x01, 1064 }; 1065 1066 struct pdu_big_ctrl_chan_map_ind { 1067 uint8_t chm[PDU_CHANNEL_MAP_SIZE]; 1068 uint16_t instant; 1069 } __packed; 1070 1071 struct pdu_big_ctrl_term_ind { 1072 uint8_t reason; 1073 uint16_t instant; 1074 } __packed; 1075 1076 1077 struct pdu_big_ctrl { 1078 uint8_t opcode; 1079 union { 1080 uint8_t ctrl_data[0]; 1081 struct pdu_big_ctrl_chan_map_ind chan_map_ind; 1082 struct pdu_big_ctrl_term_ind term_ind; 1083 } __packed; 1084 } __packed; 1085 1086 enum pdu_bis_llid { 1087 /** Unframed complete or end fragment */ 1088 PDU_BIS_LLID_COMPLETE_END = 0x00, 1089 /** Unframed start or continuation fragment */ 1090 PDU_BIS_LLID_START_CONTINUE = 0x01, 1091 /** Framed; one or more segments of a SDU */ 1092 PDU_BIS_LLID_FRAMED = 0x02, 1093 /** BIG Control PDU */ 1094 PDU_BIS_LLID_CTRL = 0x03, 1095 }; 1096 1097 struct pdu_bis { 1098 #ifdef CONFIG_LITTLE_ENDIAN 1099 uint8_t ll_id:2; 1100 uint8_t cssn:3; 1101 uint8_t cstf:1; 1102 uint8_t rfu:2; 1103 #else 1104 uint8_t rfu:2; 1105 uint8_t cstf:1; 1106 uint8_t cssn:3; 1107 uint8_t ll_id:2; 1108 #endif /* CONFIG_LITTLE_ENDIAN */ 1109 1110 uint8_t len; 1111 1112 struct pdu_bis_vnd_octet3 octet3; 1113 1114 union { 1115 uint8_t payload[0]; 1116 struct pdu_big_ctrl ctrl; 1117 } __packed; 1118 } __packed; 1119 1120 struct pdu_big_info { 1121 #ifdef CONFIG_LITTLE_ENDIAN 1122 uint32_t offs:14; 1123 uint32_t offs_units:1; 1124 uint32_t iso_interval:12; 1125 uint32_t num_bis:5; 1126 1127 uint32_t nse:5; 1128 uint32_t bn:3; 1129 uint32_t sub_interval:20; 1130 uint32_t pto:4; 1131 1132 uint32_t spacing:20; 1133 uint32_t irc:4; 1134 uint32_t max_pdu:8; 1135 1136 uint8_t rfu; 1137 1138 uint32_t seed_access_addr; 1139 1140 uint32_t sdu_interval:20; 1141 uint32_t max_sdu:12; 1142 #else 1143 uint32_t num_bis:5; 1144 uint32_t iso_interval:12; 1145 uint32_t offs_units:1; 1146 uint32_t offs:14; 1147 1148 uint32_t pto:4; 1149 uint32_t sub_interval:20; 1150 uint32_t bn:3; 1151 uint32_t nse:5; 1152 1153 uint32_t max_pdu:8; 1154 uint32_t irc:4; 1155 uint32_t spacing:20; 1156 1157 uint8_t rfu; 1158 1159 uint32_t seed_access_addr; 1160 1161 uint32_t max_sdu:12; 1162 uint32_t sdu_interval:20; 1163 #endif /* CONFIG_LITTLE_ENDIAN */ 1164 1165 uint16_t base_crc_init; 1166 1167 uint8_t chm_phy[PDU_CHANNEL_MAP_SIZE]; /* 37 bit chm; 3 bit phy */ 1168 uint8_t payload_count_framing[5]; /* 39 bit count; 1 bit framing */ 1169 1170 uint8_t giv[8]; /* encryption required */ 1171 uint8_t gskd[16]; /* encryption required */ 1172 } __packed; 1173 #define PDU_BIG_INFO_CLEARTEXT_SIZE offsetof(struct pdu_big_info, giv) 1174 #define PDU_BIG_INFO_ENCRYPTED_SIZE sizeof(struct pdu_big_info) 1175 #define PDU_BIG_BN_MAX 0x07 1176 #define PDU_BIG_PAYLOAD_COUNT_MAX 28 1177 1178 struct pdu_dtm { 1179 #ifdef CONFIG_LITTLE_ENDIAN 1180 uint8_t type:4; 1181 uint8_t rfu0:1; 1182 #if defined(CONFIG_BT_CTLR_DF_CTE_TX) 1183 uint8_t cp:1; 1184 uint8_t rfu1:2; 1185 #else 1186 uint8_t rfu1:3; 1187 #endif 1188 #else 1189 #if defined(CONFIG_BT_CTLR_DF_CTE_TX) 1190 uint8_t rfu1:2; 1191 uint8_t cp:1; 1192 #else 1193 uint8_t rfu1:3; 1194 #endif 1195 uint8_t rfu0:1; 1196 uint8_t type:4; 1197 #endif /* CONFIG_LITTLE_ENDIAN */ 1198 1199 uint8_t len; 1200 1201 struct pdu_data_vnd_octet3 octet3; 1202 1203 uint8_t payload[0]; 1204 } __packed; 1205 1206 /* Direct Test Mode maximum payload size */ 1207 #define PDU_DTM_PAYLOAD_SIZE_MAX 255 1208
