1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _SOC_MCHP_PCR_H_ 8 #define _SOC_MCHP_PCR_H_ 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /* slp_idx = [0, 4], bitpos = [0, 31] refer above */ 15 #define MCHP_XEC_PCR_SCR_ENCODE(slp_idx, bitpos, domain) \ 16 ((((uint32_t)(domain) & 0xff) << 24) | (((bitpos) & 0x1f) << 3) \ 17 | ((uint32_t)(slp_idx) & 0x7)) 18 19 #define MCHP_XEC_PCR_SCR_GET_IDX(e) ((e) & 0x7u) 20 #define MCHP_XEC_PCR_SCR_GET_BITPOS(e) (((e) & 0xf8u) >> 3) 21 22 /* cpu clock divider */ 23 #define MCHP_XEC_CLK_CPU_MASK GENMASK(7, 0) 24 #define MCHP_XEC_CLK_CPU_CLK_DIV_1 1u 25 #define MCHP_XEC_CLK_CPU_CLK_DIV_2 2u 26 #define MCHP_XEC_CLK_CPU_CLK_DIV_4 4u 27 #define MCHP_XEC_CLK_CPU_CLK_DIV_8 8u 28 #define MCHP_XEC_CLK_CPU_CLK_DIV_16 16u 29 #define MCHP_XEC_CLK_CPU_CLK_DIV_48 48u 30 31 /* slow clock divider */ 32 #define MCHP_XEC_CLK_SLOW_MASK GENMASK(8, 0) 33 #define MCHP_XEC_CLK_SLOW_CLK_DIV_100K 480u 34 35 #define MCHP_XEC_CLK_SRC_POS 24 36 #define MCHP_XEC_CLK_SRC_MASK GENMASK(31, 24) 37 38 #define MCHP_XEC_CLK_SRC_GET(n) \ 39 (((n) & MCHP_XEC_CLK_SRC_MASK) >> MCHP_XEC_CLK_SRC_POS) 40 41 #define MCHP_XEC_CLK_SRC_SET(v, c) (((v) & ~MCHP_XEC_CLK_SRC_MASK) |\ 42 (((c) << MCHP_XEC_CLK_SRC_POS) & MCHP_XEC_CLK_SRC_MASK)) 43 44 /* 45 * b[31:24] = clock source 46 * b[23:0] = clock source specific format 47 */ 48 struct mchp_xec_pcr_clk_ctrl { 49 uint32_t pcr_info; 50 }; 51 52 #ifdef __cplusplus 53 } 54 #endif 55 56 #endif /* _SOC_MCHP_PCR_H_ */ 57
