1 /* 2 * Copyright 2020 Broadcom 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef DMA_IPROC_PAX_V2 8 #define DMA_IPROC_PAX_V2 9 10 #include "dma_iproc_pax.h" 11 12 #define RING_COMPLETION_INTERRUPT_STAT_MASK 0x088 13 #define RING_COMPLETION_INTERRUPT_STAT_CLEAR 0x08c 14 #define RING_COMPLETION_INTERRUPT_STAT 0x090 15 #define RING_DISABLE_MSI_TIMEOUT 0x0a4 16 17 /* Register RM_COMM_CONTROL fields */ 18 #define RM_COMM_CONTROL_MODE_MASK 0x3 19 #define RM_COMM_CONTROL_MODE_SHIFT 0 20 #define RM_COMM_CONTROL_MODE_DOORBELL 0x0 21 #define RM_COMM_CONTROL_MODE_TOGGLE 0x2 22 #define RM_COMM_CONTROL_MODE_ALL_BD_TOGGLE 0x3 23 #define RM_COMM_CONTROL_CONFIG_DONE BIT(2) 24 #define RM_COMM_CONTROL_LINE_INTR_EN BIT(4) 25 #define RM_COMM_CONTROL_AE_TIMEOUT_EN BIT(5) 26 27 #define RING_DISABLE_MSI_TIMEOUT_VALUE 1 28 29 #define PAX_DMA_TYPE_SRC_DESC 0x2 30 #define PAX_DMA_TYPE_DST_DESC 0x3 31 #define PAX_DMA_TYPE_MEGA_SRC_DESC 0x6 32 #define PAX_DMA_TYPE_MEGA_DST_DESC 0x7 33 #define PAX_DMA_TYPE_PCIE_DESC 0xB 34 #define PAX_DMA_NUM_BD_BUFFS 9 35 /* PCIE DESC, either DST or SRC DESC */ 36 #define PAX_DMA_RM_DESC_BDCOUNT 2 37 38 /* ascii signature 'V' 'P' */ 39 #define PAX_DMA_WRITE_SYNC_SIGNATURE 0x5650 40 41 #define PAX_DMA_PCI_ADDR_MSB8_SHIFT 56 42 #define PAX_DMA_PCI_ADDR_HI_MSB8(pci) ((pci) >> PAX_DMA_PCI_ADDR_MSB8_SHIFT) 43 44 #define PAX_DMA_MAX_SZ_PER_BD (512 * 1024) 45 #define PAX_DMA_MEGA_LENGTH_MULTIPLE 16 46 47 /* Maximum DMA block count supported per request */ 48 #define RM_V2_MAX_BLOCK_COUNT 1024 49 #define MAX_BD_COUNT_PER_HEADER 30 50 51 /* 52 * Sync payload buffer size is of 4 bytes,4096 Bytes allocated here 53 * to make sure BD memories fall in 4K alignment. 54 */ 55 #define PAX_DMA_RM_SYNC_BUFFER_MISC_SIZE 4096 56 57 /* 58 * Per-ring memory, with 8K & 4K alignment 59 * Alignment may not be ensured by allocator 60 * s/w need to allocate extra upto 8K to 61 * ensure aligned memory space. 62 */ 63 #define PAX_DMA_PER_RING_ALLOC_SIZE (PAX_DMA_RM_CMPL_RING_SIZE * 2 + \ 64 PAX_DMA_NUM_BD_BUFFS * \ 65 PAX_DMA_RM_DESC_RING_SIZE + \ 66 PAX_DMA_RM_SYNC_BUFFER_MISC_SIZE) 67 68 /* RM header desc field */ 69 struct rm_header { 70 uint64_t opq : 16; /*pkt_id 15:0*/ 71 uint64_t bdf : 16; /*reserved 31:16*/ 72 uint64_t res1 : 4; /*res 32:35*/ 73 uint64_t bdcount : 5; /*bdcount 36:40*/ 74 uint64_t prot : 2; /*prot 41:42*/ 75 uint64_t res2 : 1; /*res :43:43*/ 76 uint64_t pcie_addr_msb : 8; /*pcie addr :44:51*/ 77 uint64_t res3 : 4; /*res :52:55*/ 78 uint64_t start : 1; /*S :56*/ 79 uint64_t end : 1; /*E:57*/ 80 uint64_t res4 : 1; /*res:58*/ 81 uint64_t toggle : 1; /*T:59*/ 82 uint64_t type : 4; /*type:60:63*/ 83 } __attribute__ ((__packed__)); 84 85 /* pcie desc field */ 86 struct pcie_desc { 87 uint64_t pcie_addr_lsb : 56; /* pcie_addr_lsb 0:55*/ 88 uint64_t res1: 3; /*reserved 56:58*/ 89 uint64_t toggle : 1; /*T:59*/ 90 uint64_t type : 4; /*type:60:63*/ 91 } __attribute__ ((__packed__)); 92 93 /* src/dst desc field */ 94 struct src_dst_desc { 95 uint64_t axi_addr : 44; /*axi_addr[43:0]*/ 96 uint64_t length : 15; /*length[44:58]*/ 97 uint64_t toggle : 1; /*T:59*/ 98 uint64_t type : 4; /*type:60:63*/ 99 } __attribute__ ((__packed__)); 100 101 struct next_ptr_desc { 102 uint64_t addr : 44; /*Address 43:0*/ 103 uint64_t res1 : 15;/*Reserved*/ 104 uint64_t toggle : 1; /*Toggle Bit:59*/ 105 uint64_t type : 4;/*descriptor type 63:60*/ 106 } __attribute__ ((__packed__)); 107 108 #endif 109
