1 /*
2  * Copyright (c) 2018-2019 Nordic Semiconductor ASA
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #if defined(CONFIG_BT_CTLR_CONN_META)
7 #include "lll_conn_meta.h"
8 #endif /* CONFIG_BT_CTLR_CONN_META */
9 
10 #define LLL_CONN_RSSI_SAMPLE_COUNT 10
11 #define LLL_CONN_RSSI_THRESHOLD    4
12 
13 #define LLL_CONN_MIC_NONE 0
14 #define LLL_CONN_MIC_PASS 1
15 #define LLL_CONN_MIC_FAIL 2
16 
17 struct lll_tx {
18 	uint16_t handle;
19 	void *node;
20 };
21 
22 struct node_tx {
23 	union {
24 		void        *next;
25 		memq_link_t *link;
26 	};
27 
28 	uint8_t pdu[];
29 };
30 
31 struct lll_conn {
32 	struct lll_hdr hdr;
33 
34 	uint8_t access_addr[4];
35 	uint8_t crc_init[3];
36 
37 	uint16_t handle;
38 	uint16_t interval;
39 	uint16_t latency;
40 
41 	uint16_t latency_prepare;
42 	uint16_t latency_event;
43 	uint16_t event_counter;
44 
45 	uint8_t data_chan_map[PDU_CHANNEL_MAP_SIZE];
46 	uint8_t data_chan_count:6;
47 	uint8_t data_chan_sel:1;
48 	uint8_t role:1;
49 
50 	union {
51 		struct {
52 			uint8_t data_chan_hop;
53 			uint8_t data_chan_use;
54 		};
55 
56 		uint16_t data_chan_id;
57 	};
58 
59 	union {
60 		struct {
61 			uint8_t initiated:1;
62 			uint8_t cancelled:1;
63 		} central;
64 #if defined(CONFIG_BT_PERIPHERAL)
65 		struct {
66 			uint8_t  initiated:1;
67 			uint8_t  cancelled:1;
68 			uint8_t  latency_enabled:1;
69 
70 			uint32_t window_widening_periodic_us;
71 			uint32_t window_widening_max_us;
72 			uint32_t window_widening_prepare_us;
73 			uint32_t window_widening_event_us;
74 			uint32_t window_size_prepare_us;
75 			uint32_t window_size_event_us;
76 		} periph;
77 #endif /* CONFIG_BT_PERIPHERAL */
78 	};
79 
80 #if defined(CONFIG_BT_CTLR_DATA_LENGTH)
81 	uint16_t max_tx_octets;
82 	uint16_t max_rx_octets;
83 
84 #if defined(CONFIG_BT_CTLR_PHY)
85 	uint16_t max_tx_time;
86 	uint16_t max_rx_time;
87 #endif /* CONFIG_BT_CTLR_PHY */
88 #endif /* CONFIG_BT_CTLR_DATA_LENGTH */
89 
90 #if defined(CONFIG_BT_CTLR_PHY)
91 	uint8_t phy_tx:3;
92 	uint8_t phy_flags:1;
93 	uint8_t phy_tx_time:3;
94 	uint8_t phy_rx:3;
95 #endif /* CONFIG_BT_CTLR_PHY */
96 
97 	MEMQ_DECLARE(tx);
98 	memq_link_t link_tx;
99 	memq_link_t *link_tx_free;
100 	uint8_t  packet_tx_head_len;
101 	uint8_t  packet_tx_head_offset;
102 
103 	uint8_t sn:1;
104 	uint8_t nesn:1;
105 	uint8_t empty:1;
106 
107 #if defined(CONFIG_BT_CTLR_LE_ENC)
108 	uint8_t enc_rx:1;
109 	uint8_t enc_tx:1;
110 
111 	struct ccm ccm_rx;
112 	struct ccm ccm_tx;
113 #endif /* CONFIG_BT_CTLR_LE_ENC */
114 
115 #if defined(CONFIG_BT_CTLR_CONN_RSSI)
116 	uint8_t  rssi_latest;
117 #if defined(CONFIG_BT_CTLR_CONN_RSSI_EVENT)
118 	uint8_t  rssi_reported;
119 	uint8_t  rssi_sample_count;
120 #endif /* CONFIG_BT_CTLR_CONN_RSSI_EVENT */
121 #endif /* CONFIG_BT_CTLR_CONN_RSSI */
122 
123 #if defined(CONFIG_BT_CTLR_CONN_META)
124 	struct lll_conn_meta conn_meta;
125 #endif /* CONFIG_BT_CTLR_CONN_META */
126 
127 #if defined(CONFIG_BT_CTLR_TX_PWR_DYNAMIC_CONTROL)
128 	int8_t tx_pwr_lvl;
129 #endif
130 
131 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_REQ)
132 	struct lll_df_conn_rx_params df_rx_params;
133 #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_REQ */
134 };
135 
136 int lll_conn_init(void);
137 int lll_conn_reset(void);
138 void lll_conn_flush(uint16_t handle, struct lll_conn *lll);
139 
140 void lll_conn_prepare_reset(void);
141 void lll_conn_abort_cb(struct lll_prepare_param *prepare_param, void *param);
142 void lll_conn_isr_rx(void *param);
143 void lll_conn_isr_tx(void *param);
144 void lll_conn_rx_pkt_set(struct lll_conn *lll);
145 void lll_conn_tx_pkt_set(struct lll_conn *lll, struct pdu_data *pdu_data_tx);
146 void lll_conn_pdu_tx_prep(struct lll_conn *lll, struct pdu_data **pdu_data_tx);
147 uint8_t lll_conn_force_md_cnt_set(uint8_t force_md_cnt);
148 
149 extern void ull_conn_lll_ack_enqueue(uint16_t handle, struct node_tx *tx);
150 extern uint16_t ull_conn_lll_max_tx_octets_get(struct lll_conn *lll);
151