1 /*
2 * Copyright (c) 2024-2025 Renesas Electronics Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT renesas_rz_gpio
8
9 #include <zephyr/device.h>
10 #include <zephyr/devicetree.h>
11 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/irq.h>
13 #include "r_ioport.h"
14 #include <zephyr/kernel.h>
15 #include <zephyr/drivers/gpio/gpio_utils.h>
16 #include "gpio_renesas_rz.h"
17 #include <zephyr/logging/log.h>
18 #if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
19 #include "r_icu.h"
20 #include <zephyr/drivers/interrupt_controller/intc_rz_ext_irq.h>
21 #endif
22 LOG_MODULE_REGISTER(rz_gpio, CONFIG_GPIO_LOG_LEVEL);
23
24 #define LOG_DEV_ERR(dev, format, ...) LOG_ERR("%s:" #format, (dev)->name, ##__VA_ARGS__)
25 #define LOG_DEV_DBG(dev, format, ...) LOG_DBG("%s:" #format, (dev)->name, ##__VA_ARGS__)
26
27 struct gpio_rz_config {
28 struct gpio_driver_config common;
29 uint8_t ngpios;
30 uint8_t port_num;
31 bsp_io_port_t fsp_port;
32 const ioport_cfg_t *fsp_cfg;
33 const ioport_api_t *fsp_api;
34 const struct device *int_dev;
35 uint8_t int_num[GPIO_RZ_MAX_INT_NUM];
36 #if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
37 const struct device *eirq_dev[GPIO_RZ_MAX_INT_NUM];
38
39 void (*cb_list[GPIO_RZ_MAX_INT_NUM])(void *arg);
40 #endif
41 };
42
43 struct gpio_rz_data {
44 struct gpio_driver_data common;
45 sys_slist_t cb;
46 ioport_instance_ctrl_t *fsp_ctrl;
47 struct k_spinlock lock;
48 #if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
49 uint8_t pin[GPIO_RZ_MAX_INT_NUM];
50 #endif
51 };
52
53 struct gpio_rz_isr_data {
54 const struct device *gpio_dev;
55 gpio_pin_t pin;
56 };
57
58 struct gpio_rz_int_data {
59 struct gpio_rz_isr_data gpio_mapping[GPIO_RZ_MAX_INT_NUM];
60 uint32_t irq_set_edge;
61 };
62
63 struct gpio_rz_hw_config {
64 gpio_flags_t p_pm;
65 uint8_t pfc;
66 };
67
68 struct gpio_rz_tint_config {
69 void (*gpio_int_init)(void);
70 };
71
72 static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, struct gpio_rz_hw_config *flags);
73
74 #ifdef CONFIG_GPIO_GET_CONFIG
gpio_rz_pin_get_config(const struct device * dev,gpio_pin_t pin,gpio_flags_t * flags)75 static int gpio_rz_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags)
76 {
77 const struct gpio_rz_config *config = dev->config;
78 bsp_io_port_pin_t port_pin = config->fsp_port | pin;
79 struct gpio_rz_hw_config hw_flags;
80
81 gpio_rz_pin_config_get_raw(port_pin, &hw_flags);
82 *flags = hw_flags.p_pm;
83
84 return 0;
85 }
86 #endif
87
88 /* Get previous pin's configuration, used by pin_configure/pin_interrupt_configure api */
gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin,struct gpio_rz_hw_config * flags)89 static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, struct gpio_rz_hw_config *flags)
90 {
91 bsp_io_port_t port = (port_pin >> 8U) & 0xFF;
92 gpio_pin_t pin = port_pin & 0xFF;
93 volatile uint8_t *p_p = GPIO_RZ_IOPORT_P_REG_GET(port, pin);
94 volatile uint16_t *p_pm = GPIO_RZ_IOPORT_PM_REG_GET(port, pin);
95 volatile uint32_t *p_pfc = GPIO_RZ_IOPORT_PFC_REG_GET(port, pin);
96
97 uint8_t p_value;
98 uint16_t pm_value;
99 uint32_t pfc_value;
100
101 p_value = GPIO_RZ_P_VALUE_GET(*p_p, pin);
102 pm_value = GPIO_RZ_PM_VALUE_GET(*p_pm, pin);
103 pfc_value = GPIO_RZ_PFC_VALUE_GET(*p_pfc, pin);
104
105 flags->p_pm = 0;
106 flags->pfc = 0;
107
108 if (p_value) {
109 flags->p_pm |= GPIO_OUTPUT_INIT_HIGH;
110 } else {
111 flags->p_pm |= GPIO_OUTPUT_INIT_LOW;
112 }
113
114 flags->p_pm |= (pm_value << 16);
115 flags->pfc |= pfc_value;
116 return 0;
117 }
118
gpio_rz_pin_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)119 static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
120 {
121 const struct gpio_rz_config *config = dev->config;
122 struct gpio_rz_data *data = dev->data;
123 bsp_io_port_pin_t port_pin = config->fsp_port | pin;
124 uint32_t ioport_config_data = 0;
125 struct gpio_rz_hw_config pre_flags;
126 fsp_err_t err;
127
128 gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
129
130 if (!flags) {
131 /* Disconnect mode */
132 GPIO_RZ_PIN_DISCONNECT(config->fsp_port, pin);
133 } else if (!(flags & GPIO_OPEN_DRAIN)) {
134 /* PM register */
135 ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET;
136 if (flags & GPIO_INPUT) {
137 if (flags & GPIO_OUTPUT) {
138 ioport_config_data |= IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT;
139 } else {
140 ioport_config_data |= IOPORT_CFG_PORT_DIRECTION_INPUT;
141 }
142 } else if (flags & GPIO_OUTPUT) {
143 ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET;
144 ioport_config_data |= IOPORT_CFG_PORT_DIRECTION_OUTPUT;
145 }
146 /* P register */
147 if (!(flags & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW))) {
148 flags |= pre_flags.p_pm & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW);
149 }
150
151 if (flags & GPIO_OUTPUT_INIT_HIGH) {
152 ioport_config_data |= IOPORT_CFG_PORT_OUTPUT_HIGH;
153 } else if (flags & GPIO_OUTPUT_INIT_LOW) {
154 ioport_config_data &= ~(IOPORT_CFG_PORT_OUTPUT_HIGH);
155 }
156 /* PUPD register */
157 if (flags & GPIO_PULL_UP) {
158 ioport_config_data |= IOPORT_CFG_PULLUP_ENABLE;
159 } else if (flags & GPIO_PULL_DOWN) {
160 ioport_config_data |= IOPORT_CFG_PULLDOWN_ENABLE;
161 }
162
163 /*
164 * Interrupt register
165 * RZG: ISEL
166 * RZTN: PMC
167 */
168 if (flags & GPIO_INT_ENABLE) {
169 ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_INT_ENABLE;
170 } else if (flags & GPIO_INT_DISABLE) {
171 ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INT_DISABLE;
172 }
173
174 /*
175 * Drive ability register
176 * RZG: IOLH
177 * RZTN: DRCTL
178 */
179 ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_GET(flags);
180
181 /* PFC register */
182 ioport_config_data |= GPIO_RZ_IOPORT_PFC_SET(pre_flags.pfc);
183
184 /*
185 * Specific register
186 * RZG: FILONOFF, FILNUM, FILCLKSEL
187 * RZTN: RSELP
188 */
189 ioport_config_data |= GPIO_RZ_PIN_SPECIAL_FLAG_GET(flags);
190 } else {
191 return -ENOTSUP;
192 }
193
194 err = config->fsp_api->pinCfg(data->fsp_ctrl, port_pin, ioport_config_data);
195 if (err != FSP_SUCCESS) {
196 return -EIO;
197 }
198 return 0;
199 }
200
gpio_rz_port_get_raw(const struct device * dev,gpio_port_value_t * value)201 static int gpio_rz_port_get_raw(const struct device *dev, gpio_port_value_t *value)
202 {
203 const struct gpio_rz_config *config = dev->config;
204 struct gpio_rz_data *data = dev->data;
205 fsp_err_t err;
206 ioport_size_t port_value;
207
208 err = config->fsp_api->portRead(data->fsp_ctrl, config->fsp_port, &port_value);
209 if (err != FSP_SUCCESS) {
210 return -EIO;
211 }
212 *value = (gpio_port_value_t)port_value;
213 return 0;
214 }
215
gpio_rz_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)216 static int gpio_rz_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
217 gpio_port_value_t value)
218 {
219 const struct gpio_rz_config *config = dev->config;
220 struct gpio_rz_data *data = dev->data;
221 ioport_size_t port_mask = (ioport_size_t)mask;
222 ioport_size_t port_value = (ioport_size_t)value;
223 fsp_err_t err;
224
225 err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, port_value, port_mask);
226 if (err != FSP_SUCCESS) {
227 return -EIO;
228 }
229 return 0;
230 }
231
gpio_rz_port_set_bits_raw(const struct device * dev,gpio_port_pins_t pins)232 static int gpio_rz_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
233 {
234 const struct gpio_rz_config *config = dev->config;
235 struct gpio_rz_data *data = dev->data;
236 ioport_size_t mask = (ioport_size_t)pins;
237 ioport_size_t value = (ioport_size_t)pins;
238 fsp_err_t err;
239
240 err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, value, mask);
241 if (err != FSP_SUCCESS) {
242 return -EIO;
243 }
244 return 0;
245 }
246
gpio_rz_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t pins)247 static int gpio_rz_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
248 {
249 const struct gpio_rz_config *config = dev->config;
250 struct gpio_rz_data *data = dev->data;
251 ioport_size_t mask = (ioport_size_t)pins;
252 ioport_size_t value = 0x00;
253 fsp_err_t err;
254
255 err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, value, mask);
256 if (err != FSP_SUCCESS) {
257 return -EIO;
258 }
259 return 0;
260 }
261
gpio_rz_port_toggle_bits(const struct device * dev,gpio_port_pins_t pins)262 static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
263 {
264 const struct gpio_rz_config *config = dev->config;
265 struct gpio_rz_data *data = dev->data;
266 bsp_io_port_pin_t port_pin;
267 struct gpio_rz_hw_config pre_flags;
268 ioport_size_t value = 0;
269 fsp_err_t err;
270
271 for (uint8_t idx = 0; idx < config->ngpios; idx++) {
272 if (pins & (1U << idx)) {
273 port_pin = config->fsp_port | idx;
274 gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
275 if (pre_flags.p_pm & GPIO_OUTPUT_INIT_HIGH) {
276 value &= (1U << idx);
277 } else if (pre_flags.p_pm & GPIO_OUTPUT_INIT_LOW) {
278 value |= (1U << idx);
279 }
280 }
281 }
282 err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, value,
283 (ioport_size_t)pins);
284 if (err != FSP_SUCCESS) {
285 return -EIO;
286 }
287 return 0;
288 }
289
290 #define GPIO_RZ_HAS_INTERRUPT \
291 DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_gpio_int) | \
292 DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_ext_irq)
293
294 #if GPIO_RZ_HAS_INTERRUPT
gpio_rz_int_disable(const struct device * dev,const struct device * gpio_dev,uint8_t int_num,gpio_pin_t pin)295 static int gpio_rz_int_disable(const struct device *dev, const struct device *gpio_dev,
296 uint8_t int_num, gpio_pin_t pin)
297 {
298 #if defined(CONFIG_SOC_SERIES_RZG3S)
299 volatile uint32_t *tssr = &R_INTC_IM33->TSSR0;
300 volatile uint32_t *titsr = &R_INTC_IM33->TITSR0;
301 volatile uint32_t *tscr = &R_INTC_IM33->TSCR;
302 struct gpio_rz_int_data *data = dev->data;
303
304 /* Get register offset base on interrupt number. */
305 tssr = &tssr[int_num / 4];
306 titsr = &titsr[int_num / 16];
307
308 irq_disable(GPIO_RZ_TINT_IRQ_GET(int_num));
309 /* Disable interrupt and clear interrupt source. */
310 *tssr &= ~(0xFF << GPIO_RZ_TSSR_OFFSET(int_num));
311 /* Reset interrupt dectect type to default. */
312 *titsr &= ~(0x3 << GPIO_RZ_TITSR_OFFSET(int_num));
313
314 /* Clear interrupt detection status. */
315 if (data->irq_set_edge & BIT(int_num)) {
316 *tscr &= ~BIT(int_num);
317 data->irq_set_edge &= ~BIT(int_num);
318 }
319
320 data->gpio_mapping[int_num].gpio_dev = NULL;
321 data->gpio_mapping[int_num].pin = UINT8_MAX;
322 #elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
323 const struct gpio_rz_config *gpio_config = gpio_dev->config;
324 const struct device *eirq_dev = gpio_config->eirq_dev[pin];
325
326 if (device_is_ready(eirq_dev)) {
327 intc_rz_ext_irq_disable(eirq_dev);
328 }
329 #endif /* CONFIG_SOC_SERIES_* */
330
331 return 0;
332 }
333
gpio_rz_int_enable(const struct device * int_dev,const struct device * gpio_dev,uint8_t int_num,uint8_t irq_type,gpio_pin_t pin)334 static int gpio_rz_int_enable(const struct device *int_dev, const struct device *gpio_dev,
335 uint8_t int_num, uint8_t irq_type, gpio_pin_t pin)
336 {
337 if (irq_type == GPIO_RZ_INT_UNSUPPORTED) {
338 return -ENOTSUP;
339 }
340
341 const struct gpio_rz_config *gpio_config = gpio_dev->config;
342
343 #if defined(CONFIG_SOC_SERIES_RZG3S)
344 volatile uint32_t *tssr = &R_INTC_IM33->TSSR0;
345 volatile uint32_t *titsr = &R_INTC_IM33->TITSR0;
346 struct gpio_rz_int_data *int_data = int_dev->data;
347
348 tssr = &tssr[int_num / 4];
349 titsr = &titsr[int_num / 16];
350 /* Select interrupt detect type. */
351 *titsr &= ~(3U << GPIO_RZ_TITSR_OFFSET(int_num));
352 *titsr |= (irq_type << GPIO_RZ_TITSR_OFFSET(int_num));
353 /* Select interrupt source base on port and pin number.*/
354 *tssr |= (GPIO_RZ_TSSR_VAL(gpio_config->port_num, pin)) << GPIO_RZ_TSSR_OFFSET(int_num);
355
356 if (irq_type == GPIO_RZ_INT_EDGE_RISING || irq_type == GPIO_RZ_INT_EDGE_FALLING) {
357 int_data->irq_set_edge |= BIT(int_num);
358 /* Clear interrupt status. */
359 R_INTC_IM33->TSCR &= ~BIT(int_num);
360 }
361 irq_enable(GPIO_RZ_TINT_IRQ_GET(int_num));
362 int_data->gpio_mapping[int_num].gpio_dev = gpio_dev;
363 int_data->gpio_mapping[int_num].pin = pin;
364 #elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
365 const struct device *eirq_dev = gpio_config->eirq_dev[pin];
366 struct gpio_rz_data *gpio_data = gpio_dev->data;
367
368 gpio_data->pin[int_num] = pin;
369 if (device_is_ready(eirq_dev)) {
370 intc_rz_ext_irq_set_type(eirq_dev, irq_type);
371 intc_rz_ext_irq_enable(eirq_dev);
372 intc_rz_ext_irq_set_callback(eirq_dev, gpio_config->cb_list[int_num],
373 (void *)gpio_dev);
374 }
375 #endif /* CONFIG_SOC_SERIES_* */
376
377 return 0;
378 }
379
gpio_rz_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)380 static int gpio_rz_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
381 enum gpio_int_mode mode, enum gpio_int_trig trig)
382 {
383 const struct gpio_rz_config *config = dev->config;
384 struct gpio_rz_data *data = dev->data;
385 bsp_io_port_pin_t port_pin = config->fsp_port | pin;
386 uint8_t int_num = config->int_num[pin];
387 uint8_t irq_type = 0;
388 struct gpio_rz_hw_config pre_flags;
389 k_spinlock_key_t key;
390 int ret = 0;
391
392 if (int_num >= GPIO_RZ_MAX_INT_NUM) {
393 LOG_DEV_ERR(dev, "Invalid interrupt:%d >= %d", int_num, GPIO_RZ_MAX_INT_NUM);
394 }
395
396 if (pin > config->ngpios) {
397 return -EINVAL;
398 }
399
400 key = k_spin_lock(&data->lock);
401
402 if (mode == GPIO_INT_MODE_DISABLED) {
403 gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
404 pre_flags.p_pm |= GPIO_INT_DISABLE;
405 gpio_rz_pin_configure(dev, pin, pre_flags.p_pm);
406 gpio_rz_int_disable(config->int_dev, dev, int_num, pin);
407 goto exit_unlock;
408 }
409
410 if (mode == GPIO_INT_MODE_EDGE) {
411 if (trig == GPIO_INT_TRIG_LOW) {
412 irq_type = GPIO_RZ_INT_EDGE_FALLING;
413 } else if (trig == GPIO_INT_TRIG_HIGH) {
414 irq_type = GPIO_RZ_INT_EDGE_RISING;
415 } else if (trig == GPIO_INT_TRIG_BOTH) {
416 irq_type = GPIO_RZ_INT_BOTH_EDGE;
417 }
418 } else {
419 if (trig == GPIO_INT_TRIG_LOW) {
420 irq_type = GPIO_RZ_INT_LEVEL_LOW;
421 } else if (trig == GPIO_INT_TRIG_HIGH) {
422 irq_type = GPIO_RZ_INT_LEVEL_HIGH;
423 }
424 }
425
426 ret = gpio_rz_int_enable(config->int_dev, dev, int_num, irq_type, pin);
427 if (ret == 0) {
428 gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
429 pre_flags.p_pm |= GPIO_INT_ENABLE;
430 gpio_rz_pin_configure(dev, pin, pre_flags.p_pm);
431 }
432
433 exit_unlock:
434 k_spin_unlock(&data->lock, key);
435 return ret;
436 }
437
gpio_rz_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)438 static int gpio_rz_manage_callback(const struct device *dev, struct gpio_callback *callback,
439 bool set)
440 {
441 struct gpio_rz_data *data = dev->data;
442
443 return gpio_manage_callback(&data->cb, callback, set);
444 }
445
gpio_rz_isr(uint16_t irq,void * param)446 static void gpio_rz_isr(uint16_t irq, void *param)
447 {
448 #if defined(CONFIG_SOC_SERIES_RZG3S)
449 const struct device *dev = param;
450 struct gpio_rz_int_data *int_data = dev->data;
451 volatile uint32_t *tscr = &R_INTC_IM33->TSCR;
452
453 if (!(*tscr & BIT(irq))) {
454 LOG_DEV_DBG(dev, "tint:%u spurious irq, status 0", irq);
455 return;
456 }
457
458 if (int_data->irq_set_edge & BIT(irq)) {
459 *tscr &= ~BIT(irq);
460 }
461
462 uint8_t pin = int_data->gpio_mapping[irq].pin;
463 const struct device *gpio_dev = int_data->gpio_mapping[irq].gpio_dev;
464 struct gpio_rz_data *gpio_data = gpio_dev->data;
465
466 gpio_fire_callbacks(&gpio_data->cb, gpio_dev, BIT(pin));
467 #elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
468 const struct device *gpio_dev = (const struct device *)param;
469 struct gpio_rz_data *gpio_data = gpio_dev->data;
470 uint8_t pin = gpio_data->pin[irq];
471
472 gpio_fire_callbacks(&gpio_data->cb, gpio_dev, BIT(pin));
473 #endif /* CONFIG_SOC_SERIES_* */
474 }
475
476 #endif /* GPIO_RZ_HAS_INTERRUPT */
477
478 static DEVICE_API(gpio, gpio_rz_driver_api) = {
479 .pin_configure = gpio_rz_pin_configure,
480 #ifdef CONFIG_GPIO_GET_CONFIG
481 .pin_get_config = gpio_rz_pin_get_config,
482 #endif
483 .port_get_raw = gpio_rz_port_get_raw,
484 .port_set_masked_raw = gpio_rz_port_set_masked_raw,
485 .port_set_bits_raw = gpio_rz_port_set_bits_raw,
486 .port_clear_bits_raw = gpio_rz_port_clear_bits_raw,
487 .port_toggle_bits = gpio_rz_port_toggle_bits,
488 #if GPIO_RZ_HAS_INTERRUPT
489 .pin_interrupt_configure = gpio_rz_pin_interrupt_configure,
490 .manage_callback = gpio_rz_manage_callback,
491 #endif
492 };
493
494 /*Initialize GPIO interrupt device*/
495 #define GPIO_RZ_ISR_DEFINE(irq_num, _) \
496 static void rz_gpio_isr##irq_num(void *param) \
497 { \
498 gpio_rz_isr(irq_num, param); \
499 }
500
501 #define GPIO_RZ_ALL_ISR_DEFINE(irq_num) LISTIFY(irq_num, GPIO_RZ_ISR_DEFINE, ())
502
503 #if defined(CONFIG_SOC_SERIES_RZG3S)
504
505 #define GPIO_RZ_INT_DEFINE(inst) .int_dev = DEVICE_DT_GET_OR_NULL(DT_INST(0, renesas_rz_gpio_int))
506
gpio_rz_int_init(const struct device * dev)507 static int gpio_rz_int_init(const struct device *dev)
508 {
509 const struct gpio_rz_tint_config *config = dev->config;
510
511 config->gpio_int_init();
512 return 0;
513 }
514
515 #define GPIO_RZ_TINT_CONNECT(irq_num, node_id) \
516 IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, irq_num, irq), \
517 DT_IRQ_BY_IDX(node_id, irq_num, priority), rz_gpio_isr##irq_num, \
518 DEVICE_DT_GET(node_id), 0);
519
520 #define GPIO_RZ_TINT_CONNECT_FUNC(node_id) \
521 static void rz_gpio_tint_connect_func##node_id(void) \
522 { \
523 LISTIFY(DT_NUM_IRQS(node_id), \
524 GPIO_RZ_TINT_CONNECT, (;), \
525 node_id) \
526 }
527 /* Initialize GPIO device*/
528 #define GPIO_RZ_INT_INIT(node_id) \
529 GPIO_RZ_ALL_ISR_DEFINE(DT_NUM_IRQS(node_id)) \
530 GPIO_RZ_TINT_CONNECT_FUNC(node_id) \
531 static const struct gpio_rz_tint_config rz_gpio_tint_cfg_##node_id = { \
532 .gpio_int_init = rz_gpio_tint_connect_func##node_id, \
533 }; \
534 static struct gpio_rz_int_data rz_gpio_tint_data_##node_id = {}; \
535 DEVICE_DT_DEFINE(node_id, gpio_rz_int_init, NULL, &rz_gpio_tint_data_##node_id, \
536 &rz_gpio_tint_cfg_##node_id, POST_KERNEL, \
537 UTIL_DEC(CONFIG_GPIO_INIT_PRIORITY), NULL);
538 DT_FOREACH_STATUS_OKAY(renesas_rz_gpio_int, GPIO_RZ_INT_INIT)
539
540 #elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) && GPIO_RZ_HAS_INTERRUPT
541
542 GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM)
543
544 #define EIRQ_CB_GET(eirq_line, _) [eirq_line] = rz_gpio_isr##eirq_line
545
546 #define EIRQ_DEV_LABEL_GET(inst, idx) CONCAT(irq, DT_INST_PROP_BY_IDX(inst, irqs, UTIL_INC(idx)))
547
548 #define EIRQ_DEV_GET(idx, inst) \
549 COND_CODE_1(DT_INST_PROP_HAS_IDX(inst, irqs, idx), \
550 ([DT_INST_PROP_BY_IDX(inst, irqs, idx)] = \
551 DEVICE_DT_GET_OR_NULL(DT_NODELABEL(EIRQ_DEV_LABEL_GET(inst, idx))),), \
552 ())
553
554 #define ALL_EIRQ_DEV_GET(inst) \
555 FOR_EACH_FIXED_ARG(EIRQ_DEV_GET, (), inst, \
556 LISTIFY(DT_INST_PROP_LEN_OR(inst, irqs, 0), VALUE_2X, (,)))
557
558 #define GPIO_RZ_INT_DEFINE(inst) \
559 .eirq_dev = {ALL_EIRQ_DEV_GET(inst)}, \
560 .cb_list = {LISTIFY(GPIO_RZ_MAX_INT_NUM, EIRQ_CB_GET, (,))}
561 #else
562 #define GPIO_RZ_INT_DEFINE(inst)
563 #endif /* CONFIG_SOC_SERIES_* */
564
565 #define VALUE_2X(i, _) UTIL_X2(i)
566 #define PIN_IRQ_GET(idx, inst) \
567 COND_CODE_1(DT_INST_PROP_HAS_IDX(inst, irqs, idx), \
568 ([DT_INST_PROP_BY_IDX(inst, irqs, idx)] = \
569 DT_INST_PROP_BY_IDX(inst, irqs, UTIL_INC(idx)),), \
570 ())
571
572 #define PIN_IRQS_GET(inst) \
573 FOR_EACH_FIXED_ARG(PIN_IRQ_GET, (), inst, \
574 LISTIFY(DT_INST_PROP_LEN_OR(inst, irqs, 0), VALUE_2X, (,)))
575
576 #define RZG_GPIO_PORT_INIT(inst) \
577 static ioport_cfg_t g_ioport_##inst##_cfg = { \
578 .number_of_pins = 0, \
579 .p_pin_cfg_data = NULL, \
580 .p_extend = NULL, \
581 }; \
582 static const struct gpio_rz_config gpio_rz_##inst##_config = { \
583 .common = \
584 { \
585 .port_pin_mask = \
586 (gpio_port_pins_t)GPIO_PORT_PIN_MASK_FROM_DT_INST(inst), \
587 }, \
588 .fsp_port = (uint32_t)DT_INST_REG_ADDR(inst), \
589 .port_num = (uint8_t)DT_NODE_CHILD_IDX(DT_DRV_INST(inst)), \
590 .ngpios = (uint8_t)DT_INST_PROP(inst, ngpios), \
591 .fsp_cfg = &g_ioport_##inst##_cfg, \
592 .fsp_api = &g_ioport_on_ioport, \
593 .int_num = {PIN_IRQS_GET(inst)}, \
594 GPIO_RZ_INT_DEFINE(inst)}; \
595 static ioport_instance_ctrl_t g_ioport_##inst##_ctrl; \
596 static struct gpio_rz_data gpio_rz_##inst##_data = { \
597 .fsp_ctrl = &g_ioport_##inst##_ctrl, \
598 }; \
599 DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &gpio_rz_##inst##_data, &gpio_rz_##inst##_config, \
600 POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, &gpio_rz_driver_api);
601
602 DT_INST_FOREACH_STATUS_OKAY(RZG_GPIO_PORT_INIT)
603
