1 /* SPDX-License-Identifier: Apache-2.0 */ 2 /* 3 * Copyright (c) 2023 Intel Corporation 4 * 5 * Author: Adrian Warecki <adrian.warecki@intel.com> 6 */ 7 8 #ifndef __INTEL_DAI_DRIVER_DMIC_NHLT_H__ 9 #define __INTEL_DAI_DRIVER_DMIC_NHLT_H__ 10 11 /* For NHLT DMIC configuration parsing */ 12 #define DMIC_HW_CONTROLLERS_MAX 4 13 #define DMIC_HW_FIFOS_MAX 2 14 15 struct nhlt_dmic_gateway_attributes { 16 uint32_t dw; 17 }; 18 19 /* Time-slot mappings */ 20 struct nhlt_dmic_ts_group { 21 uint32_t ts_group[4]; 22 }; 23 24 /* Global configuration settings */ 25 struct nhlt_dmic_global_config { 26 uint32_t clock_on_delay; 27 }; 28 29 /* PDM channels to be programmed using data from channel_cfg array. */ 30 struct nhlt_dmic_channel_ctrl_mask { 31 /* i'th bit = 1 means that configuration for PDM channel # i is provided. */ 32 uint8_t channel_ctrl_mask; 33 uint8_t clock_source; 34 uint16_t rsvd; 35 }; 36 37 /* Channel configuration, see PDM HW specification for details. */ 38 struct nhlt_dmic_channel_config { 39 uint32_t out_control; 40 }; 41 42 struct nhlt_dmic_config_blob { 43 struct nhlt_dmic_gateway_attributes gtw_attributes; 44 struct nhlt_dmic_ts_group time_slot; 45 struct nhlt_dmic_global_config global_config; 46 struct nhlt_dmic_channel_ctrl_mask ctrl_mask; 47 struct nhlt_dmic_channel_config channel_config[]; 48 }; 49 50 struct nhlt_pdm_ctrl_mask { 51 uint32_t pdm_ctrl_mask; 52 }; 53 54 /* FIR configuration, see PDM HW specification for details. 55 * 56 * If there is only one PDM controller configuration passed, the other (missing) one is configured 57 * by the driver just by clearing CIC_CONTROL.SOFT_RESET bit. 58 * 59 * The driver needs to make sure that all mics are disabled before starting to program PDM 60 * controllers. 61 */ 62 struct nhlt_pdm_ctrl_fir_cfg { 63 uint32_t fir_control; 64 uint32_t fir_config; 65 int32_t dc_offset_left; 66 int32_t dc_offset_right; 67 int32_t out_gain_left; 68 int32_t out_gain_right; 69 uint32_t reserved[2]; 70 }; 71 72 /* PDM controller configuration, see PDM HW specification for details. */ 73 struct nhlt_pdm_ctrl_cfg { 74 uint32_t cic_control; 75 uint32_t cic_config; 76 77 uint32_t reserved0; 78 uint32_t mic_control; 79 80 /* PDM SoundWire Map 81 * 82 * This field is used on platforms with SoundWire, otherwise ignored. 83 */ 84 uint32_t pdm_sdw_map; 85 86 /* Index of another nhlt_pdm_ctrl_cfg to be used as a source of FIR coefficients. 87 * 88 * The index is 1-based, value of 0 means that FIR coefficients array fir_coeffs is provided 89 * by this item. 90 * This is a very common case that the same FIR coefficients are used to program more than 91 * one PDM controller. In this case, fir_coeffs array may be provided in a single copy 92 * following nhlt_pdm_ctrl_cfg #0 and be reused by nhlt_pdm_ctrl_cfg #1 by setting 93 * reuse_fir_from_pdm to 1 (1-based index). 94 */ 95 uint32_t reuse_fir_from_pdm; 96 uint32_t reserved1[2]; 97 98 /* FIR configurations */ 99 struct nhlt_pdm_ctrl_fir_cfg fir_config[2]; 100 101 /* Array of FIR coefficients, channel A goes first, then channel B. 102 * 103 * Actual size of the array depends on the number of active taps of the FIR filter for 104 * channel A plus the number of active taps of the FIR filter for channel B (see FIR_CONFIG) 105 * as well as on the form (packed/unpacked) of values. 106 */ 107 uint32_t fir_coeffs[]; 108 }; 109 110 /* Tag indicating that FIRs are in a packed 24-bit format. 111 * 112 * Size of a single coefficient is 20-bit. Coefficients may be sent in either unpacked form where 113 * each value takes one DWORD (32-bits) or in packed form where the array begins with 114 * (FIR_COEFFS_PACKED_TO_24_BITS) value to indicate packed form (unpacked coefficient has always 115 * most significant byte set to 0) followed by array of 24-bit values (in little endian form). 116 */ 117 #define FIR_COEFFS_PACKED_TO_24_BITS 0xFFFFFFFF 118 119 #endif /* __INTEL_DAI_DRIVER_DMIC_NHLT_H__ */ 120
