1 /*
2  * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <stdlib.h>
8 #include "spi_flash_chip_generic.h"
9 #include "spi_flash_defs.h"
10 #include "esp_log.h"
11 #include "string.h"
12 #include <sys/param.h> // For MIN/MAX
13 #include "hal/spi_flash_hal.h"
14 
15 #define CMD_OPI_FLASH_MXIC(cmd)              ((((~(cmd) & 0xff) << 8)) | ((cmd) & 0xff))
16 #define CMD_OPI_FLASH_MXIC_CHIP_ERASE        0x9F60
17 #define CMD_OPI_FLASH_MXIC_READ_STR          0x13EC
18 #define CMD_OPI_FLASH_MXIC_READ_DTR          0x11EE
19 #define CMD_OPI_FLASH_MXIC_RDCR2             0x8E71
20 #define CMD_OPI_FLASH_MXIC_WRCR2             0x8D72
21 
22 /* Driver for MXIC OPI flash chip */
23 static const char chip_name[] = "mxic (opi)";
24 
spi_flash_chip_mxic_opi_probe(esp_flash_t * chip,uint32_t flash_id)25 esp_err_t spi_flash_chip_mxic_opi_probe(esp_flash_t *chip, uint32_t flash_id)
26 {
27     /* Check manufacturer and product IDs match our desired masks */
28     const uint8_t MFG_ID = 0xC2;
29     if (flash_id >> 16 != MFG_ID) {
30         return ESP_ERR_NOT_FOUND;
31     }
32 
33     if (chip->read_mode < SPI_FLASH_OPI_FLAG) {
34         // The code here serve for opi flash under opi mode only, for ordinary mxic chip, go `spi_flash_chip_mxic.c`
35         return ESP_ERR_NOT_FOUND;
36     }
37 
38     return ESP_OK;
39 }
40 
spi_flash_chip_mxic_opi_detect_size(esp_flash_t * chip,uint32_t * size)41 esp_err_t spi_flash_chip_mxic_opi_detect_size(esp_flash_t *chip, uint32_t *size)
42 {
43     uint32_t id = chip->chip_id;
44     *size = 0;
45 
46     /* Can't detect size unless the high byte of the product ID matches the same convention, which is usually 0x40 or
47      * 0xC0 or similar. */
48     if (((id & 0xFFFF) == 0x0000) || ((id & 0xFFFF) == 0xFFFF)) {
49         return ESP_ERR_FLASH_UNSUPPORTED_CHIP;
50     }
51 
52     *size = 1 << ((id & 0xFF) - 0x20);
53     return ESP_OK;
54 }
55 
spi_flash_chip_mxic_opi_get_caps(esp_flash_t * chip)56 spi_flash_caps_t spi_flash_chip_mxic_opi_get_caps(esp_flash_t *chip)
57 {
58     spi_flash_caps_t caps_flags = 0;
59     caps_flags |= SPI_FLASH_CHIP_CAP_32MB_SUPPORT;
60     // flash-suspend is not supported yet. // IDF-3852
61     // reading unique id is not supported.
62     return caps_flags;
63 }
64 
spi_flash_chip_mxic_opi_set_write_protect(esp_flash_t * chip,bool write_protect)65 esp_err_t spi_flash_chip_mxic_opi_set_write_protect(esp_flash_t *chip, bool write_protect)
66 {
67     esp_err_t err = ESP_OK;
68 
69     err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
70     spi_flash_trans_t t = {};
71     if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
72         if(write_protect) {
73             t.command = CMD_OPI_FLASH_MXIC(CMD_WRDI);
74         } else {
75             t.command = CMD_OPI_FLASH_MXIC(CMD_WREN);
76         }
77         err = chip->host->driver->common_command(chip->host, &t);
78     }
79 
80     bool wp_read;
81     err = chip->chip_drv->get_chip_write_protect(chip, &wp_read);
82     if (err == ESP_OK && wp_read != write_protect) {
83         err = ESP_ERR_NOT_FOUND;
84     }
85     return err;
86 }
87 
spi_flash_chip_mxic_opi_get_data_length_zoom(esp_flash_io_mode_t io_mode,uint32_t * length_zoom)88 static void spi_flash_chip_mxic_opi_get_data_length_zoom(esp_flash_io_mode_t io_mode, uint32_t *length_zoom)
89 {
90     /* Under STR mode, one byte occupies one single clock. While under DTR mode, one byte occupies half clock.
91        For exmaple, if an operation needs 3 clock dummy, host send 3 dummy bytes under STR mode, while 6 dummy bytes under DTR mode.
92        Therefore, we need to adjust data zoom to fit the clock here. */
93     assert((io_mode == SPI_FLASH_OPI_STR) || (io_mode == SPI_FLASH_OPI_DTR));
94     *length_zoom = (io_mode == SPI_FLASH_OPI_STR) ? 1 : 2;
95 }
96 
spi_flash_chip_mxic_opi_read_id(esp_flash_t * chip,uint32_t * out_chip_id)97 esp_err_t spi_flash_chip_mxic_opi_read_id(esp_flash_t *chip, uint32_t* out_chip_id)
98 {
99     uint64_t id_buf = 0;
100     uint32_t length_zoom;
101     spi_flash_chip_mxic_opi_get_data_length_zoom(chip->read_mode, &length_zoom);
102     spi_flash_trans_t t = {
103         .command = CMD_OPI_FLASH_MXIC(CMD_RDID),
104         .miso_len = 3 * length_zoom,
105         .dummy_bitlen = 4 * length_zoom,
106         .address_bitlen = 32,
107         .miso_data = ((uint8_t*) &id_buf),
108     };
109 
110     chip->host->driver->common_command(chip->host, &t);
111 
112     if(chip->read_mode == SPI_FLASH_OPI_DTR) {
113         // Adjust the id_buf in DTR mode, because in DTR mode, the data back in STR rule.
114         // So it looks like [MD, MD, MT, MT, MID, MID], adjust it to [MD, MT, MID] here.
115         ESP_EARLY_LOGV(chip_name, "raw_chip_id: %llx\n", id_buf);
116         id_buf = (id_buf & 0xff) | ((id_buf & 0xff0000) >> 8) | ((id_buf & 0xff00000000) >> 16);
117     } else {
118         ESP_EARLY_LOGV(chip_name, "raw_chip_id: %X\n", id_buf);
119     }
120 
121     uint32_t raw_flash_id = __builtin_bswap32(id_buf);
122     if (raw_flash_id == 0xFFFFFF || raw_flash_id == 0) {
123         ESP_EARLY_LOGE(chip_name, "no response\n");
124         return ESP_ERR_FLASH_NO_RESPONSE;
125     }
126 
127     *out_chip_id = (raw_flash_id >> 8);
128     ESP_EARLY_LOGV(chip_name, "chip_id: %X\n", *out_chip_id);
129     return ESP_OK;
130 }
131 
spi_flash_chip_mxic_opi_read_reg(esp_flash_t * chip,spi_flash_register_t reg_id,uint32_t * out_reg)132 esp_err_t spi_flash_chip_mxic_opi_read_reg(esp_flash_t *chip, spi_flash_register_t reg_id, uint32_t* out_reg)
133 {
134     uint32_t stat_buf = 0;
135     uint32_t length_zoom;
136     spi_flash_chip_mxic_opi_get_data_length_zoom(chip->read_mode, &length_zoom);
137     spi_flash_trans_t t = {
138         .command = CMD_OPI_FLASH_MXIC(CMD_RDSR),
139         .miso_data = ((uint8_t*) &stat_buf),
140         .miso_len = 1 * length_zoom,
141         .address_bitlen = 32,
142         .dummy_bitlen = 4 * length_zoom,
143     };
144     esp_err_t err = chip->host->driver->common_command(chip->host, &t);
145     if (err != ESP_OK) {
146         return err;
147     }
148 
149     // For DTR mode, RDSR result like [SR1, SR1], just keeping one SR1.
150     *out_reg = (stat_buf & 0xff);
151     return ESP_OK;
152 }
153 
spi_flash_chip_mxic_opi_get_write_protect(esp_flash_t * chip,bool * out_write_protected)154 esp_err_t spi_flash_chip_mxic_opi_get_write_protect(esp_flash_t *chip, bool *out_write_protected)
155 {
156     esp_err_t err = ESP_OK;
157     uint32_t status;
158     assert(out_write_protected!=NULL);
159     err = chip->chip_drv->read_reg(chip, SPI_FLASH_REG_STATUS, &status);
160     if (err != ESP_OK) {
161         return err;
162     }
163 
164     *out_write_protected = ((status & SR_WREN) == 0);
165     return err;
166 }
167 
spi_flash_chip_mxic_opi_erase_chip(esp_flash_t * chip)168 esp_err_t spi_flash_chip_mxic_opi_erase_chip(esp_flash_t *chip)
169 {
170     esp_err_t err;
171 
172     err = chip->chip_drv->set_chip_write_protect(chip, false);
173     if (err == ESP_OK) {
174         err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
175     }
176 
177     if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
178         // Do erase chip here.
179         spi_flash_trans_t t = {
180             .command = CMD_OPI_FLASH_MXIC_CHIP_ERASE,
181         };
182         err = chip->host->driver->common_command(chip->host, &t);
183         chip->busy = 1;
184 #ifdef CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED
185         err = chip->chip_drv->wait_idle(chip, ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT);
186 #else
187         err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->chip_erase_timeout);
188 #endif
189     }
190     // Ensure WEL is 0, even if the erase failed.
191     if (err == ESP_ERR_NOT_SUPPORTED) {
192         chip->chip_drv->set_chip_write_protect(chip, true);
193     }
194 
195     return err;
196 
197 }
198 
spi_flash_chip_mxic_opi_erase_sector(esp_flash_t * chip,uint32_t start_address)199 esp_err_t spi_flash_chip_mxic_opi_erase_sector(esp_flash_t *chip, uint32_t start_address)
200 {
201     esp_err_t err = chip->chip_drv->set_chip_write_protect(chip, false);
202     if (err == ESP_OK) {
203         err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
204     }
205     //The chip didn't accept the previous write command. Ignore this in preparationstage.
206     if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
207         spi_flash_trans_t t = {
208             .command = CMD_OPI_FLASH_MXIC(CMD_SECTOR_ERASE_4B),
209             .address_bitlen = 32,
210             .address = start_address,
211         };
212         err = chip->host->driver->common_command(chip->host, &t);
213         chip->busy = 1;
214 #ifdef CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED
215         err = chip->chip_drv->wait_idle(chip, ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT);
216 #else
217         err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->sector_erase_timeout);
218 #endif
219     }
220     // Ensure WEL is 0, even if the erase failed.
221     if (err == ESP_ERR_NOT_SUPPORTED) {
222         err = chip->chip_drv->set_chip_write_protect(chip, true);
223     }
224 
225     return err;
226 }
227 
spi_flash_chip_mxic_opi_erase_block(esp_flash_t * chip,uint32_t start_address)228 esp_err_t spi_flash_chip_mxic_opi_erase_block(esp_flash_t *chip, uint32_t start_address)
229 {
230     esp_err_t err = chip->chip_drv->set_chip_write_protect(chip, false);
231     if (err == ESP_OK) {
232         err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
233     }
234     //The chip didn't accept the previous write command. Ignore this in preparationstage.
235     if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
236         spi_flash_trans_t t = {
237             .command = CMD_OPI_FLASH_MXIC(CMD_LARGE_BLOCK_ERASE_4B),
238             .address_bitlen = 32,
239             .address = start_address,
240         };
241         err = chip->host->driver->common_command(chip->host, &t);
242         chip->busy = 1;
243 #ifdef CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED
244         err = chip->chip_drv->wait_idle(chip, ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT);
245 #else
246         err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->block_erase_timeout);
247 #endif
248     }
249     // Ensure WEL is 0, even if the erase failed.
250     if (err == ESP_ERR_NOT_SUPPORTED) {
251         err = chip->chip_drv->set_chip_write_protect(chip, true);
252     }
253 
254     return err;
255 }
256 
spi_flash_chip_mxic_opi_page_program(esp_flash_t * chip,const void * buffer,uint32_t address,uint32_t length)257 esp_err_t spi_flash_chip_mxic_opi_page_program(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length)
258 {
259     esp_err_t err;
260 
261     err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout);
262     //The chip didn't accept the previous write command. Ignore this in preparationstage.
263     if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) {
264         // Perform the actual Page Program command
265         spi_flash_trans_t t = {
266             .command = CMD_OPI_FLASH_MXIC(CMD_PROGRAM_PAGE_4B),
267             .address_bitlen = 32,
268             .address = address,
269             .mosi_len = length,
270             .mosi_data = buffer,
271         };
272         chip->host->driver->common_command(chip->host, &t);
273         chip->busy = 1;
274 
275         err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->page_program_timeout);
276     }
277     // Ensure WEL is 0, even if the page program failed.
278     if (err == ESP_ERR_NOT_SUPPORTED) {
279         err = chip->chip_drv->set_chip_write_protect(chip, true);
280     }
281     return err;
282 }
283 
spi_flash_chip_mxic_opi_write(esp_flash_t * chip,const void * buffer,uint32_t address,uint32_t length)284 esp_err_t spi_flash_chip_mxic_opi_write(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length)
285 {
286     esp_err_t err = ESP_OK;
287     const uint32_t page_size = chip->chip_drv->page_size;
288     uint32_t align_address;
289     uint8_t temp_buffer[64]; //spiflash hal max length of write no longer than 64byte
290 
291     while (err == ESP_OK && length > 0) {
292         memset(temp_buffer, 0xFF, sizeof(temp_buffer));
293         uint32_t page_len = chip->host->driver->write_data_slicer(chip->host, address, length, &align_address, page_size);
294         uint32_t left_off = address - align_address;
295         uint32_t write_len = MIN(align_address + page_len, address + length) - address;
296         memcpy(temp_buffer + left_off, buffer, write_len);
297 
298         err = chip->chip_drv->set_chip_write_protect(chip, false);
299         if (err == ESP_OK && length > 0) {
300             err = chip->chip_drv->program_page(chip, temp_buffer, align_address, page_len);
301 
302             address += write_len;
303             buffer = (void *)((intptr_t)buffer + write_len);
304             length -= write_len;
305         }
306     }
307     // The caller is responsible to do host->driver->flush_cache, because this function may be
308     // called in small pieces. Frequency call of flush cache will do harm to the performance.
309     return err;
310 }
311 
spi_flash_chip_mxic_opi_get_io_mode(esp_flash_t * chip,esp_flash_io_mode_t * out_io_mode)312 esp_err_t spi_flash_chip_mxic_opi_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
313 {
314     uint32_t stat_buf = 0;
315     uint32_t length_zoom;
316     spi_flash_chip_mxic_opi_get_data_length_zoom(chip->read_mode, &length_zoom);
317 
318     spi_flash_trans_t t = {
319         .command = CMD_OPI_FLASH_MXIC_RDCR2,
320         .dummy_bitlen = 4 * length_zoom,
321         .miso_data = ((uint8_t*) &stat_buf),
322         .miso_len = 1 * length_zoom,
323         .address_bitlen = 32,
324     };
325     esp_err_t err = chip->host->driver->common_command(chip->host, &t);
326     if (err != ESP_OK) {
327         return err;
328     }
329 
330     // For DTR mode, RDSR result like [CR1, CR1], just keeping one CR1.
331     switch (stat_buf & 0xff)
332     {
333     case 0x1:
334         *out_io_mode = SPI_FLASH_OPI_STR;
335         break;
336     case 0x2:
337         *out_io_mode = SPI_FLASH_OPI_DTR;
338         break;
339     default:
340         // wrong mode.
341         *out_io_mode = 0;
342         break;
343     }
344     if (*out_io_mode != chip->read_mode) {
345         // Current chip mode is not the mode we configured.
346         *out_io_mode = 0;
347     }
348 
349     return ESP_OK;
350 }
351 
spi_flash_chip_xmic_opi_set_io_mode(esp_flash_t * chip)352 esp_err_t spi_flash_chip_xmic_opi_set_io_mode(esp_flash_t *chip)
353 {
354     // TODO: configure opi flash chip set io mode, only useful for external flash currently.
355     // For main flash, we already set io mode when chip starts up. But for external flash,
356     // We need to set mode when flash initialized, so keeping this for future usage.
357     return ESP_OK;
358 }
359 
360 // This function should only be called after opi mode initialization. So, only configure for OPI-STR/OPI-DTR mode
361 // not support other mode in this file, return `ESP_ERR_FLASH_NOT_INITIALISED` directely.
spi_flash_chip_xmic_opi_config_host_io_mode(esp_flash_t * chip,uint32_t flags)362 esp_err_t spi_flash_chip_xmic_opi_config_host_io_mode(esp_flash_t *chip, uint32_t flags)
363 {
364     uint32_t dummy_cyclelen_base;
365     uint32_t addr_bitlen;
366     uint32_t read_command;
367     esp_flash_io_mode_t read_mode = chip->read_mode;
368 
369     switch (read_mode & 0xFFFF) {
370     case SPI_FLASH_OPI_STR:
371         addr_bitlen = SPI_FLASH_OPISTR_ADDR_BITLEN;
372         dummy_cyclelen_base = SPI_FLASH_OPISTR_DUMMY_BITLEN;
373         read_command = CMD_OPI_FLASH_MXIC_READ_STR;
374         break;
375     case SPI_FLASH_OPI_DTR:
376         addr_bitlen = SPI_FLASH_OPIDTR_ADDR_BITLEN;
377         dummy_cyclelen_base = SPI_FLASH_OPIDTR_DUMMY_BITLEN;
378         read_command = CMD_OPI_FLASH_MXIC_READ_DTR;
379         break;
380     default:
381         return ESP_ERR_FLASH_NOT_INITIALISED;
382     }
383 
384     return chip->host->driver->configure_host_io_mode(chip->host, read_command, addr_bitlen, dummy_cyclelen_base, read_mode);
385 }
386 
387 // Most of mxic opi implementations are totally different from that is generic.
388 // Replace them to opi implementation.
389 const spi_flash_chip_t esp_flash_chip_mxic_opi = {
390     .name = chip_name,
391     .timeout = &spi_flash_chip_generic_timeout,
392     .probe = spi_flash_chip_mxic_opi_probe,
393     .reset = spi_flash_chip_generic_reset,
394     .detect_size = spi_flash_chip_mxic_opi_detect_size,
395     .erase_chip = spi_flash_chip_mxic_opi_erase_chip,
396     .erase_sector = spi_flash_chip_mxic_opi_erase_sector,
397     .erase_block = spi_flash_chip_mxic_opi_erase_block,
398     .sector_size = 4 * 1024,
399     .block_erase_size = 64 * 1024,
400 
401     .get_chip_write_protect = spi_flash_chip_mxic_opi_get_write_protect,
402     .set_chip_write_protect = spi_flash_chip_mxic_opi_set_write_protect,
403 
404     .num_protectable_regions = 0,
405     .protectable_regions = NULL,
406     .get_protected_regions = NULL,
407     .set_protected_regions = NULL,
408 
409     .read = spi_flash_chip_generic_read,
410     .write = spi_flash_chip_mxic_opi_write,
411     .program_page = spi_flash_chip_mxic_opi_page_program,
412     .page_size = 256,
413     .write_encrypted = spi_flash_chip_generic_write_encrypted,
414 
415     .wait_idle = spi_flash_chip_generic_wait_idle,
416 
417     .set_io_mode = spi_flash_chip_xmic_opi_set_io_mode,
418     .get_io_mode = spi_flash_chip_mxic_opi_get_io_mode,
419 
420     .read_id = spi_flash_chip_mxic_opi_read_id,
421     .read_reg = spi_flash_chip_mxic_opi_read_reg,
422     .yield = spi_flash_chip_generic_yield,
423     .sus_setup = spi_flash_chip_generic_suspend_cmd_conf,
424     .read_unique_id = spi_flash_chip_generic_read_unique_id_none,
425     .get_chip_caps = spi_flash_chip_mxic_opi_get_caps,
426     .config_host_io_mode = spi_flash_chip_xmic_opi_config_host_io_mode,
427 };
428