1 /*
2 * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /* ----------------------------------------------------------------------
20 * Project: CMSIS NN Library
21 * Title: arm_elementwise_mul_s8
22 * Description: Element wise multiplication
23 *
24 * $Date: January 26, 2021
25 * $Revision: V.1.0.5
26 *
27 * Target Processor: Cortex-M cores
28 *
29 * -------------------------------------------------------------------- */
30
31 #include "arm_nnfunctions.h"
32 #include "arm_nnsupportfunctions.h"
33
34 /**
35 * @ingroup groupNN
36 */
37
38 /**
39 * @addtogroup BasicMath
40 * @{
41 */
42
43 /**
44 * @brief s8 element wise multiplication of two vectors
45 *
46 * @note Refer header file for details.
47 *
48 */
49
arm_elementwise_mul_s8(const int8_t * input_1_vect,const int8_t * input_2_vect,const int32_t input_1_offset,const int32_t input_2_offset,int8_t * output,const int32_t out_offset,const int32_t out_mult,const int32_t out_shift,const int32_t out_activation_min,const int32_t out_activation_max,const uint32_t block_size)50 arm_status arm_elementwise_mul_s8(const int8_t *input_1_vect,
51 const int8_t *input_2_vect,
52 const int32_t input_1_offset,
53 const int32_t input_2_offset,
54 int8_t *output,
55 const int32_t out_offset,
56 const int32_t out_mult,
57 const int32_t out_shift,
58 const int32_t out_activation_min,
59 const int32_t out_activation_max,
60 const uint32_t block_size)
61 {
62
63 int32_t loop_count;
64 #if defined(ARM_MATH_MVEI)
65
66 loop_count = (block_size + 3) / 4;
67 uint32_t num_elements = block_size;
68
69 for (int i = 0; i < loop_count; i++)
70 {
71 mve_pred16_t p = vctp32q(num_elements);
72
73 int32x4_t input_1 = vldrbq_z_s32(input_1_vect, p);
74 input_1 = vaddq_n_s32(input_1, input_1_offset);
75
76 int32x4_t input_2 = vldrbq_z_s32(input_2_vect, p);
77 input_2 = vaddq_n_s32(input_2, input_2_offset);
78
79 int32x4_t res_0 = vmulq_s32(input_1, input_2);
80
81 res_0 = arm_requantize_mve_32x4(res_0, vdupq_n_s32(out_mult), vdupq_n_s32(out_shift));
82
83 res_0 += vdupq_n_s32(out_offset);
84
85 res_0 = vmaxq_s32(res_0, vdupq_n_s32(out_activation_min));
86 res_0 = vminq_s32(res_0, vdupq_n_s32(out_activation_max));
87
88 vstrbq_p_s32(output, res_0, p);
89 input_1_vect += 4;
90 input_2_vect += 4;
91 output += 4;
92 num_elements -= 4;
93 }
94
95 #else
96 int32_t input_1;
97 int32_t input_2;
98 int32_t mul_res;
99
100 #if defined(ARM_MATH_DSP)
101 int32_t a_1, b_1, a_2, b_2;
102
103 int32_t offset_1_packed, offset_2_packed;
104
105 int8_t r1, r2, r3, r4;
106
107 offset_1_packed = (input_1_offset << 16U) | (input_1_offset & 0x0FFFFL);
108 offset_2_packed = (input_2_offset << 16U) | (input_2_offset & 0x0FFFFL);
109
110 loop_count = block_size >> 2;
111
112 while (loop_count > 0)
113 {
114 /* 4 outputs are calculated in one loop. The order of calculation is follows the order of output sign extension
115 intrinsic */
116 input_1_vect = read_and_pad_reordered(input_1_vect, &b_1, &a_1);
117 input_2_vect = read_and_pad_reordered(input_2_vect, &b_2, &a_2);
118
119 a_1 = __SADD16(a_1, offset_1_packed);
120 b_1 = __SADD16(b_1, offset_1_packed);
121
122 a_2 = __SADD16(a_2, offset_2_packed);
123 b_2 = __SADD16(b_2, offset_2_packed);
124
125 /* Mul 1 */
126 input_1 = (int16_t)(b_1 & 0x0FFFFL);
127 input_2 = (int16_t)(b_2 & 0x0FFFFL);
128
129 mul_res = input_1 * input_2;
130 mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset;
131
132 mul_res = MAX(mul_res, out_activation_min);
133 mul_res = MIN(mul_res, out_activation_max);
134 r1 = (q7_t)mul_res;
135
136 /* Mul 3 */
137 input_1 = (int16_t)((b_1 >> 16U) & 0x0FFFFL);
138 input_2 = (int16_t)((b_2 >> 16U) & 0x0FFFFL);
139
140 mul_res = input_1 * input_2;
141 mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset;
142 mul_res = MAX(mul_res, out_activation_min);
143 mul_res = MIN(mul_res, out_activation_max);
144 r3 = (q7_t)mul_res;
145
146 /* Mul 2 */
147 input_1 = (int16_t)(a_1 & 0x0FFFFL);
148 input_2 = (int16_t)(a_2 & 0x0FFFFL);
149
150 mul_res = input_1 * input_2;
151 mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset;
152 mul_res = MAX(mul_res, out_activation_min);
153 mul_res = MIN(mul_res, out_activation_max);
154 r2 = (q7_t)mul_res;
155
156 /* Mul 4 */
157 input_1 = (int16_t)((a_1 >> 16U) & 0x0FFFFL);
158 input_2 = (int16_t)((a_2 >> 16U) & 0x0FFFFL);
159
160 mul_res = input_1 * input_2;
161 mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset;
162 mul_res = MAX(mul_res, out_activation_min);
163 mul_res = MIN(mul_res, out_activation_max);
164 r4 = (q7_t)mul_res;
165
166 write_q7x4_ia(&output, __PACKq7(r1, r2, r3, r4));
167
168 loop_count--;
169 }
170
171 loop_count = block_size & 0x3;
172 #else
173 loop_count = block_size;
174 #endif
175
176 while (loop_count > 0)
177 {
178 /* C = A * B */
179
180 input_1 = *input_1_vect++ + input_1_offset;
181 input_2 = *input_2_vect++ + input_2_offset;
182
183 mul_res = input_1 * input_2;
184 mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset;
185
186 mul_res = MAX(mul_res, out_activation_min);
187 mul_res = MIN(mul_res, out_activation_max);
188
189 *output++ = (q7_t)mul_res;
190
191 /* Decrement loop counter */
192 loop_count--;
193 }
194 #endif
195 return ARM_MATH_SUCCESS;
196 }
197
198 /**
199 * @} end of BasicMath group
200 */
201
