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/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_enet.c735 uint32_t num = 0U, count = 0U, maxsize = 0U; in enet_descriptors_chain_init() local
807 uint32_t num = 0U, count = 0U, maxsize = 0U; in enet_descriptors_ring_init() local
1395 void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) in enet_registers_get()
2338 uint32_t num = 0U, count = 0U, maxsize = 0U; in enet_ptp_enhanced_descriptors_chain_init() local
2408 uint32_t num = 0U, count = 0U, maxsize = 0U; in enet_ptp_enhanced_descriptors_ring_init() local
2685 uint32_t num = 0U, count = 0U, maxsize = 0U; in enet_ptp_normal_descriptors_chain_init() local
2764 uint32_t num = 0U, count = 0U, maxsize = 0U; in enet_ptp_normal_descriptors_ring_init() local
3051 uint32_t num = 0U; in enet_wum_filter_config() local
Dgd32f4xx_adc.c578 uint32_t num = 0U; in adc_inserted_channel_offset_config() local
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e50x/standard_peripheral/source/
Dgd32e50x_enet.c733 uint32_t num = 0U, count = 0U, maxsize = 0U; in enet_descriptors_chain_init() local
805 uint32_t num = 0U, count = 0U, maxsize = 0U; in enet_descriptors_ring_init() local
1403 void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) in enet_registers_get()
2347 uint32_t num = 0U, count = 0U, maxsize = 0U; in enet_ptp_enhanced_descriptors_chain_init() local
2417 uint32_t num = 0U, count = 0U, maxsize = 0U; in enet_ptp_enhanced_descriptors_ring_init() local
2695 uint32_t num = 0U, count = 0U, maxsize = 0U; in enet_ptp_normal_descriptors_chain_init() local
2774 uint32_t num = 0U, count = 0U, maxsize = 0U; in enet_ptp_normal_descriptors_ring_init() local
3060 uint32_t num = 0U; in enet_wum_filter_config() local
Dgd32e50x_adc.c448 uint32_t num = 0U; in adc_inserted_channel_offset_config() local
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_adc.c408 uint32_t num = 0U; in adc_inserted_channel_offset_config() local
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32l23x/standard_peripheral/source/
Dgd32l23x_adc.c463 uint32_t num = 0U; in adc_inserted_channel_offset_config() local
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32f403/standard_peripheral/source/
Dgd32f403_adc.c450 uint32_t num = 0U; in adc_inserted_channel_offset_config() local
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/source/
Dgd32a50x_adc.c443 uint32_t num = 0U; in adc_inserted_channel_offset_config() local
Dgd32a50x_can.c658 uint32_t num; in can_rx_fifo_config() local
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32vf103/standard_peripheral/source/
Dgd32vf103_adc.c467 uint32_t num = 0U; in adc_inserted_channel_offset_config() local
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32e10x/standard_peripheral/source/
Dgd32e10x_adc.c553 uint32_t num = 0U; in adc_inserted_channel_offset_config() local
/hal_gigadevice-3.7.0-3.6.0-3.5.0-3.4.0/gd32a50x/standard_peripheral/include/
Dgd32a50x_can.h540 #define CAN_RFIFOMPF(canx, num) REG32((canx) + 0x00000880U + (num) * 0x00000004U) /*!< CAN r… argument