1 /*
2 * Copyright (c) 2021 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRFY_UARTE_H__
35 #define NRFY_UARTE_H__
36
37 #include <nrfx.h>
38 #include <hal/nrf_uarte.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 typedef struct nrfy_uarte_xfer_desc_t nrfy_uarte_xfer_desc_t;
45
46 NRFY_STATIC_INLINE void __nrfy_internal_uarte_event_enabled_clear(NRF_UARTE_Type * p_reg,
47 uint32_t mask,
48 nrf_uarte_event_t event);
49
50 NRFY_STATIC_INLINE bool __nrfy_internal_uarte_event_handle(NRF_UARTE_Type * p_reg,
51 uint32_t mask,
52 nrf_uarte_event_t event,
53 uint32_t * p_evt_mask);
54
55 NRFY_STATIC_INLINE
56 uint32_t __nrfy_internal_uarte_events_process(NRF_UARTE_Type * p_reg,
57 uint32_t mask,
58 nrfy_uarte_xfer_desc_t const * p_xfer);
59
60 /**
61 * @defgroup nrfy_uarte UARTE HALY
62 * @{
63 * @ingroup nrf_uarte
64 * @brief Hardware access layer with cache and barrier support for managing the UARTE peripheral.
65 */
66
67 /** @brief UARTE pins configuration structure. */
68 typedef struct
69 {
70 uint32_t txd_pin; ///< TXD pin number.
71 uint32_t rxd_pin; ///< RXD pin number.
72 uint32_t rts_pin; ///< RTS pin number.
73 uint32_t cts_pin; ///< CTS pin number.
74 } nrfy_uarte_pins_t;
75
76 /** @brief UARTE configuration structure. */
77 typedef struct
78 {
79 nrfy_uarte_pins_t pins; ///< Pin configuration structure.
80 nrf_uarte_baudrate_t baudrate; ///< Baud rate.
81 nrf_uarte_config_t config; ///< Peripheral configuration.
82 bool skip_psel_cfg; ///< Skip pin selection configuration.
83 /**< When set to true, the driver does not modify
84 * pin select registers in the peripheral.
85 * Those registers are supposed to be set up
86 * externally before the driver is initialized.
87 * @note When both GPIO configuration and pin
88 * selection are to be skipped, the structure
89 * fields that specify pins can be omitted,
90 * as they are ignored anyway. */
91 } nrfy_uarte_config_t;
92
93 /** @brief Structure describing an UARTE transfer. */
94 struct nrfy_uarte_xfer_desc_t
95 {
96 uint8_t * p_buffer; ///< Pointer to transferred data.
97 size_t length; ///< Number of bytes transferred.
98 };
99
100 /**
101 * @brief Function for configuring the UARTE.
102 *
103 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
104 * @param[in] p_config Pointer to the peripheral configuration structure.
105 */
nrfy_uarte_periph_configure(NRF_UARTE_Type * p_reg,nrfy_uarte_config_t const * p_config)106 NRFY_STATIC_INLINE void nrfy_uarte_periph_configure(NRF_UARTE_Type * p_reg,
107 nrfy_uarte_config_t const * p_config)
108 {
109 nrf_uarte_baudrate_set(p_reg, p_config->baudrate);
110 nrf_uarte_configure(p_reg, &p_config->config);
111 if (!p_config->skip_psel_cfg)
112 {
113 nrf_uarte_txrx_pins_set(p_reg, p_config->pins.txd_pin, p_config->pins.rxd_pin);
114 }
115
116 if (p_config->config.hwfc == NRF_UARTE_HWFC_ENABLED && !p_config->skip_psel_cfg)
117 {
118 nrf_uarte_hwfc_pins_set(p_reg, p_config->pins.rts_pin, p_config->pins.cts_pin);
119 }
120 nrf_barrier_w();
121 }
122
123 /**
124 * @brief Function for initializing the specified UARTE interrupts.
125 *
126 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
127 * @param[in] mask Mask of interrupts to be initialized.
128 * @param[in] irq_priority Interrupt priority.
129 * @param[in] enable True if interrupts associated with the event mask are to be enabled, false otherwise.
130 */
nrfy_uarte_int_init(NRF_UARTE_Type * p_reg,uint32_t mask,uint8_t irq_priority,bool enable)131 NRFY_STATIC_INLINE void nrfy_uarte_int_init(NRF_UARTE_Type * p_reg,
132 uint32_t mask,
133 uint8_t irq_priority,
134 bool enable)
135 {
136 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_CTS);
137 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_NCTS);
138 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_RXDRDY);
139 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_ENDRX);
140 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_TXDRDY);
141 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_ENDTX);
142 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_ERROR);
143 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_RXTO);
144 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_RXSTARTED);
145 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_TXSTARTED);
146 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_TXSTOPPED);
147 nrf_barrier_w();
148
149 NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_reg), irq_priority);
150 NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_reg));
151 if (enable)
152 {
153 nrf_uarte_int_enable(p_reg, mask);
154 }
155 nrf_barrier_w();
156 }
157
158 /**
159 * @brief Function for uninitializing the UARTE interrupts.
160 *
161 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
162 */
nrfy_uarte_int_uninit(NRF_UARTE_Type * p_reg)163 NRFY_STATIC_INLINE void nrfy_uarte_int_uninit(NRF_UARTE_Type * p_reg)
164 {
165 NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_reg));
166 nrf_barrier_w();
167 }
168
169 /**
170 * @brief Function for processing the specified UARTE events.
171 *
172 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
173 * @param[in] mask Mask of events to be processed, created by @ref NRFY_EVENT_TO_INT_BITMASK().
174 * @param[in] p_xfer Pointer to the structure containing buffer associated with the last reception.
175 * Can be NULL.
176 *
177 * @return Mask of events that were generated and processed.
178 * To be checked against the result of @ref NRFY_EVENT_TO_INT_BITMASK().
179 */
nrfy_uarte_events_process(NRF_UARTE_Type * p_reg,uint32_t mask,nrfy_uarte_xfer_desc_t const * p_xfer)180 NRFY_STATIC_INLINE uint32_t nrfy_uarte_events_process(NRF_UARTE_Type * p_reg,
181 uint32_t mask,
182 nrfy_uarte_xfer_desc_t const * p_xfer)
183 {
184 uint32_t evt_mask = __nrfy_internal_uarte_events_process(p_reg, mask, p_xfer);
185 nrf_barrier_w();
186 return evt_mask;
187 }
188
189 /**
190 * @brief Function for aborting the ongoing UARTE transmission.
191 *
192 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
193 * @param[in] wait True if CPU should wait for peripheral to abort transmission, false otherwise.
194 */
nrfy_uarte_tx_abort(NRF_UARTE_Type * p_reg,bool wait)195 NRFY_STATIC_INLINE void nrfy_uarte_tx_abort(NRF_UARTE_Type * p_reg,
196 bool wait)
197 {
198 nrf_uarte_event_clear(p_reg, NRF_UARTE_EVENT_TXSTOPPED);
199 nrf_barrier_w();
200 nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STOPTX);
201 if (wait)
202 {
203 nrf_barrier_w();
204 while (!nrf_uarte_event_check(p_reg, NRF_UARTE_EVENT_TXSTOPPED))
205 {}
206 }
207 nrf_barrier_w();
208 }
209
210 /**
211 * @brief Function for stopping the UARTE transmitter and receiver.
212 *
213 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
214 * @param[in] p_xfer Pointer to the structure containing reception buffer. Can be NULL.
215 */
nrfy_uarte_stop(NRF_UARTE_Type * p_reg,nrfy_uarte_xfer_desc_t const * p_xfer)216 NRFY_STATIC_INLINE void nrfy_uarte_stop(NRF_UARTE_Type * p_reg,
217 nrfy_uarte_xfer_desc_t const * p_xfer)
218 {
219 nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STOPTX);
220 nrf_barrier_w();
221 while (!__nrfy_internal_uarte_events_process(p_reg,
222 NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_TXSTOPPED),
223 NULL))
224 {}
225 if (p_xfer && p_xfer->length)
226 {
227 nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STOPRX);
228 nrf_barrier_w();
229 while (!__nrfy_internal_uarte_events_process(p_reg,
230 NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_RXTO),
231 p_xfer))
232 {}
233 }
234 }
235
236 /**
237 * @brief Function for starting the UARTE transmission.
238 *
239 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
240 * @param[in] wait True for blocking transmission, false otherwise.
241 *
242 * @return Mask of events occured, created by @ref NRFY_EVENT_TO_INT_BITMASK().
243 * Always 0 for non-blocking transmission.
244 */
nrfy_uarte_tx_start(NRF_UARTE_Type * p_reg,bool wait)245 NRFY_STATIC_INLINE uint32_t nrfy_uarte_tx_start(NRF_UARTE_Type * p_reg,
246 bool wait)
247 {
248 uint32_t evt_mask = 0;
249 nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STARTTX);
250 if (wait)
251 {
252 uint32_t mask = NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_ENDTX) |
253 NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_TXSTOPPED);
254 nrf_barrier_w();
255 do {
256 evt_mask = nrfy_uarte_events_process(p_reg, mask, NULL);
257 } while (!evt_mask);
258 }
259 nrf_barrier_w();
260 return evt_mask;
261 }
262
263 /**
264 * @brief Function for starting the UARTE reception.
265 *
266 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
267 * @param[in] p_xfer Pointer to the structure containing reception buffer if the
268 * reception is to be blocking. NULL for non-blocking reception.
269 *
270 * @return Mask of events occured, created by @ref NRFY_EVENT_TO_INT_BITMASK().
271 * Always 0 for non-blocking reception.
272 */
nrfy_uarte_rx_start(NRF_UARTE_Type * p_reg,nrfy_uarte_xfer_desc_t const * p_xfer)273 NRFY_STATIC_INLINE uint32_t nrfy_uarte_rx_start(NRF_UARTE_Type * p_reg,
274 nrfy_uarte_xfer_desc_t const * p_xfer)
275 {
276 uint32_t evt_mask = 0;
277 nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STARTRX);
278 if (p_xfer)
279 {
280 uint32_t mask = NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_ENDRX) |
281 NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_RXTO) |
282 NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_ERROR);
283 nrf_barrier_w();
284 do {
285 evt_mask = nrfy_uarte_events_process(p_reg, mask, p_xfer);
286 } while (!evt_mask);
287 }
288 nrf_barrier_w();
289 return evt_mask;
290 }
291
292 /**
293 * @brief Function for getting UARTE pins configuration.
294 *
295 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
296 * @param[in] p_pins Pointer to the UARTE pin configurartion structure.
297 */
nrfy_uarte_pins_get(NRF_UARTE_Type const * p_reg,nrfy_uarte_pins_t * p_pins)298 NRFY_STATIC_INLINE void nrfy_uarte_pins_get(NRF_UARTE_Type const * p_reg,
299 nrfy_uarte_pins_t * p_pins)
300 {
301 nrf_barrier_rw();
302 p_pins->txd_pin = nrf_uarte_tx_pin_get(p_reg);
303 p_pins->rxd_pin = nrf_uarte_rx_pin_get(p_reg);
304 p_pins->rts_pin = nrf_uarte_rts_pin_get(p_reg);
305 p_pins->cts_pin = nrf_uarte_cts_pin_get(p_reg);
306 nrf_barrier_r();
307 }
308
309 /**
310 * @brief Function for disconnecting UARTE pins.
311 *
312 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
313 */
nrfy_uarte_pins_disconnect(NRF_UARTE_Type * p_reg)314 NRFY_STATIC_INLINE void nrfy_uarte_pins_disconnect(NRF_UARTE_Type * p_reg)
315 {
316 nrf_uarte_txrx_pins_disconnect(p_reg);
317 nrf_uarte_hwfc_pins_disconnect(p_reg);
318 nrf_barrier_w();
319 }
320
321 /** @refhal{nrf_uarte_event_clear} */
nrfy_uarte_event_clear(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)322 NRFY_STATIC_INLINE void nrfy_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
323 {
324 nrf_uarte_event_clear(p_reg, event);
325 nrf_barrier_w();
326 }
327
328 /** @refhal{nrf_uarte_event_check} */
nrfy_uarte_event_check(NRF_UARTE_Type const * p_reg,nrf_uarte_event_t event)329 NRFY_STATIC_INLINE bool nrfy_uarte_event_check(NRF_UARTE_Type const * p_reg,
330 nrf_uarte_event_t event)
331 {
332 nrf_barrier_r();
333 bool check = nrf_uarte_event_check(p_reg, event);
334 nrf_barrier_r();
335 return check;
336 }
337
338 /** @refhal{nrf_uarte_event_address_get} */
nrfy_uarte_event_address_get(NRF_UARTE_Type const * p_reg,nrf_uarte_event_t event)339 NRFY_STATIC_INLINE uint32_t nrfy_uarte_event_address_get(NRF_UARTE_Type const * p_reg,
340 nrf_uarte_event_t event)
341 {
342 return nrf_uarte_event_address_get(p_reg, event);
343 }
344
345 /** @refhal{nrf_uarte_shorts_enable} */
nrfy_uarte_shorts_enable(NRF_UARTE_Type * p_reg,uint32_t mask)346 NRFY_STATIC_INLINE void nrfy_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
347 {
348 nrf_uarte_shorts_enable(p_reg, mask);
349 nrf_barrier_w();
350 }
351
352 /** @refhal{nrf_uarte_shorts_disable} */
nrfy_uarte_shorts_disable(NRF_UARTE_Type * p_reg,uint32_t mask)353 NRFY_STATIC_INLINE void nrfy_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
354 {
355 nrf_uarte_shorts_disable(p_reg, mask);
356 nrf_barrier_w();
357 }
358
359 /** @refhal{nrf_uarte_int_enable} */
nrfy_uarte_int_enable(NRF_UARTE_Type * p_reg,uint32_t mask)360 NRFY_STATIC_INLINE void nrfy_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
361 {
362 nrf_uarte_int_enable(p_reg, mask);
363 nrf_barrier_w();
364 }
365
366 /** @refhal{nrf_uarte_int_enable_check} */
nrfy_uarte_int_enable_check(NRF_UARTE_Type const * p_reg,uint32_t mask)367 NRFY_STATIC_INLINE uint32_t nrfy_uarte_int_enable_check(NRF_UARTE_Type const * p_reg,
368 uint32_t mask)
369 {
370 nrf_barrier_rw();
371 uint32_t check = nrf_uarte_int_enable_check(p_reg, mask);
372 nrf_barrier_r();
373 return check;
374 }
375
376 /** @refhal{nrf_uarte_int_disable} */
nrfy_uarte_int_disable(NRF_UARTE_Type * p_reg,uint32_t mask)377 NRFY_STATIC_INLINE void nrfy_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
378 {
379 nrf_uarte_int_disable(p_reg, mask);
380 nrf_barrier_w();
381 }
382
383 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
384 /** @refhal{nrf_uarte_subscribe_set} */
nrfy_uarte_subscribe_set(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task,uint8_t channel)385 NRFY_STATIC_INLINE void nrfy_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
386 nrf_uarte_task_t task,
387 uint8_t channel)
388 {
389 nrf_uarte_subscribe_set(p_reg, task, channel);
390 nrf_barrier_w();
391 }
392
393 /** @refhal{nrf_uarte_subscribe_clear} */
nrfy_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)394 NRFY_STATIC_INLINE void nrfy_uarte_subscribe_clear(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
395 {
396 nrf_uarte_subscribe_clear(p_reg, task);
397 nrf_barrier_w();
398 }
399
400 /** @refhal{nrf_uarte_publish_set} */
nrfy_uarte_publish_set(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event,uint8_t channel)401 NRFY_STATIC_INLINE void nrfy_uarte_publish_set(NRF_UARTE_Type * p_reg,
402 nrf_uarte_event_t event,
403 uint8_t channel)
404 {
405 nrf_uarte_publish_set(p_reg, event, channel);
406 nrf_barrier_w();
407 }
408
409 /** @refhal{nrf_uarte_publish_clear} */
nrfy_uarte_publish_clear(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)410 NRFY_STATIC_INLINE void nrfy_uarte_publish_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
411 {
412 nrf_uarte_publish_clear(p_reg, event);
413 nrf_barrier_w();
414 }
415 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
416
417 /** @refhal{nrf_uarte_errorsrc_get_and_clear} */
nrfy_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)418 NRFY_STATIC_INLINE uint32_t nrfy_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)
419 {
420 nrf_barrier_rw();
421 uint32_t errorsrc = nrf_uarte_errorsrc_get_and_clear(p_reg);
422 nrf_barrier_rw();
423 return errorsrc;
424 }
425
426 /** @refhal{nrf_uarte_enable} */
nrfy_uarte_enable(NRF_UARTE_Type * p_reg)427 NRFY_STATIC_INLINE void nrfy_uarte_enable(NRF_UARTE_Type * p_reg)
428 {
429 nrf_uarte_enable(p_reg);
430 nrf_barrier_w();
431 }
432
433 /** @refhal{nrf_uarte_disable} */
nrfy_uarte_disable(NRF_UARTE_Type * p_reg)434 NRFY_STATIC_INLINE void nrfy_uarte_disable(NRF_UARTE_Type * p_reg)
435 {
436 nrf_uarte_disable(p_reg);
437 nrf_barrier_w();
438 }
439
440 /** @refhal{nrf_uarte_txrx_pins_set} */
nrfy_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,uint32_t pseltxd,uint32_t pselrxd)441 NRFY_STATIC_INLINE void nrfy_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,
442 uint32_t pseltxd,
443 uint32_t pselrxd)
444 {
445 nrf_uarte_txrx_pins_set(p_reg, pseltxd, pselrxd);
446 nrf_barrier_w();
447 }
448
449 /** @refhal{nrf_uarte_txrx_pins_disconnect} */
nrfy_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)450 NRFY_STATIC_INLINE void nrfy_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)
451 {
452 nrf_uarte_txrx_pins_disconnect(p_reg);
453 nrf_barrier_w();
454 }
455
456 /** @refhal{nrf_uarte_tx_pin_get} */
nrfy_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg)457 NRFY_STATIC_INLINE uint32_t nrfy_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg)
458 {
459 nrf_barrier_rw();
460 uint32_t pin = nrf_uarte_tx_pin_get(p_reg);
461 nrf_barrier_r();
462 return pin;
463 }
464
465 /** @refhal{nrf_uarte_rx_pin_get} */
nrfy_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg)466 NRFY_STATIC_INLINE uint32_t nrfy_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg)
467 {
468 nrf_barrier_rw();
469 uint32_t pin = nrf_uarte_rx_pin_get(p_reg);
470 nrf_barrier_r();
471 return pin;
472 }
473
474 /** @refhal{nrf_uarte_rts_pin_get} */
nrfy_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg)475 NRFY_STATIC_INLINE uint32_t nrfy_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg)
476 {
477 nrf_barrier_rw();
478 uint32_t pin = nrf_uarte_rts_pin_get(p_reg);
479 nrf_barrier_r();
480 return pin;
481 }
482
483 /** @refhal{nrf_uarte_cts_pin_get} */
nrfy_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg)484 NRFY_STATIC_INLINE uint32_t nrfy_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg)
485 {
486 nrf_barrier_rw();
487 uint32_t pin = nrf_uarte_cts_pin_get(p_reg);
488 nrf_barrier_r();
489 return pin;
490 }
491
492 /** @refhal{nrf_uarte_hwfc_pins_set} */
nrfy_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,uint32_t pselrts,uint32_t pselcts)493 NRFY_STATIC_INLINE void nrfy_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
494 uint32_t pselrts,
495 uint32_t pselcts)
496 {
497 nrf_uarte_hwfc_pins_set(p_reg, pselrts, pselcts);
498 nrf_barrier_w();
499 }
500
501 /** @refhal{nrf_uarte_hwfc_pins_disconnect} */
nrfy_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)502 NRFY_STATIC_INLINE void nrfy_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)
503 {
504 nrf_uarte_hwfc_pins_disconnect(p_reg);
505 nrf_barrier_w();
506 }
507
508 /** @refhal{nrf_uarte_task_trigger} */
nrfy_uarte_task_trigger(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)509 NRFY_STATIC_INLINE void nrfy_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
510 {
511 nrf_uarte_task_trigger(p_reg, task);
512 nrf_barrier_w();
513 }
514
515 /** @refhal{nrf_uarte_task_address_get} */
nrfy_uarte_task_address_get(NRF_UARTE_Type const * p_reg,nrf_uarte_task_t task)516 NRFY_STATIC_INLINE uint32_t nrfy_uarte_task_address_get(NRF_UARTE_Type const * p_reg,
517 nrf_uarte_task_t task)
518 {
519 return nrf_uarte_task_address_get(p_reg, task);
520 }
521
522 /** @refhal{nrf_uarte_configure} */
nrfy_uarte_configure(NRF_UARTE_Type * p_reg,nrf_uarte_config_t const * p_cfg)523 NRFY_STATIC_INLINE void nrfy_uarte_configure(NRF_UARTE_Type * p_reg,
524 nrf_uarte_config_t const * p_cfg)
525 {
526 nrf_uarte_configure(p_reg, p_cfg);
527 nrf_barrier_w();
528 }
529
530 /** @refhal{nrf_uarte_baudrate_set} */
nrfy_uarte_baudrate_set(NRF_UARTE_Type * p_reg,nrf_uarte_baudrate_t baudrate)531 NRFY_STATIC_INLINE void nrfy_uarte_baudrate_set(NRF_UARTE_Type * p_reg,
532 nrf_uarte_baudrate_t baudrate)
533 {
534 nrf_uarte_baudrate_set(p_reg, baudrate);
535 nrf_barrier_w();
536 }
537
538 /** @refhal{nrf_uarte_tx_buffer_set} */
nrfy_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,uint8_t const * p_buffer,size_t length)539 NRFY_STATIC_INLINE void nrfy_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
540 uint8_t const * p_buffer,
541 size_t length)
542 {
543 if (p_buffer)
544 {
545 NRFY_CACHE_WB(p_buffer, length);
546 nrf_uarte_tx_buffer_set(p_reg, p_buffer, length);
547 nrf_barrier_w();
548 }
549 }
550
551 /** @refhal{nrf_uarte_tx_amount_get} */
nrfy_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg)552 NRFY_STATIC_INLINE uint32_t nrfy_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg)
553 {
554 nrf_barrier_r();
555 uint32_t amount = nrf_uarte_tx_amount_get(p_reg);
556 nrf_barrier_r();
557 return amount;
558 }
559
560 /** @refhal{nrf_uarte_rx_buffer_set} */
nrfy_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,uint8_t * p_buffer,size_t length)561 NRFY_STATIC_INLINE void nrfy_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
562 uint8_t * p_buffer,
563 size_t length)
564 {
565 nrf_uarte_rx_buffer_set(p_reg, p_buffer, length);
566 nrf_barrier_w();
567 }
568
569 /** @refhal{nrf_uarte_rx_amount_get} */
nrfy_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)570 NRFY_STATIC_INLINE uint32_t nrfy_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)
571 {
572 nrf_barrier_r();
573 uint32_t amount = nrf_uarte_rx_amount_get(p_reg);
574 nrf_barrier_r();
575 return amount;
576 }
577 /** @} */
578
__nrfy_internal_uarte_event_enabled_clear(NRF_UARTE_Type * p_reg,uint32_t mask,nrf_uarte_event_t event)579 NRFY_STATIC_INLINE void __nrfy_internal_uarte_event_enabled_clear(NRF_UARTE_Type * p_reg,
580 uint32_t mask,
581 nrf_uarte_event_t event)
582 {
583 if (mask & NRFY_EVENT_TO_INT_BITMASK(event))
584 {
585 nrf_uarte_event_clear(p_reg, event);
586 }
587 }
588
__nrfy_internal_uarte_event_handle(NRF_UARTE_Type * p_reg,uint32_t mask,nrf_uarte_event_t event,uint32_t * p_evt_mask)589 NRFY_STATIC_INLINE bool __nrfy_internal_uarte_event_handle(NRF_UARTE_Type * p_reg,
590 uint32_t mask,
591 nrf_uarte_event_t event,
592 uint32_t * p_evt_mask)
593 {
594 if ((mask & NRFY_EVENT_TO_INT_BITMASK(event)) && nrf_uarte_event_check(p_reg, event))
595 {
596 nrf_uarte_event_clear(p_reg, event);
597 if (p_evt_mask)
598 {
599 *p_evt_mask |= NRFY_EVENT_TO_INT_BITMASK(event);
600 }
601 return true;
602 }
603 return false;
604 }
605
606 NRFY_STATIC_INLINE
__nrfy_internal_uarte_events_process(NRF_UARTE_Type * p_reg,uint32_t mask,nrfy_uarte_xfer_desc_t const * p_xfer)607 uint32_t __nrfy_internal_uarte_events_process(NRF_UARTE_Type * p_reg,
608 uint32_t mask,
609 nrfy_uarte_xfer_desc_t const * p_xfer)
610 {
611 uint32_t evt_mask = 0;
612
613 nrf_barrier_r();
614 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_CTS, &evt_mask);
615 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_NCTS, &evt_mask);
616 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_RXDRDY, &evt_mask);
617 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_ENDRX, &evt_mask);
618 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_TXDRDY, &evt_mask);
619 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_ENDTX, &evt_mask);
620 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_ERROR, &evt_mask);
621 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_RXTO, &evt_mask);
622 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_RXSTARTED, &evt_mask);
623 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_TXSTARTED, &evt_mask);
624 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_TXSTOPPED, &evt_mask);
625
626 if (mask & NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_ENDRX))
627 {
628 NRFY_CACHE_INV(p_xfer->p_buffer, p_xfer->length);
629 }
630 else if (mask & NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_RXTO))
631 {
632 size_t size = nrf_uarte_rx_amount_get(p_reg);
633 nrf_barrier_rw();
634 NRFY_CACHE_INV(p_xfer->p_buffer, size);
635 }
636 nrf_barrier_w();
637 return evt_mask;
638 }
639
640 #ifdef __cplusplus
641 }
642 #endif
643
644 #endif // NRFY_UARTE_H__
645
