1 /*
2 * Copyright (c) 2021 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRFY_UARTE_H__
35 #define NRFY_UARTE_H__
36
37 #include <nrfx.h>
38 #include <hal/nrf_uarte.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 #if NRF_UARTE_HAS_FRAME_TIMEOUT || defined(__NRFX_DOXYGEN__)
45 /** @refhal{NRF_UARTE_HAS_FRAME_TIMEOUT} */
46 #define NRFY_UARTE_HAS_FRAME_TIMEOUT 1
47 #else
48 #define NRFY_UARTE_HAS_FRAME_TIMEOUT 0
49 #endif
50
51 typedef struct nrfy_uarte_buffer_t nrfy_uarte_buffer_t;
52
53 NRFY_STATIC_INLINE void __nrfy_internal_uarte_event_enabled_clear(NRF_UARTE_Type * p_reg,
54 uint32_t mask,
55 nrf_uarte_event_t event);
56
57 NRFY_STATIC_INLINE bool __nrfy_internal_uarte_event_handle(NRF_UARTE_Type * p_reg,
58 uint32_t mask,
59 nrf_uarte_event_t event,
60 uint32_t * p_evt_mask);
61
62 NRFY_STATIC_INLINE
63 uint32_t __nrfy_internal_uarte_events_process(NRF_UARTE_Type * p_reg,
64 uint32_t mask,
65 nrfy_uarte_buffer_t const * p_xfer);
66
67 /**
68 * @defgroup nrfy_uarte UARTE HALY
69 * @{
70 * @ingroup nrf_uarte
71 * @brief Hardware access layer with cache and barrier support for managing the UARTE peripheral.
72 */
73
74 /** @brief UARTE pins configuration structure. */
75 typedef struct
76 {
77 uint32_t txd_pin; ///< TXD pin number.
78 uint32_t rxd_pin; ///< RXD pin number.
79 uint32_t rts_pin; ///< RTS pin number.
80 uint32_t cts_pin; ///< CTS pin number.
81 } nrfy_uarte_pins_t;
82
83 /** @brief UARTE configuration structure. */
84 typedef struct
85 {
86 nrfy_uarte_pins_t pins; ///< Pin configuration structure.
87 nrf_uarte_baudrate_t baudrate; ///< Baud rate.
88 nrf_uarte_config_t config; ///< Peripheral configuration.
89 bool skip_psel_cfg; ///< Skip pin selection configuration.
90 /**< When set to true, the driver does not modify
91 * pin select registers in the peripheral.
92 * Those registers are supposed to be set up
93 * externally before the driver is initialized.
94 * @note When both GPIO configuration and pin
95 * selection are to be skipped, the structure
96 * fields that specify pins can be omitted,
97 * as they are ignored anyway. */
98 } nrfy_uarte_config_t;
99
100 /** @brief Structure describing an UARTE transfer. */
101 struct nrfy_uarte_buffer_t
102 {
103 uint8_t * p_buffer; ///< Buffer address.
104 size_t length; ///< Data length.
105 };
106
107 /**
108 * @brief Function for configuring the UARTE.
109 *
110 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
111 * @param[in] p_config Pointer to the peripheral configuration structure.
112 */
nrfy_uarte_periph_configure(NRF_UARTE_Type * p_reg,nrfy_uarte_config_t const * p_config)113 NRFY_STATIC_INLINE void nrfy_uarte_periph_configure(NRF_UARTE_Type * p_reg,
114 nrfy_uarte_config_t const * p_config)
115 {
116 nrf_uarte_baudrate_set(p_reg, p_config->baudrate);
117 nrf_uarte_configure(p_reg, &p_config->config);
118 if (!p_config->skip_psel_cfg)
119 {
120 nrf_uarte_txrx_pins_set(p_reg, p_config->pins.txd_pin, p_config->pins.rxd_pin);
121 }
122
123 if (p_config->config.hwfc == NRF_UARTE_HWFC_ENABLED && !p_config->skip_psel_cfg)
124 {
125 nrf_uarte_hwfc_pins_set(p_reg, p_config->pins.rts_pin, p_config->pins.cts_pin);
126 }
127 nrf_barrier_w();
128 }
129
130 /**
131 * @brief Function for initializing the specified UARTE interrupts.
132 *
133 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
134 * @param[in] mask Mask of interrupts to be initialized.
135 * @param[in] irq_priority Interrupt priority.
136 * @param[in] enable True if interrupts associated with the event mask are to be enabled, false otherwise.
137 */
nrfy_uarte_int_init(NRF_UARTE_Type * p_reg,uint32_t mask,uint8_t irq_priority,bool enable)138 NRFY_STATIC_INLINE void nrfy_uarte_int_init(NRF_UARTE_Type * p_reg,
139 uint32_t mask,
140 uint8_t irq_priority,
141 bool enable)
142 {
143 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_CTS);
144 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_NCTS);
145 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_RXDRDY);
146 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_ENDRX);
147 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_TXDRDY);
148 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_ENDTX);
149 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_ERROR);
150 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_RXTO);
151 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_RXSTARTED);
152 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_TXSTARTED);
153 __nrfy_internal_uarte_event_enabled_clear(p_reg, mask, NRF_UARTE_EVENT_TXSTOPPED);
154 nrf_barrier_w();
155
156 NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_reg), irq_priority);
157 NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_reg));
158 if (enable)
159 {
160 nrf_uarte_int_enable(p_reg, mask);
161 }
162 nrf_barrier_w();
163 }
164
165 /**
166 * @brief Function for uninitializing the UARTE interrupts.
167 *
168 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
169 */
nrfy_uarte_int_uninit(NRF_UARTE_Type * p_reg)170 NRFY_STATIC_INLINE void nrfy_uarte_int_uninit(NRF_UARTE_Type * p_reg)
171 {
172 NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_reg));
173 nrf_barrier_w();
174 }
175
176 /**
177 * @brief Function for processing the specified UARTE events.
178 *
179 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
180 * @param[in] mask Mask of events to be processed, created by @ref NRFY_EVENT_TO_INT_BITMASK().
181 * @param[in] p_xfer Pointer to the structure containing buffer associated with the last reception.
182 * Can be NULL.
183 *
184 * @return Mask of events that were generated and processed.
185 * To be checked against the result of @ref NRFY_EVENT_TO_INT_BITMASK().
186 */
nrfy_uarte_events_process(NRF_UARTE_Type * p_reg,uint32_t mask,nrfy_uarte_buffer_t const * p_xfer)187 NRFY_STATIC_INLINE uint32_t nrfy_uarte_events_process(NRF_UARTE_Type * p_reg,
188 uint32_t mask,
189 nrfy_uarte_buffer_t const * p_xfer)
190 {
191 uint32_t evt_mask = __nrfy_internal_uarte_events_process(p_reg, mask, p_xfer);
192 nrf_barrier_w();
193 return evt_mask;
194 }
195
196 /**
197 * @brief Function for aborting the ongoing UARTE transmission.
198 *
199 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
200 * @param[in] wait True if CPU should wait for peripheral to abort transmission, false otherwise.
201 */
nrfy_uarte_tx_abort(NRF_UARTE_Type * p_reg,bool wait)202 NRFY_STATIC_INLINE void nrfy_uarte_tx_abort(NRF_UARTE_Type * p_reg,
203 bool wait)
204 {
205 nrf_uarte_event_clear(p_reg, NRF_UARTE_EVENT_TXSTOPPED);
206 nrf_barrier_w();
207 nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STOPTX);
208 if (wait)
209 {
210 nrf_barrier_w();
211 while (!nrf_uarte_event_check(p_reg, NRF_UARTE_EVENT_TXSTOPPED))
212 {}
213 }
214 nrf_barrier_w();
215 }
216
217 /**
218 * @brief Function for stopping the UARTE transmitter and receiver.
219 *
220 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
221 * @param[in] p_xfer Pointer to the structure containing reception buffer. Can be NULL.
222 */
nrfy_uarte_stop(NRF_UARTE_Type * p_reg,nrfy_uarte_buffer_t const * p_xfer)223 NRFY_STATIC_INLINE void nrfy_uarte_stop(NRF_UARTE_Type * p_reg,
224 nrfy_uarte_buffer_t const * p_xfer)
225 {
226 nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STOPTX);
227 nrf_barrier_w();
228 while (!__nrfy_internal_uarte_events_process(p_reg,
229 NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_TXSTOPPED),
230 NULL))
231 {}
232 if (p_xfer && p_xfer->length)
233 {
234 nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STOPRX);
235 nrf_barrier_w();
236 while (!__nrfy_internal_uarte_events_process(p_reg,
237 NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_RXTO),
238 p_xfer))
239 {}
240 }
241 }
242
243 /**
244 * @brief Function for starting the UARTE transmission.
245 *
246 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
247 * @param[in] wait True for blocking transmission, false otherwise.
248 *
249 * @return Mask of events occured, created by @ref NRFY_EVENT_TO_INT_BITMASK().
250 * Always 0 for non-blocking transmission.
251 */
nrfy_uarte_tx_start(NRF_UARTE_Type * p_reg,bool wait)252 NRFY_STATIC_INLINE uint32_t nrfy_uarte_tx_start(NRF_UARTE_Type * p_reg,
253 bool wait)
254 {
255 uint32_t evt_mask = 0;
256 nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STARTTX);
257 if (wait)
258 {
259 uint32_t mask = NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_ENDTX) |
260 NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_TXSTOPPED);
261 nrf_barrier_w();
262 do {
263 evt_mask = nrfy_uarte_events_process(p_reg, mask, NULL);
264 } while (!evt_mask);
265 }
266 nrf_barrier_w();
267 return evt_mask;
268 }
269
270 /**
271 * @brief Function for starting the UARTE reception.
272 *
273 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
274 * @param[in] p_xfer Pointer to the structure containing reception buffer if the
275 * reception is to be blocking. NULL for non-blocking reception.
276 *
277 * @return Mask of events occured, created by @ref NRFY_EVENT_TO_INT_BITMASK().
278 * Always 0 for non-blocking reception.
279 */
nrfy_uarte_rx_start(NRF_UARTE_Type * p_reg,nrfy_uarte_buffer_t const * p_xfer)280 NRFY_STATIC_INLINE uint32_t nrfy_uarte_rx_start(NRF_UARTE_Type * p_reg,
281 nrfy_uarte_buffer_t const * p_xfer)
282 {
283 uint32_t evt_mask = 0;
284 nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STARTRX);
285 if (p_xfer)
286 {
287 uint32_t mask = NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_ENDRX) |
288 NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_RXTO) |
289 NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_ERROR);
290 nrf_barrier_w();
291 do {
292 evt_mask = nrfy_uarte_events_process(p_reg, mask, p_xfer);
293 } while (!evt_mask);
294 }
295 nrf_barrier_w();
296 return evt_mask;
297 }
298
299 /**
300 * @brief Function for getting UARTE pins configuration.
301 *
302 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
303 * @param[in] p_pins Pointer to the UARTE pin configurartion structure.
304 */
nrfy_uarte_pins_get(NRF_UARTE_Type const * p_reg,nrfy_uarte_pins_t * p_pins)305 NRFY_STATIC_INLINE void nrfy_uarte_pins_get(NRF_UARTE_Type const * p_reg,
306 nrfy_uarte_pins_t * p_pins)
307 {
308 nrf_barrier_rw();
309 p_pins->txd_pin = nrf_uarte_tx_pin_get(p_reg);
310 p_pins->rxd_pin = nrf_uarte_rx_pin_get(p_reg);
311 p_pins->rts_pin = nrf_uarte_rts_pin_get(p_reg);
312 p_pins->cts_pin = nrf_uarte_cts_pin_get(p_reg);
313 nrf_barrier_r();
314 }
315
316 /**
317 * @brief Function for disconnecting UARTE pins.
318 *
319 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
320 */
nrfy_uarte_pins_disconnect(NRF_UARTE_Type * p_reg)321 NRFY_STATIC_INLINE void nrfy_uarte_pins_disconnect(NRF_UARTE_Type * p_reg)
322 {
323 nrf_uarte_txrx_pins_disconnect(p_reg);
324 nrf_uarte_hwfc_pins_disconnect(p_reg);
325 nrf_barrier_w();
326 }
327
328 /** @refhal{nrf_uarte_event_clear} */
nrfy_uarte_event_clear(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)329 NRFY_STATIC_INLINE void nrfy_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
330 {
331 nrf_uarte_event_clear(p_reg, event);
332 nrf_barrier_w();
333 }
334
335 /** @refhal{nrf_uarte_event_check} */
nrfy_uarte_event_check(NRF_UARTE_Type const * p_reg,nrf_uarte_event_t event)336 NRFY_STATIC_INLINE bool nrfy_uarte_event_check(NRF_UARTE_Type const * p_reg,
337 nrf_uarte_event_t event)
338 {
339 nrf_barrier_r();
340 bool check = nrf_uarte_event_check(p_reg, event);
341 nrf_barrier_r();
342 return check;
343 }
344
345 /** @refhal{nrf_uarte_event_address_get} */
nrfy_uarte_event_address_get(NRF_UARTE_Type const * p_reg,nrf_uarte_event_t event)346 NRFY_STATIC_INLINE uint32_t nrfy_uarte_event_address_get(NRF_UARTE_Type const * p_reg,
347 nrf_uarte_event_t event)
348 {
349 return nrf_uarte_event_address_get(p_reg, event);
350 }
351
352 /** @refhal{nrf_uarte_shorts_set} */
nrfy_uarte_shorts_set(NRF_UARTE_Type * p_reg,uint32_t mask)353 NRFY_STATIC_INLINE void nrfy_uarte_shorts_set(NRF_UARTE_Type * p_reg, uint32_t mask)
354 {
355 nrf_uarte_shorts_set(p_reg, mask);
356 nrf_barrier_w();
357 }
358
359 /** @refhal{nrf_uarte_shorts_get} */
nrfy_uarte_shorts_get(NRF_UARTE_Type * p_reg,uint32_t mask)360 NRFY_STATIC_INLINE uint32_t nrfy_uarte_shorts_get(NRF_UARTE_Type * p_reg, uint32_t mask)
361 {
362 nrf_barrier_rw();
363 uint32_t ret = nrf_uarte_shorts_get(p_reg, mask);
364 nrf_barrier_r();
365
366 return ret;
367 }
368
369 /** @refhal{nrf_uarte_shorts_enable} */
nrfy_uarte_shorts_enable(NRF_UARTE_Type * p_reg,uint32_t mask)370 NRFY_STATIC_INLINE void nrfy_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
371 {
372 nrf_uarte_shorts_enable(p_reg, mask);
373 nrf_barrier_w();
374 }
375
376 /** @refhal{nrf_uarte_shorts_disable} */
nrfy_uarte_shorts_disable(NRF_UARTE_Type * p_reg,uint32_t mask)377 NRFY_STATIC_INLINE void nrfy_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
378 {
379 nrf_uarte_shorts_disable(p_reg, mask);
380 nrf_barrier_w();
381 }
382
383 /** @refhal{nrf_uarte_int_enable} */
nrfy_uarte_int_enable(NRF_UARTE_Type * p_reg,uint32_t mask)384 NRFY_STATIC_INLINE void nrfy_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
385 {
386 nrf_uarte_int_enable(p_reg, mask);
387 nrf_barrier_w();
388 }
389
390 /** @refhal{nrf_uarte_int_enable_check} */
nrfy_uarte_int_enable_check(NRF_UARTE_Type const * p_reg,uint32_t mask)391 NRFY_STATIC_INLINE uint32_t nrfy_uarte_int_enable_check(NRF_UARTE_Type const * p_reg,
392 uint32_t mask)
393 {
394 nrf_barrier_rw();
395 uint32_t check = nrf_uarte_int_enable_check(p_reg, mask);
396 nrf_barrier_r();
397 return check;
398 }
399
400 /** @refhal{nrf_uarte_int_disable} */
nrfy_uarte_int_disable(NRF_UARTE_Type * p_reg,uint32_t mask)401 NRFY_STATIC_INLINE void nrfy_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
402 {
403 nrf_uarte_int_disable(p_reg, mask);
404 nrf_barrier_w();
405 }
406
407 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
408 /** @refhal{nrf_uarte_subscribe_set} */
nrfy_uarte_subscribe_set(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task,uint8_t channel)409 NRFY_STATIC_INLINE void nrfy_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
410 nrf_uarte_task_t task,
411 uint8_t channel)
412 {
413 nrf_uarte_subscribe_set(p_reg, task, channel);
414 nrf_barrier_w();
415 }
416
417 /** @refhal{nrf_uarte_subscribe_clear} */
nrfy_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)418 NRFY_STATIC_INLINE void nrfy_uarte_subscribe_clear(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
419 {
420 nrf_uarte_subscribe_clear(p_reg, task);
421 nrf_barrier_w();
422 }
423
424 /** @refhal{nrf_uarte_publish_set} */
nrfy_uarte_publish_set(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event,uint8_t channel)425 NRFY_STATIC_INLINE void nrfy_uarte_publish_set(NRF_UARTE_Type * p_reg,
426 nrf_uarte_event_t event,
427 uint8_t channel)
428 {
429 nrf_uarte_publish_set(p_reg, event, channel);
430 nrf_barrier_w();
431 }
432
433 /** @refhal{nrf_uarte_publish_clear} */
nrfy_uarte_publish_clear(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)434 NRFY_STATIC_INLINE void nrfy_uarte_publish_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
435 {
436 nrf_uarte_publish_clear(p_reg, event);
437 nrf_barrier_w();
438 }
439 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
440
441 /** @refhal{nrf_uarte_errorsrc_get_and_clear} */
nrfy_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)442 NRFY_STATIC_INLINE uint32_t nrfy_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)
443 {
444 nrf_barrier_rw();
445 uint32_t errorsrc = nrf_uarte_errorsrc_get(p_reg);
446 nrf_barrier_rw();
447 nrf_uarte_errorsrc_clear(p_reg, errorsrc);
448 nrf_barrier_rw();
449 return errorsrc;
450 }
451
452 /** @refhal{nrf_uarte_enable} */
nrfy_uarte_enable(NRF_UARTE_Type * p_reg)453 NRFY_STATIC_INLINE void nrfy_uarte_enable(NRF_UARTE_Type * p_reg)
454 {
455 nrf_uarte_enable(p_reg);
456 nrf_barrier_w();
457 }
458
459 /** @refhal{nrf_uarte_disable} */
nrfy_uarte_disable(NRF_UARTE_Type * p_reg)460 NRFY_STATIC_INLINE void nrfy_uarte_disable(NRF_UARTE_Type * p_reg)
461 {
462 nrf_uarte_disable(p_reg);
463 nrf_barrier_w();
464 }
465
466 /** @refhal{nrf_uarte_enable_check} */
nrfy_uarte_enable_check(NRF_UARTE_Type * p_reg)467 NRFY_STATIC_INLINE bool nrfy_uarte_enable_check(NRF_UARTE_Type * p_reg)
468 {
469 nrf_barrier_rw();
470 bool ret = nrf_uarte_enable_check(p_reg);
471 nrf_barrier_r();
472 return ret;
473 }
474
475 /** @refhal{nrf_uarte_txrx_pins_set} */
nrfy_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,uint32_t pseltxd,uint32_t pselrxd)476 NRFY_STATIC_INLINE void nrfy_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,
477 uint32_t pseltxd,
478 uint32_t pselrxd)
479 {
480 nrf_uarte_txrx_pins_set(p_reg, pseltxd, pselrxd);
481 nrf_barrier_w();
482 }
483
484 /** @refhal{nrf_uarte_txrx_pins_disconnect} */
nrfy_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)485 NRFY_STATIC_INLINE void nrfy_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)
486 {
487 nrf_uarte_txrx_pins_disconnect(p_reg);
488 nrf_barrier_w();
489 }
490
491 /** @refhal{nrf_uarte_tx_pin_get} */
nrfy_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg)492 NRFY_STATIC_INLINE uint32_t nrfy_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg)
493 {
494 nrf_barrier_rw();
495 uint32_t pin = nrf_uarte_tx_pin_get(p_reg);
496 nrf_barrier_r();
497 return pin;
498 }
499
500 /** @refhal{nrf_uarte_rx_pin_get} */
nrfy_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg)501 NRFY_STATIC_INLINE uint32_t nrfy_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg)
502 {
503 nrf_barrier_rw();
504 uint32_t pin = nrf_uarte_rx_pin_get(p_reg);
505 nrf_barrier_r();
506 return pin;
507 }
508
509 /** @refhal{nrf_uarte_rts_pin_get} */
nrfy_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg)510 NRFY_STATIC_INLINE uint32_t nrfy_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg)
511 {
512 nrf_barrier_rw();
513 uint32_t pin = nrf_uarte_rts_pin_get(p_reg);
514 nrf_barrier_r();
515 return pin;
516 }
517
518 /** @refhal{nrf_uarte_cts_pin_get} */
nrfy_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg)519 NRFY_STATIC_INLINE uint32_t nrfy_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg)
520 {
521 nrf_barrier_rw();
522 uint32_t pin = nrf_uarte_cts_pin_get(p_reg);
523 nrf_barrier_r();
524 return pin;
525 }
526
527 /** @refhal{nrf_uarte_hwfc_pins_set} */
nrfy_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,uint32_t pselrts,uint32_t pselcts)528 NRFY_STATIC_INLINE void nrfy_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
529 uint32_t pselrts,
530 uint32_t pselcts)
531 {
532 nrf_uarte_hwfc_pins_set(p_reg, pselrts, pselcts);
533 nrf_barrier_w();
534 }
535
536 /** @refhal{nrf_uarte_hwfc_pins_disconnect} */
nrfy_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)537 NRFY_STATIC_INLINE void nrfy_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)
538 {
539 nrf_uarte_hwfc_pins_disconnect(p_reg);
540 nrf_barrier_w();
541 }
542
543 /** @refhal{nrf_uarte_task_trigger} */
nrfy_uarte_task_trigger(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)544 NRFY_STATIC_INLINE void nrfy_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
545 {
546 nrf_uarte_task_trigger(p_reg, task);
547 nrf_barrier_w();
548 }
549
550 /** @refhal{nrf_uarte_task_address_get} */
nrfy_uarte_task_address_get(NRF_UARTE_Type const * p_reg,nrf_uarte_task_t task)551 NRFY_STATIC_INLINE uint32_t nrfy_uarte_task_address_get(NRF_UARTE_Type const * p_reg,
552 nrf_uarte_task_t task)
553 {
554 return nrf_uarte_task_address_get(p_reg, task);
555 }
556
557 /** @refhal{nrf_uarte_configure} */
nrfy_uarte_configure(NRF_UARTE_Type * p_reg,nrf_uarte_config_t const * p_cfg)558 NRFY_STATIC_INLINE void nrfy_uarte_configure(NRF_UARTE_Type * p_reg,
559 nrf_uarte_config_t const * p_cfg)
560 {
561 nrf_uarte_configure(p_reg, p_cfg);
562 nrf_barrier_w();
563 }
564
565 /** @refhal{nrf_uarte_baudrate_set} */
nrfy_uarte_baudrate_set(NRF_UARTE_Type * p_reg,nrf_uarte_baudrate_t baudrate)566 NRFY_STATIC_INLINE void nrfy_uarte_baudrate_set(NRF_UARTE_Type * p_reg,
567 nrf_uarte_baudrate_t baudrate)
568 {
569 nrf_uarte_baudrate_set(p_reg, baudrate);
570 nrf_barrier_w();
571 }
572
573 /** @refhal{nrf_uarte_tx_buffer_set} */
nrfy_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,uint8_t const * p_buffer,size_t length)574 NRFY_STATIC_INLINE void nrfy_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
575 uint8_t const * p_buffer,
576 size_t length)
577 {
578 if (p_buffer)
579 {
580 NRFY_CACHE_WB(p_buffer, length);
581 nrf_uarte_tx_buffer_set(p_reg, p_buffer, length);
582 nrf_barrier_w();
583 }
584 }
585
586 /** @refhal{nrf_uarte_tx_buffer_get} */
nrfy_uarte_tx_buffer_get(NRF_UARTE_Type * p_reg)587 NRFY_STATIC_INLINE uint8_t const * nrfy_uarte_tx_buffer_get(NRF_UARTE_Type * p_reg)
588 {
589 nrf_barrier_r();
590 uint8_t const * ptr = nrf_uarte_tx_buffer_get(p_reg);
591 nrf_barrier_r();
592 return ptr;
593 }
594
595 /** @refhal{nrf_uarte_tx_amount_get} */
nrfy_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg)596 NRFY_STATIC_INLINE uint32_t nrfy_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg)
597 {
598 nrf_barrier_r();
599 uint32_t amount = nrf_uarte_tx_amount_get(p_reg);
600 nrf_barrier_r();
601 return amount;
602 }
603
604 /** @refhal{nrf_uarte_rx_buffer_set} */
nrfy_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,uint8_t * p_buffer,size_t length)605 NRFY_STATIC_INLINE void nrfy_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
606 uint8_t * p_buffer,
607 size_t length)
608 {
609 nrf_uarte_rx_buffer_set(p_reg, p_buffer, length);
610 nrf_barrier_w();
611 }
612
613 /** @refhal{nrf_uarte_rx_amount_get} */
nrfy_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)614 NRFY_STATIC_INLINE uint32_t nrfy_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)
615 {
616 nrf_barrier_r();
617 uint32_t amount = nrf_uarte_rx_amount_get(p_reg);
618 nrf_barrier_r();
619 return amount;
620 }
621
622 #if NRFX_CHECK(NRFY_UARTE_HAS_FRAME_TIMEOUT)
623 /** @refhal{nrf_uarte_frame_timeout_set} */
nrfy_uarte_frame_timeout_set(NRF_UARTE_Type * p_reg,uint32_t timeout)624 NRFY_STATIC_INLINE void nrfy_uarte_frame_timeout_set(NRF_UARTE_Type * p_reg,
625 uint32_t timeout)
626 {
627 nrf_barrier_r();
628 nrf_uarte_frame_timeout_set(p_reg, timeout);
629 nrf_barrier_r();
630 }
631 #endif
632 /** @} */
633
__nrfy_internal_uarte_event_enabled_clear(NRF_UARTE_Type * p_reg,uint32_t mask,nrf_uarte_event_t event)634 NRFY_STATIC_INLINE void __nrfy_internal_uarte_event_enabled_clear(NRF_UARTE_Type * p_reg,
635 uint32_t mask,
636 nrf_uarte_event_t event)
637 {
638 if (mask & NRFY_EVENT_TO_INT_BITMASK(event))
639 {
640 nrf_uarte_event_clear(p_reg, event);
641 }
642 }
643
__nrfy_internal_uarte_event_handle(NRF_UARTE_Type * p_reg,uint32_t mask,nrf_uarte_event_t event,uint32_t * p_evt_mask)644 NRFY_STATIC_INLINE bool __nrfy_internal_uarte_event_handle(NRF_UARTE_Type * p_reg,
645 uint32_t mask,
646 nrf_uarte_event_t event,
647 uint32_t * p_evt_mask)
648 {
649 if ((mask & NRFY_EVENT_TO_INT_BITMASK(event)) && nrf_uarte_event_check(p_reg, event))
650 {
651 nrf_uarte_event_clear(p_reg, event);
652 if (p_evt_mask)
653 {
654 *p_evt_mask |= NRFY_EVENT_TO_INT_BITMASK(event);
655 }
656 return true;
657 }
658 return false;
659 }
660
661 NRFY_STATIC_INLINE
__nrfy_internal_uarte_events_process(NRF_UARTE_Type * p_reg,uint32_t mask,nrfy_uarte_buffer_t const * p_xfer)662 uint32_t __nrfy_internal_uarte_events_process(NRF_UARTE_Type * p_reg,
663 uint32_t mask,
664 nrfy_uarte_buffer_t const * p_xfer)
665 {
666 uint32_t evt_mask = 0;
667
668 nrf_barrier_r();
669 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_CTS, &evt_mask);
670 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_NCTS, &evt_mask);
671 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_RXDRDY, &evt_mask);
672 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_ENDRX, &evt_mask);
673 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_TXDRDY, &evt_mask);
674 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_ENDTX, &evt_mask);
675 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_ERROR, &evt_mask);
676 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_RXTO, &evt_mask);
677 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_RXSTARTED, &evt_mask);
678 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_TXSTARTED, &evt_mask);
679 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_TXSTOPPED, &evt_mask);
680 #if NRFY_UARTE_HAS_FRAME_TIMEOUT
681 (void)__nrfy_internal_uarte_event_handle(p_reg, mask, NRF_UARTE_EVENT_FRAME_TIMEOUT, &evt_mask);
682 #endif
683
684 if (mask & NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_ENDRX))
685 {
686 NRFY_CACHE_INV(p_xfer->p_buffer, p_xfer->length);
687 }
688 else if (mask & NRFY_EVENT_TO_INT_BITMASK(NRF_UARTE_EVENT_RXTO))
689 {
690 size_t size = nrf_uarte_rx_amount_get(p_reg);
691 nrf_barrier_rw();
692 NRFY_CACHE_INV(p_xfer->p_buffer, size);
693 }
694
695 nrf_barrier_w();
696 return evt_mask;
697 }
698
699 #ifdef __cplusplus
700 }
701 #endif
702
703 #endif // NRFY_UARTE_H__
704
