1 /*
2 * Copyright (c) 2023 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRFY_TBM_H__
35 #define NRFY_TBM_H__
36
37 #include <nrfx.h>
38 #include <hal/nrf_tbm.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 NRFY_STATIC_INLINE uint32_t __nrfy_internal_tbm_event_handle(NRF_TBM_Type * p_reg,
45 uint32_t mask,
46 nrf_tbm_event_t event);
47
48 NRFY_STATIC_INLINE void __nrfy_internal_tbm_event_enabled_clear(NRF_TBM_Type * p_reg,
49 uint32_t mask,
50 nrf_tbm_event_t event);
51 /**
52 * @defgroup nrfy_tbm TBM HALY
53 * @{
54 * @ingroup nrf_tbm
55 * @brief Hardware access layer with cache and barrier support
56 * for managing the Trace Buffer Monitor (TBM).
57 */
58
59 /**
60 * @brief Function for configuring the TBM.
61 *
62 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
63 * @param[in] size Buffer size (in 32 bit words).
64 */
nrfy_tbm_configure(NRF_TBM_Type * p_reg,uint32_t size)65 NRFY_STATIC_INLINE void nrfy_tbm_configure(NRF_TBM_Type * p_reg, uint32_t size)
66 {
67 nrf_tbm_buffersize_set(p_reg, size);
68 nrf_barrier_w();
69 }
70
71 /**
72 * @brief Function for initializing the specified TBM interrutps.
73 *
74 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
75 * @param[in] mask Mask of interrupts to be initialized.
76 * @param[in] irq_priority Interrupt priority.
77 * @param[in] enable True if the interrupts are to be enabled, false otherwise.
78 */
nrfy_tbm_int_init(NRF_TBM_Type * p_reg,uint32_t mask,uint8_t irq_priority,bool enable)79 NRFY_STATIC_INLINE void nrfy_tbm_int_init(NRF_TBM_Type * p_reg,
80 uint32_t mask,
81 uint8_t irq_priority,
82 bool enable)
83 {
84 __nrfy_internal_tbm_event_enabled_clear(p_reg, mask, NRF_TBM_EVENT_HALFFULL);
85 __nrfy_internal_tbm_event_enabled_clear(p_reg, mask, NRF_TBM_EVENT_FULL);
86 __nrfy_internal_tbm_event_enabled_clear(p_reg, mask, NRF_TBM_EVENT_FLUSH);
87 nrf_barrier_w();
88
89 NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_reg), irq_priority);
90 NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_reg));
91 if (enable)
92 {
93 nrf_tbm_int_enable(p_reg, mask);
94 }
95 nrf_barrier_w();
96 }
97
98 /**
99 * @brief Function for uninitializing the TBM interrupts.
100 *
101 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
102 */
nrfy_tbm_int_uninit(NRF_TBM_Type * p_reg)103 NRFY_STATIC_INLINE void nrfy_tbm_int_uninit(NRF_TBM_Type * p_reg)
104 {
105 NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_reg));
106 nrf_barrier_w();
107 }
108
109 /**
110 * @brief Function for processing the specified TBM events.
111 *
112 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
113 * @param[in] mask Mask of events to be processed,
114 * created by @ref NRFY_EVENT_TO_INT_BITMASK().
115 *
116 * @return Mask of events that were generated and processed.
117 * To be checked against the result of @ref NRFY_EVENT_TO_INT_BITMASK().
118 */
nrfy_tbm_events_process(NRF_TBM_Type * p_reg,uint32_t mask)119 NRFY_STATIC_INLINE uint32_t nrfy_tbm_events_process(NRF_TBM_Type * p_reg, uint32_t mask)
120 {
121 uint32_t evt_mask;
122
123 nrf_barrier_r();
124
125 evt_mask = __nrfy_internal_tbm_event_handle(p_reg, mask, NRF_TBM_EVENT_HALFFULL);
126 evt_mask |= __nrfy_internal_tbm_event_handle(p_reg, mask, NRF_TBM_EVENT_FULL);
127 evt_mask |= __nrfy_internal_tbm_event_handle(p_reg, mask, NRF_TBM_EVENT_FLUSH);
128
129 nrf_barrier_w();
130 return evt_mask;
131 }
132
133 /** @refhal{nrf_tbm_count_get} */
nrfy_tbm_count_get(NRF_TBM_Type * p_reg)134 NRFY_STATIC_INLINE uint32_t nrfy_tbm_count_get(NRF_TBM_Type * p_reg)
135 {
136 nrf_barrier_r();
137 return nrf_tbm_count_get(p_reg);
138 }
139
140 /** @refhal{nrf_tbm_task_trigger} */
nrfy_tbm_task_trigger(NRF_TBM_Type * p_reg,nrf_tbm_task_t task)141 NRFY_STATIC_INLINE void nrfy_tbm_task_trigger(NRF_TBM_Type * p_reg, nrf_tbm_task_t task)
142 {
143 nrf_tbm_task_trigger(p_reg, task);
144 nrf_barrier_w();
145 }
146
147 /** @refhal{nrf_tbm_event_clear} */
nrfy_tbm_event_clear(NRF_TBM_Type * p_reg,nrf_tbm_event_t event)148 NRFY_STATIC_INLINE void nrfy_tbm_event_clear(NRF_TBM_Type * p_reg,
149 nrf_tbm_event_t event)
150 {
151 nrf_tbm_event_clear(p_reg, event);
152 nrf_barrier_w();
153 }
154
155 /** @refhal{nrf_tbm_event_check} */
nrfy_tbm_event_check(NRF_TBM_Type const * p_reg,nrf_tbm_event_t event)156 NRFY_STATIC_INLINE bool nrfy_tbm_event_check(NRF_TBM_Type const * p_reg,
157 nrf_tbm_event_t event)
158 {
159 nrf_barrier_r();
160 bool check = nrf_tbm_event_check(p_reg, event);
161 nrf_barrier_r();
162 return check;
163 }
164
165 /** @refhal{nrf_tbm_int_enable} */
nrfy_tbm_int_enable(NRF_TBM_Type * p_reg,uint32_t mask)166 NRFY_STATIC_INLINE void nrfy_tbm_int_enable(NRF_TBM_Type * p_reg, uint32_t mask)
167 {
168 nrf_tbm_int_enable(p_reg, mask);
169 nrf_barrier_w();
170 }
171
172 /** @refhal{nrf_tbm_int_disable} */
nrfy_tbm_int_disable(NRF_TBM_Type * p_reg,uint32_t mask)173 NRFY_STATIC_INLINE void nrfy_tbm_int_disable(NRF_TBM_Type * p_reg, uint32_t mask)
174 {
175 nrf_tbm_int_disable(p_reg, mask);
176 nrf_barrier_w();
177 }
178
179 /** @refhal{nrf_tbm_int_enable_check} */
nrfy_tbm_int_enable_check(NRF_TBM_Type const * p_reg,uint32_t mask)180 NRFY_STATIC_INLINE uint32_t nrfy_tbm_int_enable_check(NRF_TBM_Type const * p_reg, uint32_t mask)
181 {
182 nrf_barrier_rw();
183 uint32_t check = nrf_tbm_int_enable_check(p_reg, mask);
184 nrf_barrier_r();
185 return check;
186 }
187
188 /** @} */
189
__nrfy_internal_tbm_event_handle(NRF_TBM_Type * p_reg,uint32_t mask,nrf_tbm_event_t event)190 NRFY_STATIC_INLINE uint32_t __nrfy_internal_tbm_event_handle(NRF_TBM_Type * p_reg,
191 uint32_t mask,
192 nrf_tbm_event_t event)
193 {
194 if ((mask & NRFY_EVENT_TO_INT_BITMASK(event)) && nrf_tbm_event_check(p_reg, event))
195 {
196 nrf_tbm_event_clear(p_reg, event);
197 return NRFY_EVENT_TO_INT_BITMASK(event);
198 }
199 return 0;
200 }
201
__nrfy_internal_tbm_event_enabled_clear(NRF_TBM_Type * p_reg,uint32_t mask,nrf_tbm_event_t event)202 NRFY_STATIC_INLINE void __nrfy_internal_tbm_event_enabled_clear(NRF_TBM_Type * p_reg,
203 uint32_t mask,
204 nrf_tbm_event_t event)
205 {
206 if (mask & NRFY_EVENT_TO_INT_BITMASK(event))
207 {
208 nrf_tbm_event_clear(p_reg, event);
209 }
210 }
211
212 #ifdef __cplusplus
213 }
214 #endif
215
216 #endif // NRFY_TBM_H__
217
