1 /*
2 * Copyright (c) 2021 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRFY_SAADC_H__
35 #define NRFY_SAADC_H__
36
37 #include <nrfx.h>
38 #include <hal/nrf_saadc.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 typedef struct nrfy_saadc_buffer_t nrfy_saadc_buffer_t;
45
46 NRFY_STATIC_INLINE bool __nrfy_internal_saadc_event_handle(NRF_SAADC_Type * p_reg,
47 uint32_t mask,
48 nrf_saadc_event_t event,
49 uint32_t * p_event_mask);
50
51 NRFY_STATIC_INLINE
52 uint32_t __nrfy_internal_saadc_events_process(NRF_SAADC_Type * p_reg,
53 uint32_t mask,
54 nrfy_saadc_buffer_t const * p_desc);
55
56 NRFY_STATIC_INLINE void __nrfy_internal_saadc_event_enabled_clear(NRF_SAADC_Type * p_reg,
57 uint32_t mask,
58 nrf_saadc_event_t event);
59
60 NRFY_STATIC_INLINE void __nrfy_internal_saadc_buffer_latch(NRF_SAADC_Type * p_reg, bool wait);
61
62 NRFY_STATIC_INLINE void __nrfy_internal_saadc_stop(NRF_SAADC_Type * p_reg, bool wait);
63
64 /**
65 * @defgroup nrfy_saadc SAADC HALY
66 * @{
67 * @ingroup nrf_saadc
68 * @brief Hardware access layer with cache and barrier support for managing the SAADC peripheral.
69 */
70
71 /** @brief Structure describing SAADC sampling buffer. */
72 struct nrfy_saadc_buffer_t
73 {
74 nrf_saadc_value_t * p_buffer; ///< Pointer to the sampling buffer.
75 size_t length; ///< Sampling buffer length.
76 };
77
78 /** @brief SAADC configuration structure. */
79 typedef struct
80 {
81 nrf_saadc_resolution_t resolution; ///< Sampling resolution.
82 nrf_saadc_oversample_t oversampling; ///< Oversampling setting.
83 } nrfy_saadc_config_t;
84
85 /** @brief SAADC channel input configuration structure. */
86 typedef struct
87 {
88 nrf_saadc_input_t input_p; ///< Positive input.
89 nrf_saadc_input_t input_n; ///< Negative input.
90 } nrfy_saadc_channel_input_t;
91
92 /**
93 * @brief Function for configuring the SAADC.
94 *
95 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
96 * @param[in] p_config Pointer to the peripheral configuration structure.
97 */
nrfy_saadc_periph_configure(NRF_SAADC_Type * p_reg,nrfy_saadc_config_t const * p_config)98 NRFY_STATIC_INLINE void nrfy_saadc_periph_configure(NRF_SAADC_Type * p_reg,
99 nrfy_saadc_config_t const * p_config)
100 {
101 nrf_saadc_resolution_set(p_reg, p_config->resolution);
102 nrf_saadc_oversample_set(p_reg, p_config->oversampling);
103 nrf_barrier_w();
104 }
105
106 /**
107 * @brief Function for initializing the specified SAADC interrupts.
108 *
109 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
110 * @param[in] mask Mask of interrupts to be initialized.
111 * @param[in] irq_priority Interrupt priority.
112 * @param[in] enable True if the interrupts are to be enabled, false otherwise.
113 */
nrfy_saadc_int_init(NRF_SAADC_Type * p_reg,uint32_t mask,uint8_t irq_priority,bool enable)114 NRFY_STATIC_INLINE void nrfy_saadc_int_init(NRF_SAADC_Type * p_reg,
115 uint32_t mask,
116 uint8_t irq_priority,
117 bool enable)
118 {
119 __nrfy_internal_saadc_event_enabled_clear(p_reg, mask, NRF_SAADC_EVENT_STARTED);
120 __nrfy_internal_saadc_event_enabled_clear(p_reg, mask, NRF_SAADC_EVENT_END);
121 __nrfy_internal_saadc_event_enabled_clear(p_reg, mask, NRF_SAADC_EVENT_DONE);
122 __nrfy_internal_saadc_event_enabled_clear(p_reg, mask, NRF_SAADC_EVENT_RESULTDONE);
123 __nrfy_internal_saadc_event_enabled_clear(p_reg, mask, NRF_SAADC_EVENT_CALIBRATEDONE);
124 __nrfy_internal_saadc_event_enabled_clear(p_reg, mask, NRF_SAADC_EVENT_STOPPED);
125
126 for (uint32_t i = 0; i < SAADC_CH_NUM; i++)
127 {
128 nrf_saadc_event_t event = nrf_saadc_limit_event_get(i, NRF_SAADC_LIMIT_LOW);
129 __nrfy_internal_saadc_event_enabled_clear(p_reg, mask, event);
130
131 event = nrf_saadc_limit_event_get(i, NRF_SAADC_LIMIT_HIGH);
132 __nrfy_internal_saadc_event_enabled_clear(p_reg, mask, event);
133 }
134
135 nrf_barrier_w();
136
137 NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_reg), irq_priority);
138 NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_reg));
139 if (enable)
140 {
141 nrf_saadc_int_enable(p_reg, mask);
142 }
143
144 nrf_barrier_w();
145 }
146
147 /**
148 * @brief Function for uninitializing the SAADC interrupts.
149 *
150 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
151 */
nrfy_saadc_int_uninit(NRF_SAADC_Type * p_reg)152 NRFY_STATIC_INLINE void nrfy_saadc_int_uninit(NRF_SAADC_Type * p_reg)
153 {
154 NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_reg));
155 nrf_barrier_w();
156 }
157
158 /**
159 * @brief Function for processing the specified SAADC events.
160 *
161 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
162 * @param[in] mask Mask of events to be processed, created by @ref NRFY_EVENT_TO_INT_BITMASK().
163 * @param[in] p_desc Pointer to the structure containing buffer associated with the last sampling.
164 * Can be NULL.
165 *
166 * @return Mask of events that were generated and processed.
167 * To be checked against the result of @ref NRFY_EVENT_TO_INT_BITMASK().
168 */
nrfy_saadc_events_process(NRF_SAADC_Type * p_reg,uint32_t mask,nrfy_saadc_buffer_t const * p_desc)169 NRFY_STATIC_INLINE uint32_t nrfy_saadc_events_process(NRF_SAADC_Type * p_reg,
170 uint32_t mask,
171 nrfy_saadc_buffer_t const * p_desc)
172 {
173 uint32_t evt_mask = __nrfy_internal_saadc_events_process(p_reg, mask, p_desc);
174 nrf_barrier_w();
175 return evt_mask;
176 }
177
178 /**
179 * @brief Function for configuring the specified SAADC channel.
180 *
181 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
182 * @param[in] channel Channel number.
183 * @param[in] p_config Pointer to the channel configuration structure.
184 * NULL if configuration is to be omitted.
185 * @param[in] p_input Pointer to the channel input configuration structure.
186 * NULL if configuration is to be omitted.
187 */
nrfy_saadc_channel_configure(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_channel_config_t const * p_config,nrfy_saadc_channel_input_t const * p_input)188 NRFY_STATIC_INLINE void nrfy_saadc_channel_configure(NRF_SAADC_Type * p_reg,
189 uint8_t channel,
190 nrf_saadc_channel_config_t const * p_config,
191 nrfy_saadc_channel_input_t const * p_input)
192 {
193 if (p_config)
194 {
195 nrf_saadc_channel_init(p_reg, channel, p_config);
196 }
197 if (p_input)
198 {
199 nrf_saadc_channel_input_set(p_reg, channel, p_input->input_p, p_input->input_n);
200 }
201 nrf_barrier_w();
202 }
203
204 /**
205 * @brief Function for setting the SAADC sampling buffer.
206 *
207 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
208 * @param[in] p_desc Pointer to the structure containing sampling buffer description.
209 * @param[in] latch True if buffer is to be latched, false otherwise.
210 * @param[in] wait True if latching is to be blocking, false otherwise.
211 */
nrfy_saadc_buffer_set(NRF_SAADC_Type * p_reg,nrfy_saadc_buffer_t const * p_desc,bool latch,bool wait)212 NRFY_STATIC_INLINE void nrfy_saadc_buffer_set(NRF_SAADC_Type * p_reg,
213 nrfy_saadc_buffer_t const * p_desc,
214 bool latch,
215 bool wait)
216 {
217 nrf_saadc_buffer_init(p_reg, p_desc->p_buffer, p_desc->length);
218 nrf_barrier_w();
219 if (latch)
220 {
221 __nrfy_internal_saadc_buffer_latch(p_reg, wait);
222 }
223 }
224
225 /**
226 * @brief Function for latching the SAADC sampling buffer.
227 *
228 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
229 * @param[in] wait True if latching is to be blocking, false otherwise.
230 */
nrfy_saadc_buffer_latch(NRF_SAADC_Type * p_reg,bool wait)231 NRFY_STATIC_INLINE void nrfy_saadc_buffer_latch(NRF_SAADC_Type * p_reg, bool wait)
232 {
233 __nrfy_internal_saadc_buffer_latch(p_reg, wait);
234 }
235
236 /**
237 * @brief Function for starting the SAADC sampling.
238 *
239 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
240 * @param[in] p_desc Pointer to the structure containing sampling buffer
241 * if the sampling is to be blocking. NULL for non-blocking operation.
242 */
nrfy_saadc_sample_start(NRF_SAADC_Type * p_reg,nrfy_saadc_buffer_t const * p_desc)243 NRFY_STATIC_INLINE void nrfy_saadc_sample_start(NRF_SAADC_Type * p_reg,
244 nrfy_saadc_buffer_t const * p_desc)
245 {
246 nrf_saadc_task_trigger(p_reg, NRF_SAADC_TASK_SAMPLE);
247 if (p_desc)
248 {
249 nrf_barrier_w();
250 uint32_t evt_mask = NRFY_EVENT_TO_INT_BITMASK(NRF_SAADC_EVENT_END);
251 while (!__nrfy_internal_saadc_events_process(p_reg, evt_mask, p_desc))
252 {}
253 nrf_saadc_event_clear(p_reg, NRF_SAADC_EVENT_DONE);
254 nrf_saadc_event_clear(p_reg, NRF_SAADC_EVENT_RESULTDONE);
255 }
256 nrf_barrier_w();
257 }
258
259 /**
260 * @brief Function for aborting the ongoing SAADC sampling.
261 *
262 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
263 * @param[in] p_desc Pointer to the structure containing sampling buffer
264 * if the abort is to be blocking. NULL for non-blocking operation.
265 */
nrfy_saadc_abort(NRF_SAADC_Type * p_reg,nrfy_saadc_buffer_t const * p_desc)266 NRFY_STATIC_INLINE void nrfy_saadc_abort(NRF_SAADC_Type * p_reg,
267 nrfy_saadc_buffer_t const * p_desc)
268 {
269 __nrfy_internal_saadc_stop(p_reg, p_desc ? true : false);
270 if (p_desc)
271 {
272 (void)__nrfy_internal_saadc_events_process(p_reg,
273 NRFY_EVENT_TO_INT_BITMASK(NRF_SAADC_EVENT_END),
274 p_desc);
275 }
276 nrf_barrier_w();
277 }
278
279 /**
280 * @brief Function for stopping the SAADC.
281 *
282 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
283 * @param[in] wait True if stopping is to be blocking, false otherwise.
284 */
nrfy_saadc_stop(NRF_SAADC_Type * p_reg,bool wait)285 NRFY_STATIC_INLINE void nrfy_saadc_stop(NRF_SAADC_Type * p_reg, bool wait)
286 {
287 __nrfy_internal_saadc_stop(p_reg, wait);
288 nrf_barrier_w();
289 }
290
291 /**
292 * @brief Function for calibrating the SAADC.
293 *
294 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
295 * @param[in] wait True if calibration is to be blocking, false otherwise.
296 */
nrfy_saadc_calibrate(NRF_SAADC_Type * p_reg,bool wait)297 NRFY_STATIC_INLINE void nrfy_saadc_calibrate(NRF_SAADC_Type * p_reg, bool wait)
298 {
299 nrf_saadc_task_trigger(p_reg, NRF_SAADC_TASK_CALIBRATEOFFSET);
300 if (wait)
301 {
302 nrf_barrier_w();
303 uint32_t evt_mask = NRFY_EVENT_TO_INT_BITMASK(NRF_SAADC_EVENT_CALIBRATEDONE);
304 while (!__nrfy_internal_saadc_events_process(p_reg, evt_mask, NULL))
305 {}
306 nrf_saadc_event_clear(p_reg, NRF_SAADC_EVENT_END);
307 }
308 nrf_barrier_w();
309 }
310
311 /** @refhal{nrf_saadc_task_trigger} */
nrfy_saadc_task_trigger(NRF_SAADC_Type * p_reg,nrf_saadc_task_t task)312 NRFY_STATIC_INLINE void nrfy_saadc_task_trigger(NRF_SAADC_Type * p_reg, nrf_saadc_task_t task)
313 {
314 nrf_saadc_task_trigger(p_reg, task);
315 nrf_barrier_w();
316 }
317
318 /** @refhal{nrf_saadc_task_address_get} */
nrfy_saadc_task_address_get(NRF_SAADC_Type const * p_reg,nrf_saadc_task_t task)319 NRFY_STATIC_INLINE uint32_t nrfy_saadc_task_address_get(NRF_SAADC_Type const * p_reg,
320 nrf_saadc_task_t task)
321 {
322 return nrf_saadc_task_address_get(p_reg, task);
323 }
324
325 /** @refhal{nrf_saadc_event_check} */
nrfy_saadc_event_check(NRF_SAADC_Type const * p_reg,nrf_saadc_event_t event)326 NRFY_STATIC_INLINE bool nrfy_saadc_event_check(NRF_SAADC_Type const * p_reg,
327 nrf_saadc_event_t event)
328 {
329 nrf_barrier_r();
330 bool check = nrf_saadc_event_check(p_reg, event);
331 nrf_barrier_r();
332 return check;
333 }
334
335 /** @refhal{nrf_saadc_event_clear} */
nrfy_saadc_event_clear(NRF_SAADC_Type * p_reg,nrf_saadc_event_t event)336 NRFY_STATIC_INLINE void nrfy_saadc_event_clear(NRF_SAADC_Type * p_reg, nrf_saadc_event_t event)
337 {
338 nrf_saadc_event_clear(p_reg, event);
339 nrf_barrier_w();
340 }
341
342 /** @refhal{nrf_saadc_event_address_get} */
nrfy_saadc_event_address_get(NRF_SAADC_Type const * p_reg,nrf_saadc_event_t event)343 NRFY_STATIC_INLINE uint32_t nrfy_saadc_event_address_get(NRF_SAADC_Type const * p_reg,
344 nrf_saadc_event_t event)
345 {
346 return nrf_saadc_event_address_get(p_reg, event);
347 }
348
349 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
350 /** @refhal{nrf_saadc_subscribe_set} */
nrfy_saadc_subscribe_set(NRF_SAADC_Type * p_reg,nrf_saadc_task_t task,uint8_t channel)351 NRFY_STATIC_INLINE void nrfy_saadc_subscribe_set(NRF_SAADC_Type * p_reg,
352 nrf_saadc_task_t task,
353 uint8_t channel)
354 {
355 nrf_saadc_subscribe_set(p_reg, task, channel);
356 nrf_barrier_w();
357 }
358
359 /** @refhal{nrf_saadc_subscribe_clear} */
nrfy_saadc_subscribe_clear(NRF_SAADC_Type * p_reg,nrf_saadc_task_t task)360 NRFY_STATIC_INLINE void nrfy_saadc_subscribe_clear(NRF_SAADC_Type * p_reg, nrf_saadc_task_t task)
361 {
362 nrf_saadc_subscribe_clear(p_reg, task);
363 nrf_barrier_w();
364 }
365
366 /** @refhal{nrf_saadc_publish_set} */
nrfy_saadc_publish_set(NRF_SAADC_Type * p_reg,nrf_saadc_event_t event,uint8_t channel)367 NRFY_STATIC_INLINE void nrfy_saadc_publish_set(NRF_SAADC_Type * p_reg,
368 nrf_saadc_event_t event,
369 uint8_t channel)
370 {
371 nrf_saadc_publish_set(p_reg, event, channel);
372 nrf_barrier_w();
373 }
374
375 /** @refhal{nrf_saadc_publish_clear} */
nrfy_saadc_publish_clear(NRF_SAADC_Type * p_reg,nrf_saadc_event_t event)376 NRFY_STATIC_INLINE void nrfy_saadc_publish_clear(NRF_SAADC_Type * p_reg, nrf_saadc_event_t event)
377 {
378 nrf_saadc_publish_clear(p_reg, event);
379 nrf_barrier_w();
380 }
381 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
382
383 /** @refhal{nrf_saadc_limit_event_get} */
nrfy_saadc_limit_event_get(uint8_t channel,nrf_saadc_limit_t limit_type)384 NRFY_STATIC_INLINE nrf_saadc_event_t nrfy_saadc_limit_event_get(uint8_t channel,
385 nrf_saadc_limit_t limit_type)
386 {
387 return nrf_saadc_limit_event_get(channel, limit_type);
388 }
389
390 /** @refhal{nrf_saadc_channel_input_set} */
nrfy_saadc_channel_input_set(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_input_t pselp,nrf_saadc_input_t pseln)391 NRFY_STATIC_INLINE void nrfy_saadc_channel_input_set(NRF_SAADC_Type * p_reg,
392 uint8_t channel,
393 nrf_saadc_input_t pselp,
394 nrf_saadc_input_t pseln)
395 {
396 nrf_saadc_channel_input_set(p_reg, channel, pselp, pseln);
397 nrf_barrier_w();
398 }
399
400 /** @refhal{nrf_saadc_channel_pos_input_set} */
nrfy_saadc_channel_pos_input_set(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_input_t pselp)401 NRFY_STATIC_INLINE void nrfy_saadc_channel_pos_input_set(NRF_SAADC_Type * p_reg,
402 uint8_t channel,
403 nrf_saadc_input_t pselp)
404 {
405 nrf_saadc_channel_pos_input_set(p_reg, channel, pselp);
406 nrf_barrier_w();
407 }
408
409 /** @refhal{nrf_saadc_channel_limits_set} */
nrfy_saadc_channel_limits_set(NRF_SAADC_Type * p_reg,uint8_t channel,int16_t low,int16_t high)410 NRFY_STATIC_INLINE void nrfy_saadc_channel_limits_set(NRF_SAADC_Type * p_reg,
411 uint8_t channel,
412 int16_t low,
413 int16_t high)
414 {
415 nrf_saadc_channel_limits_set(p_reg, channel, low, high);
416 nrf_barrier_w();
417 }
418
419 /** @refhal{nrf_saadc_int_set} */
nrfy_saadc_int_set(NRF_SAADC_Type * p_reg,uint32_t mask)420 NRFY_STATIC_INLINE void nrfy_saadc_int_set(NRF_SAADC_Type * p_reg, uint32_t mask)
421 {
422 nrf_saadc_int_set(p_reg, mask);
423 nrf_barrier_w();
424 }
425
426 /** @refhal{nrf_saadc_int_enable} */
nrfy_saadc_int_enable(NRF_SAADC_Type * p_reg,uint32_t mask)427 NRFY_STATIC_INLINE void nrfy_saadc_int_enable(NRF_SAADC_Type * p_reg, uint32_t mask)
428 {
429 nrf_saadc_int_enable(p_reg, mask);
430 nrf_barrier_w();
431 }
432
433 /** @refhal{nrf_saadc_int_enable_check} */
nrfy_saadc_int_enable_check(NRF_SAADC_Type const * p_reg,uint32_t mask)434 NRFY_STATIC_INLINE uint32_t nrfy_saadc_int_enable_check(NRF_SAADC_Type const * p_reg, uint32_t mask)
435 {
436 nrf_barrier_rw();
437 uint32_t check = nrf_saadc_int_enable_check(p_reg, mask);
438 nrf_barrier_r();
439 return check;
440 }
441
442 /** @refhal{nrf_saadc_int_disable} */
nrfy_saadc_int_disable(NRF_SAADC_Type * p_reg,uint32_t mask)443 NRFY_STATIC_INLINE void nrfy_saadc_int_disable(NRF_SAADC_Type * p_reg, uint32_t mask)
444 {
445 nrf_saadc_int_disable(p_reg, mask);
446 nrf_barrier_w();
447 }
448
449 /** @refhal{nrf_saadc_limit_int_get} */
nrfy_saadc_limit_int_get(uint8_t channel,nrf_saadc_limit_t limit_type)450 NRFY_STATIC_INLINE uint32_t nrfy_saadc_limit_int_get(uint8_t channel,
451 nrf_saadc_limit_t limit_type)
452 {
453 return nrf_saadc_limit_int_get(channel, limit_type);
454 }
455
456 /** @refhal{nrf_saadc_busy_check} */
nrfy_saadc_busy_check(NRF_SAADC_Type const * p_reg)457 NRFY_STATIC_INLINE bool nrfy_saadc_busy_check(NRF_SAADC_Type const * p_reg)
458 {
459 nrf_barrier_r();
460 bool check = nrf_saadc_busy_check(p_reg);
461 nrf_barrier_r();
462 return check;
463 }
464
465 /** @refhal{nrf_saadc_enable} */
nrfy_saadc_enable(NRF_SAADC_Type * p_reg)466 NRFY_STATIC_INLINE void nrfy_saadc_enable(NRF_SAADC_Type * p_reg)
467 {
468 nrf_saadc_enable(p_reg);
469 nrf_barrier_w();
470 }
471
472 /** @refhal{nrf_saadc_disable} */
nrfy_saadc_disable(NRF_SAADC_Type * p_reg)473 NRFY_STATIC_INLINE void nrfy_saadc_disable(NRF_SAADC_Type * p_reg)
474 {
475 nrf_saadc_disable(p_reg);
476 nrf_barrier_w();
477 }
478
479 /** @refhal{nrf_saadc_enable_check} */
nrfy_saadc_enable_check(NRF_SAADC_Type const * p_reg)480 NRFY_STATIC_INLINE bool nrfy_saadc_enable_check(NRF_SAADC_Type const * p_reg)
481 {
482 nrf_barrier_rw();
483 bool check = nrf_saadc_enable_check(p_reg);
484 nrf_barrier_r();
485 return check;
486 }
487
488 /** @refhal{nrf_saadc_buffer_init} */
nrfy_saadc_buffer_init(NRF_SAADC_Type * p_reg,nrf_saadc_value_t * p_buffer,uint32_t size)489 NRFY_STATIC_INLINE void nrfy_saadc_buffer_init(NRF_SAADC_Type * p_reg,
490 nrf_saadc_value_t * p_buffer,
491 uint32_t size)
492 {
493 nrf_saadc_buffer_init(p_reg, p_buffer, size);
494 nrf_barrier_w();
495 }
496
497 /** @refhal{nrf_saadc_buffer_pointer_set} */
nrfy_saadc_buffer_pointer_set(NRF_SAADC_Type * p_reg,nrf_saadc_value_t * p_buffer)498 NRFY_STATIC_INLINE void nrfy_saadc_buffer_pointer_set(NRF_SAADC_Type * p_reg,
499 nrf_saadc_value_t * p_buffer)
500 {
501 nrf_saadc_buffer_pointer_set(p_reg, p_buffer);
502 nrf_barrier_w();
503 }
504
505 /** @refhal{nrf_saadc_buffer_pointer_get} */
nrfy_saadc_buffer_pointer_get(NRF_SAADC_Type const * p_reg)506 NRFY_STATIC_INLINE nrf_saadc_value_t * nrfy_saadc_buffer_pointer_get(NRF_SAADC_Type const * p_reg)
507 {
508 nrf_barrier_rw();
509 nrf_saadc_value_t * p_buffer = nrf_saadc_buffer_pointer_get(p_reg);
510 nrf_barrier_r();
511 return p_buffer;
512 }
513
514 /** @refhal{nrf_saadc_amount_get} */
nrfy_saadc_amount_get(NRF_SAADC_Type const * p_reg)515 NRFY_STATIC_INLINE uint16_t nrfy_saadc_amount_get(NRF_SAADC_Type const * p_reg)
516 {
517 nrf_barrier_r();
518 uint16_t amount = nrf_saadc_amount_get(p_reg);
519 nrf_barrier_r();
520 return amount;
521 }
522
523 /** @refhal{nrf_saadc_resolution_set} */
nrfy_saadc_resolution_set(NRF_SAADC_Type * p_reg,nrf_saadc_resolution_t resolution)524 NRFY_STATIC_INLINE void nrfy_saadc_resolution_set(NRF_SAADC_Type * p_reg,
525 nrf_saadc_resolution_t resolution)
526 {
527 nrf_saadc_resolution_set(p_reg, resolution);
528 nrf_barrier_w();
529 }
530
531 /** @refhal{nrf_saadc_resolution_get} */
nrfy_saadc_resolution_get(NRF_SAADC_Type const * p_reg)532 NRFY_STATIC_INLINE nrf_saadc_resolution_t nrfy_saadc_resolution_get(NRF_SAADC_Type const * p_reg)
533 {
534 nrf_barrier_rw();
535 nrf_saadc_resolution_t resolution = nrf_saadc_resolution_get(p_reg);
536 nrf_barrier_r();
537 return resolution;
538 }
539
540 /** @refhal{nrf_saadc_oversample_set} */
nrfy_saadc_oversample_set(NRF_SAADC_Type * p_reg,nrf_saadc_oversample_t oversample)541 NRFY_STATIC_INLINE void nrfy_saadc_oversample_set(NRF_SAADC_Type * p_reg,
542 nrf_saadc_oversample_t oversample)
543 {
544 nrf_saadc_oversample_set(p_reg, oversample);
545 nrf_barrier_w();
546 }
547
548 /** @refhal{nrf_saadc_oversample_get} */
nrfy_saadc_oversample_get(NRF_SAADC_Type const * p_reg)549 NRFY_STATIC_INLINE nrf_saadc_oversample_t nrfy_saadc_oversample_get(NRF_SAADC_Type const * p_reg)
550 {
551 nrf_barrier_rw();
552 nrf_saadc_oversample_t oversample = nrf_saadc_oversample_get(p_reg);
553 nrf_barrier_r();
554 return oversample;
555 }
556
557 /** @refhal{nrf_saadc_oversample_sample_count_get} */
558 NRFY_STATIC_INLINE
nrfy_saadc_oversample_sample_count_get(nrf_saadc_oversample_t oversample)559 uint32_t nrfy_saadc_oversample_sample_count_get(nrf_saadc_oversample_t oversample)
560 {
561 return nrf_saadc_oversample_sample_count_get(oversample);
562 }
563
564 /** @refhal{nrf_saadc_continuous_mode_enable} */
nrfy_saadc_continuous_mode_enable(NRF_SAADC_Type * p_reg,uint16_t cc)565 NRFY_STATIC_INLINE void nrfy_saadc_continuous_mode_enable(NRF_SAADC_Type * p_reg, uint16_t cc)
566 {
567 nrf_saadc_continuous_mode_enable(p_reg, cc);
568 nrf_barrier_w();
569 }
570
571 /** @refhal{nrf_saadc_continuous_mode_enable_check} */
nrfy_saadc_continuous_mode_enable_check(NRF_SAADC_Type const * p_reg)572 NRFY_STATIC_INLINE bool nrfy_saadc_continuous_mode_enable_check(NRF_SAADC_Type const * p_reg)
573 {
574 nrf_barrier_rw();
575 bool check = nrf_saadc_continuous_mode_enable_check(p_reg);
576 nrf_barrier_r();
577 return check;
578 }
579
580 /** @refhal{nrf_saadc_continuous_mode_disable} */
nrfy_saadc_continuous_mode_disable(NRF_SAADC_Type * p_reg)581 NRFY_STATIC_INLINE void nrfy_saadc_continuous_mode_disable(NRF_SAADC_Type * p_reg)
582 {
583 nrf_saadc_continuous_mode_disable(p_reg);
584 nrf_barrier_w();
585 }
586
587 /** @refhal{nrf_saadc_channel_init} */
nrfy_saadc_channel_init(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_channel_config_t const * config)588 NRFY_STATIC_INLINE void nrfy_saadc_channel_init(NRF_SAADC_Type * p_reg,
589 uint8_t channel,
590 nrf_saadc_channel_config_t const * config)
591 {
592 nrf_saadc_channel_init(p_reg, channel, config);
593 nrf_barrier_w();
594 }
595
596 /** @refhal{nrf_saadc_burst_set} */
nrfy_saadc_burst_set(NRF_SAADC_Type * p_reg,uint8_t channel,nrf_saadc_burst_t burst)597 NRFY_STATIC_INLINE void nrfy_saadc_burst_set(NRF_SAADC_Type * p_reg,
598 uint8_t channel,
599 nrf_saadc_burst_t burst)
600 {
601 nrf_saadc_burst_set(p_reg, channel, burst);
602 nrf_barrier_w();
603 }
604
605 /** @refhal{nrf_saadc_value_min_get} */
nrfy_saadc_value_min_get(nrf_saadc_resolution_t resolution)606 NRFY_STATIC_INLINE nrf_saadc_value_t nrfy_saadc_value_min_get(nrf_saadc_resolution_t resolution)
607 {
608 return nrf_saadc_value_min_get(resolution);
609 }
610
611 /** @refhal{nrf_saadc_value_max_get} */
nrfy_saadc_value_max_get(nrf_saadc_resolution_t resolution)612 NRFY_STATIC_INLINE nrf_saadc_value_t nrfy_saadc_value_max_get(nrf_saadc_resolution_t resolution)
613 {
614 return nrf_saadc_value_max_get(resolution);
615 }
616
617 /** @} */
618
__nrfy_internal_saadc_event_handle(NRF_SAADC_Type * p_reg,uint32_t mask,nrf_saadc_event_t event,uint32_t * p_event_mask)619 NRFY_STATIC_INLINE bool __nrfy_internal_saadc_event_handle(NRF_SAADC_Type * p_reg,
620 uint32_t mask,
621 nrf_saadc_event_t event,
622 uint32_t * p_event_mask)
623 {
624 if ((mask & NRFY_EVENT_TO_INT_BITMASK(event)) && nrf_saadc_event_check(p_reg, event))
625 {
626 nrf_saadc_event_clear(p_reg, event);
627 if (p_event_mask)
628 {
629 *p_event_mask |= NRFY_EVENT_TO_INT_BITMASK(event);
630 }
631 return true;
632 }
633 return false;
634 }
635
636 NRFY_STATIC_INLINE
__nrfy_internal_saadc_events_process(NRF_SAADC_Type * p_reg,uint32_t mask,nrfy_saadc_buffer_t const * p_desc)637 uint32_t __nrfy_internal_saadc_events_process(NRF_SAADC_Type * p_reg,
638 uint32_t mask,
639 nrfy_saadc_buffer_t const * p_desc)
640 {
641 uint32_t evt_mask = 0;
642
643 nrf_barrier_r();
644
645 (void)__nrfy_internal_saadc_event_handle(p_reg, mask, NRF_SAADC_EVENT_STARTED, &evt_mask);
646 bool stop = __nrfy_internal_saadc_event_handle(p_reg, mask, NRF_SAADC_EVENT_STOPPED, &evt_mask);
647
648 if (__nrfy_internal_saadc_event_handle(p_reg, mask, NRF_SAADC_EVENT_END, &evt_mask) && p_desc)
649 {
650 size_t size = stop ? nrf_saadc_amount_get(p_reg) : p_desc->length;
651 NRFY_CACHE_INV(p_desc->p_buffer, size);
652 }
653
654 (void)__nrfy_internal_saadc_event_handle(p_reg, mask, NRF_SAADC_EVENT_DONE, &evt_mask);
655 (void)__nrfy_internal_saadc_event_handle(p_reg, mask, NRF_SAADC_EVENT_RESULTDONE, &evt_mask);
656 (void)__nrfy_internal_saadc_event_handle(p_reg, mask, NRF_SAADC_EVENT_CALIBRATEDONE, &evt_mask);
657
658 if (mask & NRF_SAADC_ALL_CHANNELS_LIMITS_INT_MASK)
659 {
660 for (uint32_t i = 0; i < SAADC_CH_NUM; i++)
661 {
662 nrf_saadc_event_t event = nrf_saadc_limit_event_get(i, NRF_SAADC_LIMIT_LOW);
663 __nrfy_internal_saadc_event_handle(p_reg, mask, event, &evt_mask);
664
665 event = nrf_saadc_limit_event_get(i, NRF_SAADC_LIMIT_HIGH);
666 __nrfy_internal_saadc_event_handle(p_reg, mask, event, &evt_mask);
667 }
668 }
669
670 return evt_mask;
671 }
672
__nrfy_internal_saadc_event_enabled_clear(NRF_SAADC_Type * p_reg,uint32_t mask,nrf_saadc_event_t event)673 NRFY_STATIC_INLINE void __nrfy_internal_saadc_event_enabled_clear(NRF_SAADC_Type * p_reg,
674 uint32_t mask,
675 nrf_saadc_event_t event)
676 {
677 if (mask & NRFY_EVENT_TO_INT_BITMASK(event))
678 {
679 nrf_saadc_event_clear(p_reg, event);
680 }
681 }
682
__nrfy_internal_saadc_buffer_latch(NRF_SAADC_Type * p_reg,bool wait)683 NRFY_STATIC_INLINE void __nrfy_internal_saadc_buffer_latch(NRF_SAADC_Type * p_reg, bool wait)
684 {
685 nrf_saadc_task_trigger(p_reg, NRF_SAADC_TASK_START);
686 if (wait)
687 {
688 nrf_barrier_w();
689 uint32_t evt_mask = NRFY_EVENT_TO_INT_BITMASK(NRF_SAADC_EVENT_STARTED);
690 while (!__nrfy_internal_saadc_events_process(p_reg, evt_mask, NULL))
691 {}
692 }
693 nrf_barrier_w();
694 }
695
__nrfy_internal_saadc_stop(NRF_SAADC_Type * p_reg,bool wait)696 NRFY_STATIC_INLINE void __nrfy_internal_saadc_stop(NRF_SAADC_Type * p_reg, bool wait)
697 {
698 nrf_saadc_task_trigger(p_reg, NRF_SAADC_TASK_STOP);
699 if (wait)
700 {
701 nrf_barrier_w();
702 uint32_t evt_mask = NRFY_EVENT_TO_INT_BITMASK(NRF_SAADC_EVENT_STOPPED);
703 while (!__nrfy_internal_saadc_events_process(p_reg, evt_mask, NULL))
704 {}
705 }
706 }
707
708 #ifdef __cplusplus
709 }
710 #endif
711
712 #endif // NRFY_SAADC_H__
713
