1 /*
2 * Copyright (c) 2021 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRFY_QDEC_H__
35 #define NRFY_QDEC_H__
36
37 #include <nrfx.h>
38 #include <hal/nrf_qdec.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 NRFY_STATIC_INLINE void __nrfy_internal_qdec_event_enabled_clear(NRF_QDEC_Type * p_reg,
45 uint32_t mask,
46 nrf_qdec_event_t event);
47
48 NRFY_STATIC_INLINE bool __nrfy_internal_qdec_event_handle(NRF_QDEC_Type * p_reg,
49 uint32_t mask,
50 nrf_qdec_event_t event,
51 uint32_t * p_evt_mask);
52
53 NRFY_STATIC_INLINE uint32_t __nrfy_internal_qdec_events_process(NRF_QDEC_Type * p_reg,
54 uint32_t mask);
55
56 /**
57 * @defgroup nrfy_qdec QDEC HALY
58 * @{
59 * @ingroup nrf_qdec
60 * @brief Hardware access layer with cache and barrier support for managing the QDEC peripheral.
61 */
62
63 /** @brief Configuration structure for QDEC pins. */
64 typedef struct
65 {
66 uint32_t a_pin; /**< Pin number for A input. */
67 uint32_t b_pin; /**< Pin number for B input. */
68 uint32_t led_pin; /**< Pin number for LED output. */
69 } nrfy_qdec_pins_t;
70
71 /** @brief QDEC configuration structure. */
72 typedef struct
73 {
74 nrf_qdec_reportper_t reportper; /**< Report period in samples. */
75 nrf_qdec_sampleper_t sampleper; /**< Sampling period in microseconds. */
76 nrfy_qdec_pins_t pins; /**< Pin configuration structure. */
77 uint32_t ledpre; /**< Time (in microseconds) how long LED is switched on before sampling. */
78 nrf_qdec_ledpol_t ledpol; /**< Active LED polarity. */
79 bool dbfen; /**< State of debouncing filter. */
80 bool skip_psel_cfg; /**< Skip pin selection configuration.
81 When set to true, the driver does not modify
82 pin select registers in the peripheral.
83 Those registers are supposed to be set up
84 externally before the driver is initialized.
85 @note When both GPIO configuration and pin
86 selection are to be skipped, the structure
87 fields that specify pins can be omitted,
88 as they are ignored anyway. */
89 } nrfy_qdec_config_t;
90
91 /**
92 * @brief Function for configuring the QDEC.
93 *
94 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
95 * @param[in] p_config Pointer to the peripheral configuration structure.
96 */
nrfy_qdec_periph_configure(NRF_QDEC_Type * p_reg,nrfy_qdec_config_t const * p_config)97 NRFY_STATIC_INLINE void nrfy_qdec_periph_configure(NRF_QDEC_Type * p_reg,
98 nrfy_qdec_config_t const * p_config)
99 {
100 nrf_qdec_sampleper_set(p_reg, p_config->sampleper);
101 nrf_qdec_reportper_set(p_reg, p_config->reportper);
102
103 if (p_config->pins.led_pin != NRF_QDEC_PIN_NOT_CONNECTED)
104 {
105 nrf_qdec_ledpre_set(p_reg, p_config->ledpre);
106 nrf_qdec_ledpol_set(p_reg, p_config->ledpol);
107 }
108
109 if (!p_config->skip_psel_cfg)
110 {
111 nrf_qdec_pins_set(p_reg,
112 p_config->pins.a_pin,
113 p_config->pins.b_pin,
114 p_config->pins.led_pin);
115 }
116
117 if (p_config->dbfen)
118 {
119 nrf_qdec_dbfen_enable(p_reg);
120 }
121 else
122 {
123 nrf_qdec_dbfen_disable(p_reg);
124 }
125
126 nrf_barrier_w();
127 }
128
129 /**
130 * @brief Function for initializing the specified QDEC interrupts.
131 *
132 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
133 * @param[in] mask Mask of interrupts to be initialized.
134 * @param[in] irq_priority Interrupt priority.
135 * @param[in] enable True if the interrupts are to be enabled, false otherwise.
136 */
nrfy_qdec_int_init(NRF_QDEC_Type * p_reg,uint32_t mask,uint8_t irq_priority,bool enable)137 NRFY_STATIC_INLINE void nrfy_qdec_int_init(NRF_QDEC_Type * p_reg,
138 uint32_t mask,
139 uint8_t irq_priority,
140 bool enable)
141 {
142 __nrfy_internal_qdec_event_enabled_clear(p_reg, mask, NRF_QDEC_EVENT_SAMPLERDY);
143 __nrfy_internal_qdec_event_enabled_clear(p_reg, mask, NRF_QDEC_EVENT_REPORTRDY);
144 __nrfy_internal_qdec_event_enabled_clear(p_reg, mask, NRF_QDEC_EVENT_ACCOF);
145 #if NRF_QDEC_HAS_EVENT_DBLRDY
146 __nrfy_internal_qdec_event_enabled_clear(p_reg, mask, NRF_QDEC_EVENT_DBLRDY);
147 #endif
148 #if NRF_QDEC_HAS_EVENT_STOPPED
149 __nrfy_internal_qdec_event_enabled_clear(p_reg, mask, NRF_QDEC_EVENT_STOPPED);
150 #endif
151
152 nrf_barrier_w();
153
154 NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_reg), irq_priority);
155 NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_reg));
156
157 if (enable)
158 {
159 nrf_qdec_int_enable(p_reg, mask);
160 }
161
162 nrf_barrier_w();
163 }
164
165 /**
166 * @brief Function for uninitializing the QDEC interrupts.
167 *
168 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
169 */
nrfy_qdec_int_uninit(NRF_QDEC_Type * p_reg)170 NRFY_STATIC_INLINE void nrfy_qdec_int_uninit(NRF_QDEC_Type * p_reg)
171 {
172 NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_reg));
173 nrf_barrier_w();
174 }
175
176 /**
177 * @brief Function for processing the specified QDEC events.
178 *
179 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
180 * @param[in] mask Mask of events to be processed, created by @ref NRFY_EVENT_TO_INT_BITMASK().
181 *
182 * @return Mask of events that were generated and processed.
183 * To be checked against the result of @ref NRFY_EVENT_TO_INT_BITMASK().
184 */
nrfy_qdec_events_process(NRF_QDEC_Type * p_reg,uint32_t mask)185 NRFY_STATIC_INLINE uint32_t nrfy_qdec_events_process(NRF_QDEC_Type * p_reg,
186 uint32_t mask)
187 {
188 uint32_t evt_mask = __nrfy_internal_qdec_events_process(p_reg, mask);
189 nrf_barrier_w();
190 return evt_mask;
191 }
192
193 /**
194 * @brief Function for reading QDEC accumulators.
195 *
196 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
197 * @param[in] p_acc Pointer to store the accumulated transitions
198 * @param[in] p_accdbl Pointer to store the accumulated double transitions.
199 */
nrfy_qdec_accumulators_read(NRF_QDEC_Type const * p_reg,int32_t * p_acc,uint32_t * p_accdbl)200 NRFY_STATIC_INLINE void nrfy_qdec_accumulators_read(NRF_QDEC_Type const * p_reg,
201 int32_t * p_acc,
202 uint32_t * p_accdbl)
203 {
204 nrf_barrier_r();
205 *p_acc = nrf_qdec_accread_get(p_reg);
206 *p_accdbl = nrf_qdec_accdblread_get(p_reg);
207 nrf_barrier_r();
208 }
209
210 /**
211 * @brief Function for reading QDEC pins.
212 *
213 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
214 * @param[in] p_pins Pointer to the QDEC pin configurartion structure.
215 */
nrfy_qdec_pins_get(NRF_QDEC_Type const * p_reg,nrfy_qdec_pins_t * p_pins)216 NRFY_STATIC_INLINE void nrfy_qdec_pins_get(NRF_QDEC_Type const * p_reg,
217 nrfy_qdec_pins_t * p_pins)
218 {
219 nrf_barrier_rw();
220 p_pins->a_pin = nrf_qdec_phase_a_pin_get(p_reg);
221 p_pins->b_pin = nrf_qdec_phase_b_pin_get(p_reg);
222 p_pins->led_pin = nrf_qdec_led_pin_get(p_reg);
223 nrf_barrier_r();
224 }
225
226 /**
227 * @brief Function for setting QDEC pins.
228 *
229 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
230 * @param[in] p_pins Pointer to the QDEC pin configurartion structure.
231 */
nrfy_qdec_pins_set(NRF_QDEC_Type * p_reg,nrfy_qdec_pins_t const * p_pins)232 NRFY_STATIC_INLINE void nrfy_qdec_pins_set(NRF_QDEC_Type * p_reg,
233 nrfy_qdec_pins_t const * p_pins)
234 {
235 nrf_qdec_pins_set(p_reg, p_pins->a_pin, p_pins->b_pin, p_pins->led_pin);
236 nrf_barrier_w();
237 }
238
239 /** @refhal{nrf_qdec_enable} */
nrfy_qdec_enable(NRF_QDEC_Type * p_reg)240 NRFY_STATIC_INLINE void nrfy_qdec_enable(NRF_QDEC_Type * p_reg)
241 {
242 nrf_qdec_enable(p_reg);
243 nrf_barrier_w();
244 }
245
246 /** @refhal{nrf_qdec_disable} */
nrfy_qdec_disable(NRF_QDEC_Type * p_reg)247 NRFY_STATIC_INLINE void nrfy_qdec_disable(NRF_QDEC_Type * p_reg)
248 {
249 nrf_qdec_disable(p_reg);
250 nrf_barrier_w();
251 }
252
253 /** @refhal{nrf_qdec_enable_get} */
nrfy_qdec_enable_get(NRF_QDEC_Type const * p_reg)254 NRFY_STATIC_INLINE uint32_t nrfy_qdec_enable_get(NRF_QDEC_Type const * p_reg)
255 {
256 nrf_barrier_rw();
257 uint32_t ret = nrf_qdec_enable_get(p_reg);
258 nrf_barrier_r();
259 return ret;
260 }
261
262 /** @refhal{nrf_qdec_int_enable} */
nrfy_qdec_int_enable(NRF_QDEC_Type * p_reg,uint32_t mask)263 NRFY_STATIC_INLINE void nrfy_qdec_int_enable(NRF_QDEC_Type * p_reg, uint32_t mask)
264 {
265 nrf_qdec_int_enable(p_reg, mask);
266 nrf_barrier_w();
267 }
268
269 /** @refhal{nrf_qdec_int_disable} */
nrfy_qdec_int_disable(NRF_QDEC_Type * p_reg,uint32_t mask)270 NRFY_STATIC_INLINE void nrfy_qdec_int_disable(NRF_QDEC_Type * p_reg, uint32_t mask)
271 {
272 nrf_qdec_int_disable(p_reg, mask);
273 nrf_barrier_w();
274 }
275
276 /** @refhal{nrf_qdec_int_enable_check} */
nrfy_qdec_int_enable_check(NRF_QDEC_Type const * p_reg,uint32_t mask)277 NRFY_STATIC_INLINE uint32_t nrfy_qdec_int_enable_check(NRF_QDEC_Type const * p_reg, uint32_t mask)
278 {
279 nrf_barrier_rw();
280 uint32_t ret = nrf_qdec_int_enable_check(p_reg, mask);
281 nrf_barrier_r();
282 return ret;
283 }
284
285 /** @refhal{nrf_qdec_dbfen_enable} */
nrfy_qdec_dbfen_enable(NRF_QDEC_Type * p_reg)286 NRFY_STATIC_INLINE void nrfy_qdec_dbfen_enable(NRF_QDEC_Type * p_reg)
287 {
288 nrf_qdec_dbfen_enable(p_reg);
289 nrf_barrier_w();
290 }
291
292 /** @refhal{nrf_qdec_dbfen_disable} */
nrfy_qdec_dbfen_disable(NRF_QDEC_Type * p_reg)293 NRFY_STATIC_INLINE void nrfy_qdec_dbfen_disable(NRF_QDEC_Type * p_reg)
294 {
295 nrf_qdec_dbfen_disable(p_reg);
296 nrf_barrier_w();
297 }
298
299 /** @refhal{nrf_qdec_dbfen_get} */
nrfy_qdec_dbfen_get(NRF_QDEC_Type const * p_reg)300 NRFY_STATIC_INLINE uint32_t nrfy_qdec_dbfen_get(NRF_QDEC_Type const * p_reg)
301 {
302 nrf_barrier_rw();
303 uint32_t ret = nrf_qdec_dbfen_get(p_reg);
304 nrf_barrier_r();
305 return ret;
306 }
307
308 /** @refhal{nrf_qdec_phase_a_pin_get} */
nrfy_qdec_a_pin_get(NRF_QDEC_Type const * p_reg)309 NRFY_STATIC_INLINE uint32_t nrfy_qdec_a_pin_get(NRF_QDEC_Type const * p_reg)
310 {
311 nrf_barrier_rw();
312 uint32_t ret = nrf_qdec_phase_a_pin_get(p_reg);
313 nrf_barrier_r();
314 return ret;
315 }
316
317 /** @refhal{nrf_qdec_phase_b_pin_get} */
nrfy_qdec_b_pin_get(NRF_QDEC_Type const * p_reg)318 NRFY_STATIC_INLINE uint32_t nrfy_qdec_b_pin_get(NRF_QDEC_Type const * p_reg)
319 {
320 nrf_barrier_rw();
321 uint32_t ret = nrf_qdec_phase_b_pin_get(p_reg);
322 nrf_barrier_r();
323 return ret;
324 }
325
326 /** @refhal{nrf_qdec_led_pin_get} */
nrfy_qdec_led_pin_get(NRF_QDEC_Type const * p_reg)327 NRFY_STATIC_INLINE uint32_t nrfy_qdec_led_pin_get(NRF_QDEC_Type const * p_reg)
328 {
329 nrf_barrier_rw();
330 uint32_t ret = nrf_qdec_led_pin_get(p_reg);
331 nrf_barrier_r();
332 return ret;
333 }
334
335 /** @refhal{nrf_qdec_task_trigger} */
nrfy_qdec_task_trigger(NRF_QDEC_Type * p_reg,nrf_qdec_task_t task)336 NRFY_STATIC_INLINE void nrfy_qdec_task_trigger(NRF_QDEC_Type * p_reg, nrf_qdec_task_t task)
337 {
338 nrf_qdec_task_trigger(p_reg, task);
339 nrf_barrier_w();
340 }
341
342 /** @refhal{nrf_qdec_task_address_get} */
nrfy_qdec_task_address_get(NRF_QDEC_Type const * p_reg,nrf_qdec_task_t task)343 NRFY_STATIC_INLINE uint32_t nrfy_qdec_task_address_get(NRF_QDEC_Type const * p_reg,
344 nrf_qdec_task_t task)
345 {
346 return nrf_qdec_task_address_get(p_reg, task);
347 }
348
349 /** @refhal{nrf_qdec_event_clear} */
nrfy_qdec_event_clear(NRF_QDEC_Type * p_reg,nrf_qdec_event_t event)350 NRFY_STATIC_INLINE void nrfy_qdec_event_clear(NRF_QDEC_Type * p_reg, nrf_qdec_event_t event)
351 {
352 nrf_qdec_event_clear(p_reg, event);
353 nrf_barrier_w();
354 }
355
356 /** @refhal{nrf_qdec_event_check} */
nrfy_qdec_event_check(NRF_QDEC_Type const * p_reg,nrf_qdec_event_t event)357 NRFY_STATIC_INLINE bool nrfy_qdec_event_check(NRF_QDEC_Type const * p_reg, nrf_qdec_event_t event)
358 {
359 nrf_barrier_rw();
360 bool ret = nrf_qdec_event_check(p_reg, event);
361 nrf_barrier_r();
362 return ret;
363 }
364
365 /** @refhal{nrf_qdec_event_address_get} */
nrfy_qdec_event_address_get(NRF_QDEC_Type const * p_reg,nrf_qdec_event_t event)366 NRFY_STATIC_INLINE uint32_t nrfy_qdec_event_address_get(NRF_QDEC_Type const * p_reg,
367 nrf_qdec_event_t event)
368 {
369 return nrf_qdec_event_address_get(p_reg, event);
370 }
371
372 /** @refhal{nrf_qdec_shorts_enable} */
nrfy_qdec_shorts_enable(NRF_QDEC_Type * p_reg,uint32_t mask)373 NRFY_STATIC_INLINE void nrfy_qdec_shorts_enable(NRF_QDEC_Type * p_reg, uint32_t mask)
374 {
375 nrf_qdec_shorts_enable(p_reg, mask);
376 nrf_barrier_w();
377 }
378
379 /** @refhal{nrf_qdec_shorts_disable} */
nrfy_qdec_shorts_disable(NRF_QDEC_Type * p_reg,uint32_t mask)380 NRFY_STATIC_INLINE void nrfy_qdec_shorts_disable(NRF_QDEC_Type * p_reg, uint32_t mask)
381 {
382 nrf_qdec_shorts_disable(p_reg, mask);
383 nrf_barrier_w();
384 }
385
386 /** @refhal{nrf_qdec_sampleper_to_value} */
nrfy_qdec_sampleper_to_value(nrf_qdec_sampleper_t sampleper)387 NRFY_STATIC_INLINE uint32_t nrfy_qdec_sampleper_to_value(nrf_qdec_sampleper_t sampleper)
388 {
389 return nrf_qdec_sampleper_to_value(sampleper);
390 }
391
392 /** @refhal{nrf_qdec_sampleper_set} */
nrfy_qdec_sampleper_set(NRF_QDEC_Type * p_reg,nrf_qdec_sampleper_t sampleper)393 NRFY_STATIC_INLINE void nrfy_qdec_sampleper_set(NRF_QDEC_Type * p_reg,
394 nrf_qdec_sampleper_t sampleper)
395 {
396 nrf_qdec_sampleper_set(p_reg, sampleper);
397 nrf_barrier_w();
398 }
399
400 /** @refhal{nrf_qdec_sampleper_get} */
nrfy_qdec_sampleper_get(NRF_QDEC_Type const * p_reg)401 NRFY_STATIC_INLINE nrf_qdec_sampleper_t nrfy_qdec_sampleper_get(NRF_QDEC_Type const * p_reg)
402 {
403 nrf_barrier_rw();
404 nrf_qdec_sampleper_t ret = nrf_qdec_sampleper_get(p_reg);
405 nrf_barrier_r();
406 return ret;
407 }
408
409 /** @refhal{nrf_qdec_sample_get} */
nrfy_qdec_sample_get(NRF_QDEC_Type const * p_reg)410 NRFY_STATIC_INLINE int32_t nrfy_qdec_sample_get(NRF_QDEC_Type const * p_reg)
411 {
412 nrf_barrier_rw();
413 int32_t ret = nrf_qdec_sample_get(p_reg);
414 nrf_barrier_r();
415 return ret;
416 }
417
418 /** @refhal{nrf_qdec_acc_get} */
nrfy_qdec_acc_get(NRF_QDEC_Type const * p_reg)419 NRFY_STATIC_INLINE int32_t nrfy_qdec_acc_get(NRF_QDEC_Type const * p_reg)
420 {
421 nrf_barrier_r();
422 int32_t ret = nrf_qdec_acc_get(p_reg);
423 nrf_barrier_r();
424 return ret;
425 }
426
427 /** @refhal{nrf_qdec_accread_get} */
nrfy_qdec_accread_get(NRF_QDEC_Type const * p_reg)428 NRFY_STATIC_INLINE int32_t nrfy_qdec_accread_get(NRF_QDEC_Type const * p_reg)
429 {
430 nrf_barrier_r();
431 int32_t ret = nrf_qdec_accread_get(p_reg);
432 nrf_barrier_r();
433 return ret;
434 }
435
436 /** @refhal{nrf_qdec_accdbl_get} */
nrfy_qdec_accdbl_get(NRF_QDEC_Type const * p_reg)437 NRFY_STATIC_INLINE uint32_t nrfy_qdec_accdbl_get(NRF_QDEC_Type const * p_reg)
438 {
439 nrf_barrier_r();
440 uint32_t ret = nrf_qdec_accdbl_get(p_reg);
441 nrf_barrier_r();
442 return ret;
443 }
444
445 /** @refhal{nrf_qdec_accdblread_get} */
nrfy_qdec_accdblread_get(NRF_QDEC_Type const * p_reg)446 NRFY_STATIC_INLINE uint32_t nrfy_qdec_accdblread_get(NRF_QDEC_Type const * p_reg)
447 {
448 nrf_barrier_r();
449 uint32_t ret = nrf_qdec_accdblread_get(p_reg);
450 nrf_barrier_r();
451 return ret;
452 }
453
454 /** @refhal{nrf_qdec_ledpre_set} */
nrfy_qdec_ledpre_set(NRF_QDEC_Type * p_reg,uint32_t time_us)455 NRFY_STATIC_INLINE void nrfy_qdec_ledpre_set(NRF_QDEC_Type * p_reg, uint32_t time_us)
456 {
457 nrf_qdec_ledpre_set(p_reg, time_us);
458 nrf_barrier_w();
459 }
460
461 /** @refhal{nrf_qdec_ledpre_get} */
nrfy_qdec_ledpre_get(NRF_QDEC_Type const * p_reg)462 NRFY_STATIC_INLINE uint32_t nrfy_qdec_ledpre_get(NRF_QDEC_Type const * p_reg)
463 {
464 nrf_barrier_rw();
465 uint32_t ret = nrf_qdec_ledpre_get(p_reg);
466 nrf_barrier_r();
467 return ret;
468 }
469
470 /** @refhal{nrf_qdec_ledpol_set} */
nrfy_qdec_ledpol_set(NRF_QDEC_Type * p_reg,nrf_qdec_ledpol_t pol)471 NRFY_STATIC_INLINE void nrfy_qdec_ledpol_set(NRF_QDEC_Type * p_reg, nrf_qdec_ledpol_t pol)
472 {
473 nrf_qdec_ledpol_set(p_reg, pol);
474 nrf_barrier_w();
475 }
476
477 /** @refhal{nrf_qdec_ledpol_get} */
nrfy_qdec_ledpol_get(NRF_QDEC_Type const * p_reg)478 NRFY_STATIC_INLINE uint32_t nrfy_qdec_ledpol_get(NRF_QDEC_Type const * p_reg)
479 {
480 nrf_barrier_rw();
481 uint32_t ret = nrf_qdec_ledpol_get(p_reg);
482 nrf_barrier_r();
483
484 return ret;
485 }
486
487 /** @refhal{nrf_qdec_reportper_set} */
nrfy_qdec_reportper_set(NRF_QDEC_Type * p_reg,nrf_qdec_reportper_t reportper)488 NRFY_STATIC_INLINE void nrfy_qdec_reportper_set(NRF_QDEC_Type * p_reg,
489 nrf_qdec_reportper_t reportper)
490 {
491 nrf_qdec_reportper_set(p_reg, reportper);
492 nrf_barrier_w();
493 }
494
495 /** @refhal{nrf_qdec_reportper_get} */
nrfy_qdec_reportper_get(NRF_QDEC_Type const * p_reg)496 NRFY_STATIC_INLINE nrf_qdec_reportper_t nrfy_qdec_reportper_get(NRF_QDEC_Type const * p_reg)
497 {
498 nrf_barrier_rw();
499 nrf_qdec_reportper_t ret = nrf_qdec_reportper_get(p_reg);
500 nrf_barrier_r();
501 return ret;
502 }
503
504 /** @refhal{nrf_qdec_reportper_to_value} */
nrfy_qdec_reportper_to_value(nrf_qdec_reportper_t reportper)505 NRFY_STATIC_INLINE uint32_t nrfy_qdec_reportper_to_value(nrf_qdec_reportper_t reportper)
506 {
507 return nrf_qdec_reportper_to_value(reportper);
508 }
509
510 /** @} */
511
__nrfy_internal_qdec_event_enabled_clear(NRF_QDEC_Type * p_reg,uint32_t mask,nrf_qdec_event_t event)512 NRFY_STATIC_INLINE void __nrfy_internal_qdec_event_enabled_clear(NRF_QDEC_Type * p_reg,
513 uint32_t mask,
514 nrf_qdec_event_t event)
515 {
516 if (mask & NRFY_EVENT_TO_INT_BITMASK(event))
517 {
518 nrf_qdec_event_clear(p_reg, event);
519 }
520 }
521
__nrfy_internal_qdec_event_handle(NRF_QDEC_Type * p_reg,uint32_t mask,nrf_qdec_event_t event,uint32_t * p_evt_mask)522 NRFY_STATIC_INLINE bool __nrfy_internal_qdec_event_handle(NRF_QDEC_Type * p_reg,
523 uint32_t mask,
524 nrf_qdec_event_t event,
525 uint32_t * p_evt_mask)
526 {
527 if ((mask & NRFY_EVENT_TO_INT_BITMASK(event)) && nrf_qdec_event_check(p_reg, event))
528 {
529 nrf_qdec_event_clear(p_reg, event);
530 if (p_evt_mask)
531 {
532 *p_evt_mask |= NRFY_EVENT_TO_INT_BITMASK(event);
533 }
534 return true;
535 }
536 return false;
537 }
538
__nrfy_internal_qdec_events_process(NRF_QDEC_Type * p_reg,uint32_t mask)539 NRFY_STATIC_INLINE uint32_t __nrfy_internal_qdec_events_process(NRF_QDEC_Type * p_reg,
540 uint32_t mask)
541 {
542 uint32_t event_mask = 0;
543
544 nrf_barrier_r();
545 (void)__nrfy_internal_qdec_event_handle(p_reg,
546 mask,
547 NRF_QDEC_EVENT_SAMPLERDY,
548 &event_mask);
549 (void)__nrfy_internal_qdec_event_handle(p_reg,
550 mask,
551 NRF_QDEC_EVENT_REPORTRDY,
552 &event_mask);
553 (void)__nrfy_internal_qdec_event_handle(p_reg,
554 mask,
555 NRF_QDEC_EVENT_ACCOF,
556 &event_mask);
557 #if NRF_QDEC_HAS_EVENT_DBLRDY
558 (void)__nrfy_internal_qdec_event_handle(p_reg,
559 mask,
560 NRF_QDEC_EVENT_DBLRDY,
561 &event_mask);
562 #endif
563 #if NRF_QDEC_HAS_EVENT_STOPPED
564 (void)__nrfy_internal_qdec_event_handle(p_reg,
565 mask,
566 NRF_QDEC_EVENT_STOPPED,
567 &event_mask);
568 #endif
569 return event_mask;
570 }
571
572 #ifdef __cplusplus
573 }
574 #endif
575
576 #endif // NRFY_QDEC_H__
577
