1 /*
2 * Copyright (c) 2015 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_UARTE_H__
35 #define NRF_UARTE_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if defined(NRF54H20_XXAA) || defined(NRF92_SERIES)
44 #define NRF_UARTE_CLOCKPIN_TXD_NEEDED 1
45 #endif
46
47 #define NRF_UARTE_PSEL_DISCONNECTED 0xFFFFFFFF
48
49 /**
50 * @defgroup nrf_uarte_hal UARTE HAL
51 * @{
52 * @ingroup nrf_uarte
53 * @brief Hardware access layer for managing the UARTE peripheral.
54 */
55
56 /**
57 * @brief Macro getting pointer to the structure of registers of the UARTE peripheral.
58 *
59 * @param[in] idx UARTE instance index.
60 *
61 * @return Pointer to the structure of registers of the UARTE peripheral.
62 */
63 #define NRF_UARTE_INST_GET(idx) NRFX_CONCAT(NRF_, UARTE, idx)
64
65 #if defined(UARTE_DMA_RX_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
66 /** @brief Symbol indicating whether dedicated DMA register is present. */
67 #define NRF_UARTE_HAS_DMA_REG 1
68 #else
69 #define NRF_UARTE_HAS_DMA_REG 0
70 #endif
71
72 #if (defined(UARTE_TASKS_DMA_RX_START_START_Msk) && defined(UARTE_EVENTS_DMA_RX_END_END_Msk)) || \
73 defined(__NRFX_DOXYGEN__)
74 /** @brief Symbol indicating whether UARTE DMA tasks and events are present. */
75 #define NRF_UARTE_HAS_DMA_TASKS_EVENTS 1
76 #else
77 #define NRF_UARTE_HAS_DMA_TASKS_EVENTS 0
78 #endif
79
80 #if defined(UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Msk) || defined(__NRFX_DOXYGEN__)
81 /** @brief Symbol indicating whether UARTE DMA shortcuts are present. */
82 #define NRF_UARTE_HAS_DMA_SHORTS 1
83 #else
84 #define NRF_UARTE_HAS_DMA_SHORTS 0
85 #endif
86
87 #if defined(UARTE_SHORTS_ENDTX_STOPTX_Msk) || defined(UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Msk) || \
88 defined(__NRFX_DOXYGEN__)
89 /** @brief Symbol indicating whether UARTE ENDTX_STOPTX shortcut is present. */
90 #define NRF_UARTE_HAS_ENDTX_STOPTX_SHORT 1
91 #else
92 #define NRF_UARTE_HAS_ENDTX_STOPTX_SHORT 0
93 #endif
94
95 #if defined(UARTE_EVENTS_FRAMETIMEOUT_EVENTS_FRAMETIMEOUT_Msk) || defined(__NRFX_DOXYGEN__)
96 /** @brief Symbol indicating whether UARTE FRAMETIMEOUT event is present. */
97 #define NRF_UARTE_HAS_FRAME_TIMEOUT 1
98 #else
99 #define NRF_UARTE_HAS_FRAME_TIMEOUT 0
100 #endif
101
102 /** @brief Base frequency value 320 MHz for UARTE. */
103 #define NRF_UARTE_BASE_FREQUENCY_320MHZ (NRFX_MHZ_TO_HZ(320UL))
104 /** @brief Base frequency value 128 MHz for UARTE. */
105 #define NRF_UARTE_BASE_FREQUENCY_128MHZ (NRFX_MHZ_TO_HZ(128UL))
106 /** @brief Base frequency value 64 MHz for UARTE. */
107 #define NRF_UARTE_BASE_FREQUENCY_64MHZ (NRFX_MHZ_TO_HZ(64UL))
108 /** @brief Base frequency value 16 MHz for UARTE. */
109 #define NRF_UARTE_BASE_FREQUENCY_16MHZ (NRFX_MHZ_TO_HZ(16UL))
110
111 #if !defined(NRF_UARTE_IS_320MHZ_UARTE)
112 /** @brief Macro for checking whether the base frequency for the specified UARTE is 320 MHz. */
113 #define NRF_UARTE_IS_320MHZ_UARTE(p_reg) \
114 NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(UARTE120), (p_reg == NRF_UARTE120), (false))
115 #endif
116
117 #if !defined(NRF_UARTE_IS_128MHZ_UARTE)
118 /** @brief Macro for checking whether the base frequency for the specified UARTE is 128 MHz. */
119 #define NRF_UARTE_IS_128MHZ_UARTE(p_reg) \
120 (NRFX_COND_CODE_1(NRFX_IS_ENABLED(NRF_CPU_FREQ_IS_128MHZ), \
121 (NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(UARTE00), (p_reg == NRF_UARTE00), (false))), \
122 (false)))
123 #endif
124
125 #if !defined(NRF_UARTE_IS_64MHZ_UARTE)
126 /** @brief Macro for checking whether the base frequency for the specified UARTE is 64 MHz. */
127 #define NRF_UARTE_IS_64MHZ_UARTE(p_reg) \
128 (NRFX_COND_CODE_1(NRFX_IS_ENABLED(NRF_CPU_FREQ_IS_64MHZ), \
129 (NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(UARTE00), (p_reg == NRF_UARTE00), (false))), \
130 (false)))
131 #endif
132
133 /**
134 * @brief Macro for getting base frequency value in Hz for the specified UARTE.
135 *
136 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
137 */
138 #define NRF_UARTE_BASE_FREQUENCY_GET(p_reg) \
139 ((NRF_UARTE_IS_320MHZ_UARTE(p_reg)) ? (NRF_UARTE_BASE_FREQUENCY_320MHZ): \
140 ((NRF_UARTE_IS_128MHZ_UARTE(p_reg)) ? (NRF_UARTE_BASE_FREQUENCY_128MHZ): \
141 ((NRF_UARTE_IS_64MHZ_UARTE(p_reg)) ? (NRF_UARTE_BASE_FREQUENCY_64MHZ) : \
142 (NRF_UARTE_BASE_FREQUENCY_16MHZ))))
143
144 /** @brief UARTE tasks. */
145 typedef enum
146 {
147 #if NRF_UARTE_HAS_DMA_TASKS_EVENTS
148 NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_DMA.RX.START), ///< Start UART receiver.
149 NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_DMA.RX.STOP), ///< Stop UART receiver.
150 NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_DMA.TX.START), ///< Start UART transmitter.
151 NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_DMA.TX.STOP), ///< Stop UART transmitter.
152 #else
153 NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX), ///< Start UART receiver.
154 NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver.
155 NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX), ///< Start UART transmitter.
156 NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter.
157 #endif
158 NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer.
159 } nrf_uarte_task_t;
160
161 /** @brief UARTE events. */
162 typedef enum
163 {
164 NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated.
165 NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated.
166 NRF_UARTE_EVENT_RXDRDY = offsetof(NRF_UARTE_Type, EVENTS_RXDRDY), ///< Data received in RXD (but potentially not yet transferred to Data RAM).
167 NRF_UARTE_EVENT_TXDRDY = offsetof(NRF_UARTE_Type, EVENTS_TXDRDY), ///< Data sent from TXD.
168 NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected.
169 NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout.
170 NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED), ///< Transmitted stopped.
171 #if NRF_UARTE_HAS_DMA_TASKS_EVENTS
172 NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_DMA.RX.END), ///< Receive buffer is filled up.
173 NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_DMA.TX.END), ///< Last TX byte transmitted.
174 NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_DMA.RX.READY), ///< Receiver has started.
175 NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_DMA.TX.READY), ///< Transmitter has started.
176 #else
177 NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up.
178 NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted.
179 NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED), ///< Receiver has started.
180 NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED), ///< Transmitter has started.
181 #endif
182 #if NRF_UARTE_HAS_FRAME_TIMEOUT
183 NRF_UARTE_EVENT_FRAME_TIMEOUT = offsetof(NRF_UARTE_Type, EVENTS_FRAMETIMEOUT), ///< Frame timeout.
184 #endif
185 } nrf_uarte_event_t;
186
187 /** @brief Types of UARTE shortcuts. */
188 typedef enum
189 {
190 #if NRF_UARTE_HAS_DMA_SHORTS
191 NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_DMA_RX_END_DMA_RX_START_Msk, ///< Shortcut between ENDRX event and STARTRX task.
192 NRF_UARTE_SHORT_ENDRX_STOPRX = UARTE_SHORTS_DMA_RX_END_DMA_RX_STOP_Msk, ///< Shortcut between ENDRX event and STOPRX task.
193 NRF_UARTE_SHORT_ENDTX_STOPTX = UARTE_SHORTS_DMA_TX_END_DMA_TX_STOP_Msk, ///< Shortcut between ENDTX event and STOPTX task.
194 #else
195 NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_ENDRX_STARTRX_Msk, ///< Shortcut between ENDRX event and STARTRX task.
196 NRF_UARTE_SHORT_ENDRX_STOPRX = UARTE_SHORTS_ENDRX_STOPRX_Msk, ///< Shortcut between ENDRX event and STOPRX task.
197 #if NRF_UARTE_HAS_ENDTX_STOPTX_SHORT
198 NRF_UARTE_SHORT_ENDTX_STOPTX = UARTE_SHORTS_ENDTX_STOPTX_Msk, ///< Shortcut between ENDTX event and STOPTX task.
199 #endif
200 #endif
201 #if NRF_UARTE_HAS_FRAME_TIMEOUT
202 NRF_UARTE_SHORT_FRAME_TIMEOUT_STOPRX = UARTE_SHORTS_FRAMETIMEOUT_DMA_RX_STOP_Msk ///< Shortcut between ENDTX event and STOPTX task.
203 #endif
204 } nrf_uarte_short_t;
205
206
207 /** @brief UARTE interrupts. */
208 typedef enum
209 {
210 NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event.
211 NRF_UARTE_INT_NCTS_MASK = UARTE_INTENSET_NCTS_Msk, ///< Interrupt on NCTS event.
212 NRF_UARTE_INT_RXDRDY_MASK = UARTE_INTENSET_RXDRDY_Msk, ///< Interrupt on RXDRDY event.
213 NRF_UARTE_INT_TXDRDY_MASK = UARTE_INTENSET_TXDRDY_Msk, ///< Interrupt on TXDRDY event.
214 NRF_UARTE_INT_ERROR_MASK = UARTE_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
215 NRF_UARTE_INT_RXTO_MASK = UARTE_INTENSET_RXTO_Msk, ///< Interrupt on RXTO event.
216 NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk, ///< Interrupt on TXSTOPPED event.
217 #if NRF_UARTE_HAS_DMA_TASKS_EVENTS
218 NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_DMARXEND_Msk, ///< Interrupt on ENDRX event.
219 NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_DMATXEND_Msk, ///< Interrupt on ENDTX event.
220 NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_DMARXREADY_Msk, ///< Interrupt on RXSTARTED event.
221 NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_DMATXREADY_Msk, ///< Interrupt on TXSTARTED event.
222 #else
223 NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
224 NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
225 NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
226 NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
227 #endif
228 #if NRF_UARTE_HAS_FRAME_TIMEOUT
229 NRF_UARTE_INT_FRAME_TIMEOUT_MASK = UARTE_INTENSET_FRAMETIMEOUT_Msk, ///< Interrupt on FRAMETIMEOUT event.
230 #endif
231 } nrf_uarte_int_mask_t;
232
233 /** @brief Baudrates supported by UARTE. */
234 typedef enum
235 {
236 NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud.
237 NRF_UARTE_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud.
238 NRF_UARTE_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud.
239 NRF_UARTE_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud.
240 NRF_UARTE_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud.
241 NRF_UARTE_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud.
242 NRF_UARTE_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud.
243 NRF_UARTE_BAUDRATE_31250 = UARTE_BAUDRATE_BAUDRATE_Baud31250, ///< 31250 baud.
244 NRF_UARTE_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud.
245 NRF_UARTE_BAUDRATE_56000 = UARTE_BAUDRATE_BAUDRATE_Baud56000, ///< 56000 baud.
246 NRF_UARTE_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud.
247 NRF_UARTE_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud.
248 NRF_UARTE_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
249 NRF_UARTE_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
250 NRF_UARTE_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
251 NRF_UARTE_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
252 NRF_UARTE_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
253 NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M ///< 1000000 baud.
254 } nrf_uarte_baudrate_t;
255
256 /** @brief Types of UARTE error masks. */
257 typedef enum
258 {
259 NRF_UARTE_ERROR_OVERRUN_MASK = UARTE_ERRORSRC_OVERRUN_Msk, ///< Overrun error.
260 NRF_UARTE_ERROR_PARITY_MASK = UARTE_ERRORSRC_PARITY_Msk, ///< Parity error.
261 NRF_UARTE_ERROR_FRAMING_MASK = UARTE_ERRORSRC_FRAMING_Msk, ///< Framing error.
262 NRF_UARTE_ERROR_BREAK_MASK = UARTE_ERRORSRC_BREAK_Msk ///< Break error.
263 } nrf_uarte_error_mask_t;
264
265 /** @brief Types of UARTE parity modes. */
266 typedef enum
267 {
268 NRF_UARTE_PARITY_EXCLUDED = UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos, ///< Parity excluded.
269 NRF_UARTE_PARITY_INCLUDED = UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos ///< Parity included.
270 } nrf_uarte_parity_t;
271
272 /** @brief Types of UARTE flow control modes. */
273 typedef enum
274 {
275 NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< Hardware flow control disabled.
276 NRF_UARTE_HWFC_ENABLED = UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos ///< Hardware flow control enabled.
277 } nrf_uarte_hwfc_t;
278
279 #if defined(UARTE_CONFIG_STOP_Msk) || defined(__NRFX_DOXYGEN__)
280 /** @brief Types of UARTE stop bit modes. */
281 typedef enum
282 {
283 NRF_UARTE_STOP_ONE = UARTE_CONFIG_STOP_One << UARTE_CONFIG_STOP_Pos, ///< One stop bit.
284 NRF_UARTE_STOP_TWO = UARTE_CONFIG_STOP_Two << UARTE_CONFIG_STOP_Pos ///< Two stop bits.
285 } nrf_uarte_stop_t;
286 #endif
287
288 #if defined(UARTE_CONFIG_PARITYTYPE_Msk) || defined(__NRFX_DOXYGEN__)
289 /** @brief Types of UARTE parity types. */
290 typedef enum
291 {
292 NRF_UARTE_PARITYTYPE_EVEN = UARTE_CONFIG_PARITYTYPE_Even << UARTE_CONFIG_PARITYTYPE_Pos, ///< Parity even.
293 NRF_UARTE_PARITYTYPE_ODD = UARTE_CONFIG_PARITYTYPE_Odd << UARTE_CONFIG_PARITYTYPE_Pos, ///< Parity odd.
294 } nrf_uarte_paritytype_t;
295 #endif
296
297 #if NRF_UARTE_HAS_FRAME_TIMEOUT
298 /** @brief Types of UARTE Frame timeout. */
299 typedef enum {
300 NRF_UARTE_FRAME_TIMEOUT_EN = UARTE_CONFIG_FRAMETIMEOUT_ENABLED << UARTE_CONFIG_FRAMETIMEOUT_Pos, ///< Frame timeout enabled.
301 NRF_UARTE_FRAME_TIMEOUT_DIS = UARTE_CONFIG_FRAMETIMEOUT_DISABLED << UARTE_CONFIG_FRAMETIMEOUT_Pos, ///< Frame timeout disabled.
302 } nrf_uarte_frame_timeout_t;
303 #endif
304
305 /** @brief Structure for UARTE transmission configuration. */
306 typedef struct
307 {
308 nrf_uarte_hwfc_t hwfc; ///< Flow control configuration.
309 nrf_uarte_parity_t parity; ///< Parity configuration.
310 #if defined(UARTE_CONFIG_STOP_Msk) || defined(__NRFX_DOXYGEN__)
311 nrf_uarte_stop_t stop; ///< Stop bits.
312 #endif
313 #if defined(UARTE_CONFIG_PARITYTYPE_Msk) || defined(__NRFX_DOXYGEN__)
314 nrf_uarte_paritytype_t paritytype; ///< Parity type.
315 #endif
316 #if NRF_UARTE_HAS_FRAME_TIMEOUT
317 nrf_uarte_frame_timeout_t frame_timeout; ///< Frame timeout.
318 #endif
319 } nrf_uarte_config_t;
320
321 /**
322 * @brief Function for clearing a specific UARTE event.
323 *
324 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
325 * @param[in] event Event to clear.
326 */
327 NRF_STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
328
329 /**
330 * @brief Function for retrieving the state of the UARTE event.
331 *
332 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
333 * @param[in] event Event to be checked.
334 *
335 * @retval true The event has been generated.
336 * @retval false The event has not been generated.
337 */
338 NRF_STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type const * p_reg,
339 nrf_uarte_event_t event);
340
341 /**
342 * @brief Function for returning the address of the specified UARTE event register.
343 *
344 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
345 * @param[in] event The specified event.
346 *
347 * @return Address of specified event register.
348 */
349 NRF_STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type const * p_reg,
350 nrf_uarte_event_t event);
351
352 /**
353 * @brief Function for configuring UARTE shortcuts.
354 *
355 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
356 * @param[in] mask Shortcuts to be set.
357 */
358 NRF_STATIC_INLINE void nrf_uarte_shorts_set(NRF_UARTE_Type * p_reg, uint32_t mask);
359
360 /**
361 * @brief Function for getting UARTE shortcuts.
362 *
363 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
364 * @param[in] mask Shortcuts to be checked.
365 *
366 * @return Mask of requested shortcuts which were enabled.
367 */
368 NRF_STATIC_INLINE uint32_t nrf_uarte_shorts_get(NRF_UARTE_Type * p_reg, uint32_t mask);
369
370 /**
371 * @brief Function for enabling UARTE shortcuts.
372 *
373 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
374 * @param[in] mask Shortcuts to be enabled.
375 */
376 NRF_STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t mask);
377
378 /**
379 * @brief Function for disabling UARTE shortcuts.
380 *
381 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
382 * @param[in] mask Shortcuts to be disabled.
383 */
384 NRF_STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t mask);
385
386 /**
387 * @brief Function for enabling UARTE interrupts.
388 *
389 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
390 * @param[in] mask Mask of interrupts to be enabled.
391 * Use @ref nrf_uarte_int_mask_t values for bit masking.
392 */
393 NRF_STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask);
394
395 /**
396 * @brief Function for checking if the specified interrupts are enabled.
397 *
398 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
399 * @param[in] mask Mask of interrupts to be checked.
400 * Use @ref nrf_uarte_int_mask_t values for bit masking.
401 *
402 * @return Mask of enabled interrupts.
403 */
404 NRF_STATIC_INLINE uint32_t nrf_uarte_int_enable_check(NRF_UARTE_Type const * p_reg, uint32_t mask);
405
406 /**
407 * @brief Function for disabling the specified interrupts.
408 *
409 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
410 * @param[in] mask Mask of interrupts to be disabled.
411 * Use @ref nrf_uarte_int_mask_t values for bit masking.
412 */
413 NRF_STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask);
414
415 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
416 /**
417 * @brief Function for setting the subscribe configuration for a given
418 * UARTE task.
419 *
420 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
421 * @param[in] task Task for which to set the configuration.
422 * @param[in] channel Channel through which to subscribe events.
423 */
424 NRF_STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
425 nrf_uarte_task_t task,
426 uint8_t channel);
427
428 /**
429 * @brief Function for clearing the subscribe configuration for a given
430 * UARTE task.
431 *
432 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
433 * @param[in] task Task for which to clear the configuration.
434 */
435 NRF_STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,
436 nrf_uarte_task_t task);
437
438 /**
439 * @brief Function for setting the publish configuration for a given
440 * UARTE event.
441 *
442 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
443 * @param[in] event Event for which to set the configuration.
444 * @param[in] channel Channel through which to publish the event.
445 */
446 NRF_STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,
447 nrf_uarte_event_t event,
448 uint8_t channel);
449
450 /**
451 * @brief Function for clearing the publish configuration for a given
452 * UARTE event.
453 *
454 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
455 * @param[in] event Event for which to clear the configuration.
456 */
457 NRF_STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,
458 nrf_uarte_event_t event);
459 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
460
461 /**
462 * @brief Function for getting error source mask. Function is clearing error source flags after reading.
463 *
464 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
465 *
466 * @return Mask with error source flags.
467 */
468 NRF_STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg);
469
470 /**
471 * @brief Function for getting error source mask.
472 *
473 * @param p_reg Pointer to the structure of registers of the peripheral.
474 *
475 * @return Mask with error source flags.
476 */
477 NRF_STATIC_INLINE uint32_t nrf_uarte_errorsrc_get(NRF_UARTE_Type * p_reg);
478
479 /**
480 * @brief Function for clearing error source flags after reading.
481 *
482 * @param p_reg Pointer to the structure of registers of the peripheral.
483 *
484 * @param errsrc_mask Mask with error sources to be cleared.
485 */
486 NRF_STATIC_INLINE void nrf_uarte_errorsrc_clear(NRF_UARTE_Type * p_reg, uint32_t errsrc_mask);
487
488 /**
489 * @brief Function for enabling UARTE.
490 *
491 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
492 */
493 NRF_STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg);
494
495 /**
496 * @brief Function for disabling UARTE.
497 *
498 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
499 */
500 NRF_STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg);
501
502 /**
503 * @brief Function for checking if the UARTE is enabled.
504 *
505 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
506 *
507 * @retval true The UARTE is enabled.
508 * @retval false The UARTE is not enabled.
509 */
510 NRF_STATIC_INLINE bool nrf_uarte_enable_check(NRF_UARTE_Type const * p_reg);
511
512 /**
513 * @brief Function for configuring TX/RX pins.
514 *
515 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
516 * @param[in] pseltxd TXD pin number.
517 * @param[in] pselrxd RXD pin number.
518 */
519 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,
520 uint32_t pseltxd,
521 uint32_t pselrxd);
522
523 /**
524 * @brief Function for disconnecting TX/RX pins.
525 *
526 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
527 */
528 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg);
529
530 /**
531 * @brief Function for configuring TX pin.
532 *
533 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
534 * @param[in] pseltxd TXD pin number.
535 */
536 NRF_STATIC_INLINE void nrf_uarte_tx_pin_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd);
537
538 /**
539 * @brief Function for getting TX pin selection.
540 *
541 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
542 *
543 * @return TX pin selection.
544 */
545 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg);
546
547 /**
548 * @brief Function for configuring RX pin.
549 *
550 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
551 * @param[in] pselrxd RXD pin number.
552 */
553 NRF_STATIC_INLINE void nrf_uarte_rx_pin_set(NRF_UARTE_Type * p_reg, uint32_t pselrxd);
554
555 /**
556 * @brief Function for getting RX pin selection.
557 *
558 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
559 *
560 * @return RX pin selection.
561 */
562 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg);
563
564 /**
565 * @brief Function for configuring RTS pin.
566 *
567 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
568 * @param[in] pselrts RTS pin number.
569 */
570 NRF_STATIC_INLINE void nrf_uarte_rts_pin_set(NRF_UARTE_Type * p_reg, uint32_t pselrts);
571
572 /**
573 * @brief Function for getting RTS pin selection.
574 *
575 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
576 *
577 * @return RTS pin selection.
578 */
579 NRF_STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg);
580
581 /**
582 * @brief Function for configuring CTS pin.
583 *
584 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
585 * @param[in] pselcts CTS pin number.
586 */
587 NRF_STATIC_INLINE void nrf_uarte_cts_pin_set(NRF_UARTE_Type * p_reg, uint32_t pselcts);
588
589 /**
590 * @brief Function for getting CTS pin selection.
591 *
592 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
593 *
594 * @return CTS pin selection.
595 */
596 NRF_STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg);
597
598 /**
599 * @brief Function for configuring flow control pins.
600 *
601 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
602 * @param[in] pselrts RTS pin number.
603 * @param[in] pselcts CTS pin number.
604 */
605 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
606 uint32_t pselrts,
607 uint32_t pselcts);
608
609 /**
610 * @brief Function for disconnecting flow control pins.
611 *
612 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
613 */
614 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg);
615
616 /**
617 * @brief Function for starting an UARTE task.
618 *
619 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
620 * @param[in] task Task.
621 */
622 NRF_STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
623
624 /**
625 * @brief Function for returning the address of the specified task register.
626 *
627 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
628 * @param[in] task Task.
629 *
630 * @return Task address.
631 */
632 NRF_STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type const * p_reg,
633 nrf_uarte_task_t task);
634
635 /**
636 * @brief Function for configuring UARTE.
637 *
638 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
639 * @param[in] p_cfg Pointer to UARTE settings structure.
640 */
641 NRF_STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
642 nrf_uarte_config_t const * p_cfg);
643
644 /**
645 * @brief Function for setting UARTE baud rate.
646 *
647 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
648 * @param[in] baudrate Baud rate.
649 */
650 NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg,
651 nrf_uarte_baudrate_t baudrate);
652
653 /**
654 * @brief Function for setting the transmit buffer.
655 *
656 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
657 * @param[in] p_buffer Pointer to the buffer with data to send.
658 * @param[in] length Maximum number of data bytes to transmit.
659 */
660 NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
661 uint8_t const * p_buffer,
662 size_t length);
663
664 /**
665 * @brief Function for getting the transmit buffer address.
666 *
667 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
668 *
669 * @return Pointer to the transmit buffer.
670 */
671 NRF_STATIC_INLINE uint8_t const * nrf_uarte_tx_buffer_get(NRF_UARTE_Type * p_reg);
672
673 /**
674 * @brief Function for getting number of bytes transmitted in the last transaction.
675 *
676 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
677 *
678 * @retval Amount of bytes transmitted.
679 */
680 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg);
681
682 /**
683 * @brief Function for setting the receive buffer.
684 *
685 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
686 * @param[in] p_buffer Pointer to the buffer for received data.
687 * @param[in] length Maximum number of data bytes to receive.
688 */
689 NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
690 uint8_t * p_buffer,
691 size_t length);
692
693 /**
694 * @brief Function for getting the reception buffer address.
695 *
696 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
697 *
698 * @return Pointer to the reception buffer.
699 */
700 NRF_STATIC_INLINE uint8_t * nrf_uarte_rx_buffer_get(NRF_UARTE_Type * p_reg);
701
702 /**
703 * @brief Function for getting number of bytes received in the last transaction.
704 *
705 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
706 *
707 * @retval Amount of bytes received.
708 */
709 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg);
710
711 #if NRF_UARTE_HAS_FRAME_TIMEOUT
712 /**
713 * @brief Function for setting frame timeout.
714 *
715 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
716 * @param[in] timeout Frame timeout in bits.
717 */
718 NRF_STATIC_INLINE void nrf_uarte_frame_timeout_set(NRF_UARTE_Type * p_reg, uint32_t timeout);
719 #endif
720
721 #ifndef NRF_DECLARE_ONLY
nrf_uarte_event_clear(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)722 NRF_STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
723 {
724 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
725 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
726 }
727
nrf_uarte_event_check(NRF_UARTE_Type const * p_reg,nrf_uarte_event_t event)728 NRF_STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type const * p_reg,
729 nrf_uarte_event_t event)
730 {
731 return nrf_event_check(p_reg, event);
732 }
733
nrf_uarte_event_address_get(NRF_UARTE_Type const * p_reg,nrf_uarte_event_t event)734 NRF_STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type const * p_reg,
735 nrf_uarte_event_t event)
736 {
737 return nrf_task_event_address_get(p_reg, event);
738 }
739
nrf_uarte_shorts_set(NRF_UARTE_Type * p_reg,uint32_t mask)740 NRF_STATIC_INLINE void nrf_uarte_shorts_set(NRF_UARTE_Type * p_reg, uint32_t mask)
741 {
742 p_reg->SHORTS = mask;
743 }
744
nrf_uarte_shorts_get(NRF_UARTE_Type * p_reg,uint32_t mask)745 NRF_STATIC_INLINE uint32_t nrf_uarte_shorts_get(NRF_UARTE_Type * p_reg, uint32_t mask)
746 {
747 return p_reg->SHORTS & mask;
748 }
749
nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg,uint32_t mask)750 NRF_STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
751 {
752 p_reg->SHORTS |= mask;
753 }
754
nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg,uint32_t mask)755 NRF_STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
756 {
757 p_reg->SHORTS &= ~(mask);
758 }
759
nrf_uarte_int_enable(NRF_UARTE_Type * p_reg,uint32_t mask)760 NRF_STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
761 {
762 p_reg->INTENSET = mask;
763 }
764
nrf_uarte_int_enable_check(NRF_UARTE_Type const * p_reg,uint32_t mask)765 NRF_STATIC_INLINE uint32_t nrf_uarte_int_enable_check(NRF_UARTE_Type const * p_reg, uint32_t mask)
766 {
767 return p_reg->INTENSET & mask;
768 }
769
nrf_uarte_int_disable(NRF_UARTE_Type * p_reg,uint32_t mask)770 NRF_STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
771 {
772 p_reg->INTENCLR = mask;
773 }
774
775 #if defined(DPPI_PRESENT)
nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task,uint8_t channel)776 NRF_STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
777 nrf_uarte_task_t task,
778 uint8_t channel)
779 {
780 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
781 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
782 }
783
nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)784 NRF_STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,
785 nrf_uarte_task_t task)
786 {
787 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
788 }
789
nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event,uint8_t channel)790 NRF_STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,
791 nrf_uarte_event_t event,
792 uint8_t channel)
793 {
794 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
795 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
796 }
797
nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)798 NRF_STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,
799 nrf_uarte_event_t event)
800 {
801 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
802 }
803 #endif // defined(DPPI_PRESENT)
804
nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)805 NRF_STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)
806 {
807 uint32_t errsrc_mask = p_reg->ERRORSRC;
808 p_reg->ERRORSRC = errsrc_mask;
809 return errsrc_mask;
810 }
811
nrf_uarte_errorsrc_get(NRF_UARTE_Type * p_reg)812 NRF_STATIC_INLINE uint32_t nrf_uarte_errorsrc_get(NRF_UARTE_Type * p_reg)
813 {
814 return p_reg->ERRORSRC;
815 }
816
nrf_uarte_errorsrc_clear(NRF_UARTE_Type * p_reg,uint32_t errsrc_mask)817 NRF_STATIC_INLINE void nrf_uarte_errorsrc_clear(NRF_UARTE_Type * p_reg, uint32_t errsrc_mask)
818 {
819 p_reg->ERRORSRC = errsrc_mask;
820 }
821
nrf_uarte_enable(NRF_UARTE_Type * p_reg)822 NRF_STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg)
823 {
824 p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
825 }
826
nrf_uarte_disable(NRF_UARTE_Type * p_reg)827 NRF_STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg)
828 {
829 p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
830 }
831
nrf_uarte_enable_check(NRF_UARTE_Type const * p_reg)832 NRF_STATIC_INLINE bool nrf_uarte_enable_check(NRF_UARTE_Type const * p_reg)
833 {
834 return p_reg->ENABLE == UARTE_ENABLE_ENABLE_Enabled;
835 }
836
nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,uint32_t pseltxd,uint32_t pselrxd)837 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,
838 uint32_t pseltxd,
839 uint32_t pselrxd)
840 {
841 p_reg->PSEL.TXD = pseltxd;
842 p_reg->PSEL.RXD = pselrxd;
843 }
844
nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)845 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)
846 {
847 nrf_uarte_txrx_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
848 }
849
nrf_uarte_tx_pin_set(NRF_UARTE_Type * p_reg,uint32_t pseltxd)850 NRF_STATIC_INLINE void nrf_uarte_tx_pin_set(NRF_UARTE_Type * p_reg, uint32_t pseltxd)
851 {
852 p_reg->PSEL.TXD = pseltxd;
853 }
854
nrf_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg)855 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg)
856 {
857 return p_reg->PSEL.TXD;
858 }
859
nrf_uarte_rx_pin_set(NRF_UARTE_Type * p_reg,uint32_t pselrxd)860 NRF_STATIC_INLINE void nrf_uarte_rx_pin_set(NRF_UARTE_Type * p_reg, uint32_t pselrxd)
861 {
862 p_reg->PSEL.RXD = pselrxd;
863 }
864
nrf_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg)865 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg)
866 {
867 return p_reg->PSEL.RXD;
868 }
869
nrf_uarte_rts_pin_set(NRF_UARTE_Type * p_reg,uint32_t pselrts)870 NRF_STATIC_INLINE void nrf_uarte_rts_pin_set(NRF_UARTE_Type * p_reg, uint32_t pselrts)
871 {
872 p_reg->PSEL.RTS = pselrts;
873 }
874
nrf_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg)875 NRF_STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg)
876 {
877 return p_reg->PSEL.RTS;
878 }
879
nrf_uarte_cts_pin_set(NRF_UARTE_Type * p_reg,uint32_t pselcts)880 NRF_STATIC_INLINE void nrf_uarte_cts_pin_set(NRF_UARTE_Type * p_reg, uint32_t pselcts)
881 {
882 p_reg->PSEL.CTS = pselcts;
883 }
884
nrf_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg)885 NRF_STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg)
886 {
887 return p_reg->PSEL.CTS;
888 }
889
nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,uint32_t pselrts,uint32_t pselcts)890 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
891 uint32_t pselrts,
892 uint32_t pselcts)
893 {
894 p_reg->PSEL.RTS = pselrts;
895 p_reg->PSEL.CTS = pselcts;
896 }
897
nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)898 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)
899 {
900 nrf_uarte_hwfc_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
901 }
902
nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)903 NRF_STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
904 {
905 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
906 }
907
nrf_uarte_task_address_get(NRF_UARTE_Type const * p_reg,nrf_uarte_task_t task)908 NRF_STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type const * p_reg,
909 nrf_uarte_task_t task)
910 {
911 return (uint32_t)p_reg + (uint32_t)task;
912 }
913
nrf_uarte_configure(NRF_UARTE_Type * p_reg,nrf_uarte_config_t const * p_cfg)914 NRF_STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
915 nrf_uarte_config_t const * p_cfg)
916 {
917 p_reg->CONFIG = (uint32_t)p_cfg->parity
918 #if defined(UARTE_CONFIG_STOP_Msk)
919 | (uint32_t)p_cfg->stop
920 #endif
921 #if defined(UARTE_CONFIG_PARITYTYPE_Msk)
922 | (uint32_t)p_cfg->paritytype
923 #endif
924 #if NRF_UARTE_HAS_FRAME_TIMEOUT
925 | (uint32_t)p_cfg->frame_timeout
926 #endif
927 | (uint32_t)p_cfg->hwfc;
928 }
929
nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg,nrf_uarte_baudrate_t baudrate)930 NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
931 {
932 p_reg->BAUDRATE = baudrate;
933 }
934
nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,uint8_t const * p_buffer,size_t length)935 NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
936 uint8_t const * p_buffer,
937 size_t length)
938 {
939 #if NRF_UARTE_HAS_DMA_REG
940 p_reg->DMA.TX.PTR = (uint32_t)p_buffer;
941 p_reg->DMA.TX.MAXCNT = length;
942 #else
943 p_reg->TXD.PTR = (uint32_t)p_buffer;
944 p_reg->TXD.MAXCNT = length;
945 #endif
946 }
947
nrf_uarte_tx_buffer_get(NRF_UARTE_Type * p_reg)948 NRF_STATIC_INLINE uint8_t const * nrf_uarte_tx_buffer_get(NRF_UARTE_Type * p_reg)
949 {
950 #if NRF_UARTE_HAS_DMA_REG
951 return (uint8_t const *)p_reg->DMA.TX.PTR;
952 #else
953 return (uint8_t const *)p_reg->TXD.PTR;
954 #endif
955 }
956
nrf_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg)957 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg)
958 {
959 #if NRF_UARTE_HAS_DMA_REG
960 return p_reg->DMA.TX.AMOUNT;
961 #else
962 return p_reg->TXD.AMOUNT;
963 #endif
964 }
965
nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,uint8_t * p_buffer,size_t length)966 NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
967 uint8_t * p_buffer,
968 size_t length)
969 {
970 #if NRF_UARTE_HAS_DMA_REG
971 p_reg->DMA.RX.PTR = (uint32_t)p_buffer;
972 p_reg->DMA.RX.MAXCNT = length;
973 #else
974 p_reg->RXD.PTR = (uint32_t)p_buffer;
975 p_reg->RXD.MAXCNT = length;
976 #endif
977 }
978
nrf_uarte_rx_buffer_get(NRF_UARTE_Type * p_reg)979 NRF_STATIC_INLINE uint8_t * nrf_uarte_rx_buffer_get(NRF_UARTE_Type * p_reg)
980 {
981 #if NRF_UARTE_HAS_DMA_REG
982 return (uint8_t *)p_reg->DMA.RX.PTR;
983 #else
984 return (uint8_t *)p_reg->RXD.PTR;
985 #endif
986 }
987
nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)988 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)
989 {
990 #if NRF_UARTE_HAS_DMA_REG
991 return p_reg->DMA.RX.AMOUNT;
992 #else
993 return p_reg->RXD.AMOUNT;
994 #endif
995 }
996
997 #if NRF_UARTE_HAS_FRAME_TIMEOUT
nrf_uarte_frame_timeout_set(NRF_UARTE_Type * p_reg,uint32_t timeout)998 NRF_STATIC_INLINE void nrf_uarte_frame_timeout_set(NRF_UARTE_Type * p_reg, uint32_t timeout)
999 {
1000 p_reg->FRAMETIMEOUT = timeout;
1001 }
1002 #endif
1003
1004 #endif // NRF_DECLARE_ONLY
1005
1006 /** @} */
1007
1008 #ifdef __cplusplus
1009 }
1010 #endif
1011
1012 #endif // NRF_UARTE_H__
1013
