1 /*
2 * Copyright (c) 2015 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_SPIM_H__
35 #define NRF_SPIM_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if defined(HALTIUM_XXAA)
44 #define NRF_SPIM_CLOCKPIN_SCK_NEEDED
45 #endif
46
47 /*
48 * Macro for generating code blocks that allow extracting
49 * the maximum prescaler value allowed for the specified SPIM instance.
50 */
51 #define _NRF_SPIM_PRESCALER_MAX_GET(periph_name, prefix, idx, p_reg) \
52 (p_reg == NRFX_CONCAT(NRF_, periph_name, prefix, idx)) ? \
53 (NRFX_CONCAT(periph_name, prefix, idx, _PRESCALER_DIVISOR_RANGE_MAX)) :
54
55 /*
56 * Macro for generating code blocks that allow extracting
57 * the minimum prescaler value allowed for the specified SPIM instance.
58 */
59 #define _NRF_SPIM_PRESCALER_MIN_GET(periph_name, prefix, idx, p_reg) \
60 (p_reg == NRFX_CONCAT(NRF_, periph_name, prefix, idx)) ? \
61 (NRFX_CONCAT(periph_name, prefix, idx, _PRESCALER_DIVISOR_RANGE_MIN)) :
62
63 /**
64 * @defgroup nrf_spim_hal SPIM HAL
65 * @{
66 * @ingroup nrf_spim
67 * @brief Hardware access layer for managing the SPIM peripheral.
68 */
69
70 /**
71 * @brief Macro getting pointer to the structure of registers of the SPIM peripheral.
72 *
73 * @param[in] idx SPIM instance index.
74 *
75 * @return Pointer to the structure of registers of the SPIM peripheral.
76 */
77 #define NRF_SPIM_INST_GET(idx) NRFX_CONCAT(NRF_, SPIM, idx)
78
79 #if defined(SPIM_FREQUENCY_FREQUENCY_M16) || defined(__NRFX_DOXYGEN__)
80 /** @brief Symbol indicating whether 16 MHz clock frequency is available. */
81 #define NRF_SPIM_HAS_16_MHZ_FREQ 1
82 #else
83 #define NRF_SPIM_HAS_16_MHZ_FREQ 0
84 #endif
85
86 #if defined(SPIM_FREQUENCY_FREQUENCY_M32) || defined(__NRFX_DOXYGEN__)
87 /** @brief Symbol indicating whether 32 MHz clock frequency is available. */
88 #define NRF_SPIM_HAS_32_MHZ_FREQ 1
89 #else
90 #define NRF_SPIM_HAS_32_MHZ_FREQ 0
91 #endif
92
93 #if defined(SPIM_FREQUENCY_FREQUENCY_Msk) || defined(__NRFX_DOXYGEN__)
94 /** @brief Symbol indicating whether frequency is used. */
95 #define NRF_SPIM_HAS_FREQUENCY 1
96 #else
97 #define NRF_SPIM_HAS_FREQUENCY 0
98 #endif
99
100 #if defined(SPIM_PRESCALER_DIVISOR_Msk) || defined(__NRFX_DOXYGEN__)
101 /** @brief Symbol indicating whether prescaler is used. */
102 #define NRF_SPIM_HAS_PRESCALER 1
103 #else
104 #define NRF_SPIM_HAS_PRESCALER 0
105 #endif
106
107 #if defined(SPIM_TXD_LIST_LIST_ArrayList) || defined(__NRFX_DOXYGEN__)
108 /** @brief Symbol indicating whether EasyDMA array list feature is present. */
109 #define NRF_SPIM_HAS_ARRAY_LIST 1
110 #else
111 #define NRF_SPIM_HAS_ARRAY_LIST 0
112 #endif
113
114 #if defined(SPIM_DMA_RX_PTR_PTR_Msk) || defined(__NRFX_DOXYGEN__)
115 /** @brief Symbol indicating whether dedicated DMA register is present. */
116 #define NRF_SPIM_HAS_DMA_REG 1
117 #else
118 #define NRF_SPIM_HAS_DMA_REG 0
119 #endif
120
121 #if (defined(SPIM_TASKS_DMA_RX_ENABLEMATCH_ENABLEMATCH_Msk) && \
122 defined(SPIM_EVENTS_DMA_RX_END_END_Msk)) || \
123 defined(__NRFX_DOXYGEN__)
124 /** @brief Symbol indicating whether SPIM DMA tasks and events are present. */
125 #define NRF_SPIM_HAS_DMA_TASKS_EVENTS 1
126 #else
127 #define NRF_SPIM_HAS_DMA_TASKS_EVENTS 0
128 #endif
129
130 /** @brief Macro for checking if the hardware chip select function is available. */
131 #if NRFX_FEATURE_PRESENT(SPIM, _FEATURE_HARDWARE_CSN_PRESENT) || defined(__NRFX_DOXYGEN__)
132 #define NRF_SPIM_HAS_HW_CSN 1
133 #else
134 #define NRF_SPIM_HAS_HW_CSN 0
135 #endif
136
137 /** @brief Macro for checking if the DCX pin control is available. */
138 #if NRFX_FEATURE_PRESENT(SPIM, _FEATURE_HARDWARE_DCX_PRESENT) || \
139 NRFX_FEATURE_PRESENT(SPIM, _FEATURE_DCX_PRESENT) || \
140 defined(__NRFX_DOXYGEN__)
141 #define NRF_SPIM_HAS_DCX 1
142 #else
143 #define NRF_SPIM_HAS_DCX 0
144 #endif
145
146 /** @brief Macro for checking if the RXDELAY function is available. */
147 #if NRFX_FEATURE_PRESENT(SPIM, _FEATURE_RXDELAY_PRESENT) || defined(__NRFX_DOXYGEN__)
148 #define NRF_SPIM_HAS_RXDELAY 1
149 #else
150 #define NRF_SPIM_HAS_RXDELAY 0
151 #endif
152
153 #if defined(SPIM_STALLSTAT_RX_Msk) || defined(__NRFX_DOXYGEN__)
154 /** @brief Macro for checking if the STALLSTAT feature is available. */
155 #define NRF_SPIM_HAS_STALLSTAT 1
156 #else
157 #define NRF_SPIM_HAS_STALLSTAT 0
158 #endif
159
160 #if NRF_SPIM_HAS_HW_CSN || NRF_SPIM_HAS_DCX || NRF_SPIM_HAS_RXDELAY
161 /** @brief Symbol indicating whether any of the SPIM extended features is available. */
162 #define NRF_SPIM_HAS_EXTENDED 1
163 #else
164 #define NRF_SPIM_HAS_EXTENDED 0
165 #endif
166
167 #if NRF_SPIM_HAS_DCX
168 /**
169 * @brief This value specified in the DCX line configuration causes this line
170 * to be set low during whole transmission (all transmitted bytes are
171 * marked as command bytes). Any lower value causes the DCX line to be
172 * switched from low to high after this number of bytes is transmitted
173 * (all remaining bytes are marked as data bytes).
174 */
175 #define NRF_SPIM_DCX_CNT_ALL_CMD 0xF
176 #endif
177
178 /**
179 * @brief This value can be used as a parameter for the @ref nrf_spim_pins_set
180 * function to specify that a given SPI signal (SCK, MOSI, or MISO)
181 * shall not be connected to a physical pin.
182 */
183 #define NRF_SPIM_PIN_NOT_CONNECTED 0xFFFFFFFF
184
185 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
186 /** @brief Max number of RX patterns. */
187 #define NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT SPIM_DMA_RX_MATCH_CANDIDATE_MaxCount
188 #endif
189
190 /** @brief Minimal SPIM frequency in Hz. */
191 #define NRF_SPIM_MIN_FREQUENCY (NRFX_KHZ_TO_HZ(125UL))
192
193 /** @brief Base frequency value 320 MHz for SPIM. */
194 #define NRF_SPIM_BASE_FREQUENCY_320MHZ (NRFX_MHZ_TO_HZ(320UL))
195
196 /** @brief Base frequency value 192 MHz for SPIM. */
197 #define NRF_SPIM_BASE_FREQUENCY_192MHZ (NRFX_MHZ_TO_HZ(192UL))
198
199 /** @brief Base frequency value 128 MHz for SPIM. */
200 #define NRF_SPIM_BASE_FREQUENCY_128MHZ (NRFX_MHZ_TO_HZ(128UL))
201
202 /** @brief Base frequency value 64 MHz for SPIM. */
203 #define NRF_SPIM_BASE_FREQUENCY_64MHZ (NRFX_MHZ_TO_HZ(64UL))
204
205 /** @brief Base frequency value 32 MHz for SPIM. */
206 #define NRF_SPIM_BASE_FREQUENCY_32MHZ (NRFX_MHZ_TO_HZ(32UL))
207
208 /** @brief Base frequency value 16 MHz for SPIM. */
209 #define NRF_SPIM_BASE_FREQUENCY_16MHZ (NRFX_MHZ_TO_HZ(16UL))
210
211 #if !defined(NRF_SPIM_IS_320MHZ_SPIM)
212 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 320 MHz. */
213 #define NRF_SPIM_IS_320MHZ_SPIM(p_reg) \
214 (NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(SPIM120), (p_reg == NRF_SPIM120), (false)) || \
215 NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(SPIM121), (p_reg == NRF_SPIM121), (false)))
216 #endif
217
218 #if !defined(NRF_SPIM_IS_192MHZ_SPIM)
219 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 192 MHz. */
220 #define NRF_SPIM_IS_192MHZ_SPIM(p_reg) false
221 #endif
222
223 #if !defined(NRF_SPIM_IS_128MHZ_SPIM)
224 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 128 MHz. */
225 #define NRF_SPIM_IS_128MHZ_SPIM(p_reg) \
226 (NRFX_COND_CODE_1(NRFX_IS_ENABLED(NRF_CPU_FREQ_IS_128MHZ), \
227 (NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(SPIM00), (p_reg == NRF_SPIM00), (false))), \
228 (false)))
229 #endif
230
231 #if !defined(NRF_SPIM_IS_64MHZ_SPIM)
232 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 64 MHz. */
233 #define NRF_SPIM_IS_64MHZ_SPIM(p_reg) \
234 (NRFX_COND_CODE_1(NRFX_IS_ENABLED(NRF_CPU_FREQ_IS_64MHZ), \
235 (NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(SPIM00), (p_reg == NRF_SPIM00), (false))), \
236 (false)))
237 #endif
238
239 #if !defined(NRF_SPIM_IS_32MHZ_SPIM)
240 /** @brief Macro for checking whether the base frequency for the specified SPIM instance is 32 MHz. */
241 #define NRF_SPIM_IS_32MHZ_SPIM(p_reg) false
242 #endif
243
244 /** @brief Macro for getting base frequency value in Hz for the specified SPIM instance. */
245 #define NRF_SPIM_BASE_FREQUENCY_GET(p_reg) \
246 ((NRF_SPIM_IS_320MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_320MHZ) : \
247 ((NRF_SPIM_IS_192MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_192MHZ) : \
248 ((NRF_SPIM_IS_128MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_128MHZ) : \
249 ((NRF_SPIM_IS_64MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_64MHZ) : \
250 ((NRF_SPIM_IS_32MHZ_SPIM(p_reg)) ? (NRF_SPIM_BASE_FREQUENCY_32MHZ) : \
251 (NRF_SPIM_BASE_FREQUENCY_16MHZ))))))
252
253 #if NRF_SPIM_HAS_PRESCALER
254 /**
255 * @brief Macro for getting the maximum value of PRESCALER register.
256 *
257 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
258 */
259 #define NRF_SPIM_PRESCALER_MAX_GET(p_reg) \
260 (NRFX_FOREACH_ENABLED(SPIM, _NRF_SPIM_PRESCALER_MAX_GET, (), (), p_reg) \
261 SPIM_PRESCALER_DIVISOR_Max)
262
263 /**
264 * @brief Macro for getting the minimum value of PRESCALER register.
265 *
266 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
267 */
268 #define NRF_SPIM_PRESCALER_MIN_GET(p_reg) \
269 (NRFX_FOREACH_ENABLED(SPIM, _NRF_SPIM_PRESCALER_MIN_GET, (), (), p_reg) \
270 SPIM_PRESCALER_DIVISOR_Min)
271
272 /**
273 * @brief Macro for computing prescaler value for a given SPIM instance and desired frequency.
274 *
275 * @warning Not every combination of base and desired frequency is supported.
276 * The @ref NRF_SPIM_FREQUENCY_STATIC_CHECK macro can be used to check if the desired frequency is supported.
277 *
278 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
279 * @param[in] frequency Desired frequency value in Hz.
280 */
281 #define NRF_SPIM_PRESCALER_CALCULATE(p_reg, frequency) \
282 ((uint32_t)(NRF_SPIM_BASE_FREQUENCY_GET(p_reg)) / (uint32_t)(frequency))
283 #endif
284
285 /**
286 * @brief Macro for checking whether specified frequency can be achieved for a given SPIM instance.
287 *
288 * @note This macro uses a compile-time assertion.
289 *
290 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
291 * @param[in] frequency Desired frequency value in Hz.
292 */
293 #define NRF_SPIM_FREQUENCY_STATIC_CHECK(p_reg, frequency) \
294 NRFX_STATIC_ASSERT( \
295 NRFX_COND_CODE_1(NRF_SPIM_HAS_PRESCALER, \
296 ((NRF_SPIM_BASE_FREQUENCY_GET(p_reg) % (uint32_t)frequency == 0) && \
297 (NRFX_IS_EVEN(NRF_SPIM_PRESCALER_CALCULATE(p_reg, (uint32_t)frequency))) && \
298 (NRF_SPIM_PRESCALER_CALCULATE(p_reg, (uint32_t)frequency) >= (NRF_SPIM_PRESCALER_MIN_GET(p_reg))) && \
299 (NRF_SPIM_PRESCALER_CALCULATE(p_reg, (uint32_t)frequency) <= (NRF_SPIM_PRESCALER_MAX_GET(p_reg)))) \
300 , \
301 (((uint32_t)frequency == (uint32_t)NRFX_KHZ_TO_HZ(125)) || \
302 ((uint32_t)frequency == (uint32_t)NRFX_KHZ_TO_HZ(250)) || \
303 ((uint32_t)frequency == (uint32_t)NRFX_KHZ_TO_HZ(500)) || \
304 ((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(1)) || \
305 ((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(2)) || \
306 ((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(4)) || \
307 ((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(8)) || \
308 (((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(16)) && (NRF_SPIM_HAS_16_MHZ_FREQ)) || \
309 (((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(32)) && (NRF_SPIM_HAS_32_MHZ_FREQ)))))
310
311 /** @brief SPIM tasks. */
312 typedef enum
313 {
314 NRF_SPIM_TASK_START = offsetof(NRF_SPIM_Type, TASKS_START), ///< Start SPI transaction.
315 NRF_SPIM_TASK_STOP = offsetof(NRF_SPIM_Type, TASKS_STOP), ///< Stop SPI transaction.
316 NRF_SPIM_TASK_SUSPEND = offsetof(NRF_SPIM_Type, TASKS_SUSPEND), ///< Suspend SPI transaction.
317 NRF_SPIM_TASK_RESUME = offsetof(NRF_SPIM_Type, TASKS_RESUME), ///< Resume SPI transaction.
318 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
319 NRF_SPIM_TASK_ENABLERXMATCH0 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.ENABLEMATCH[0]), ///< Enable SPI pattern matching functionality for pattern 0.
320 NRF_SPIM_TASK_ENABLERXMATCH1 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.ENABLEMATCH[1]), ///< Enable SPI pattern matching functionality for pattern 1.
321 NRF_SPIM_TASK_ENABLERXMATCH2 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.ENABLEMATCH[2]), ///< Enable SPI pattern matching functionality for pattern 2.
322 NRF_SPIM_TASK_ENABLERXMATCH3 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.ENABLEMATCH[3]), ///< Enable SPI pattern matching functionality for pattern 3.
323 NRF_SPIM_TASK_DISABLERXMATCH0 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.DISABLEMATCH[0]), ///< Disable SPI pattern matching functionality for pattern 0.
324 NRF_SPIM_TASK_DISABLERXMATCH1 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.DISABLEMATCH[1]), ///< Disable SPI pattern matching functionality for pattern 1.
325 NRF_SPIM_TASK_DISABLERXMATCH2 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.DISABLEMATCH[2]), ///< Disable SPI pattern matching functionality for pattern 2.
326 NRF_SPIM_TASK_DISABLERXMATCH3 = offsetof(NRF_SPIM_Type, TASKS_DMA.RX.DISABLEMATCH[3]) ///< Disable SPI pattern matching functionality for pattern 3.
327 #endif
328 } nrf_spim_task_t;
329
330 /** @brief SPIM events. */
331 typedef enum
332 {
333 NRF_SPIM_EVENT_STARTED = offsetof(NRF_SPIM_Type, EVENTS_STARTED), ///< SPI transaction has started.
334 NRF_SPIM_EVENT_STOPPED = offsetof(NRF_SPIM_Type, EVENTS_STOPPED), ///< SPI transaction has stopped.
335 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
336 NRF_SPIM_EVENT_RXSTARTED = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.READY), ///< Receive sequence started.
337 NRF_SPIM_EVENT_RXBUSERROR = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.BUSERROR), ///< Memory bus error occurred during the RX transfer.
338 NRF_SPIM_EVENT_RXMATCH0 = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.MATCH[0]), ///< Pattern match for pattern 0 detected.
339 NRF_SPIM_EVENT_RXMATCH1 = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.MATCH[1]), ///< Pattern match for pattern 1 detected.
340 NRF_SPIM_EVENT_RXMATCH2 = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.MATCH[2]), ///< Pattern match for pattern 2 detected.
341 NRF_SPIM_EVENT_RXMATCH3 = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.MATCH[3]), ///< Pattern match for pattern 3 detected.
342 NRF_SPIM_EVENT_TXSTARTED = offsetof(NRF_SPIM_Type, EVENTS_DMA.TX.READY), ///< Transmit sequence started.
343 NRF_SPIM_EVENT_TXBUSERROR = offsetof(NRF_SPIM_Type, EVENTS_DMA.TX.BUSERROR), ///< Memory bus error occurred during the TX transfer.
344 NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_DMA.RX.END), ///< End of RXD buffer reached.
345 NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_DMA.TX.END), ///< End of TXD buffer reached.
346 #else
347 NRF_SPIM_EVENT_ENDRX = offsetof(NRF_SPIM_Type, EVENTS_ENDRX), ///< End of RXD buffer reached.
348 NRF_SPIM_EVENT_ENDTX = offsetof(NRF_SPIM_Type, EVENTS_ENDTX), ///< End of TXD buffer reached.
349 #endif
350 NRF_SPIM_EVENT_END = offsetof(NRF_SPIM_Type, EVENTS_END) ///< End of RXD buffer and TXD buffer reached.
351 } nrf_spim_event_t;
352
353 /** @brief SPIM shortcuts. */
354 typedef enum
355 {
356 NRF_SPIM_SHORT_END_START_MASK = SPIM_SHORTS_END_START_Msk, ///< Shortcut between END event and START task.
357 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
358 NRF_SPIM_SHORT_RXMATCH0_ENABLERXMATCH1_MASK = SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.ENABLEMATCH1 task.
359 NRF_SPIM_SHORT_RXMATCH1_ENABLERXMATCH2_MASK = SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.ENABLEMATCH2 task.
360 NRF_SPIM_SHORT_RXMATCH2_ENABLERXMATCH3_MASK = SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.ENABLEMATCH3 task.
361 NRF_SPIM_SHORT_RXMATCH3_ENABLERXMATCH0_MASK = SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.ENABLEMATCH4 task.
362 NRF_SPIM_SHORT_RXMATCH0_DISABLERXMATCH0_MASK = SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.DISABLEMATCH0 task.
363 NRF_SPIM_SHORT_RXMATCH1_DISABLERXMATCH1_MASK = SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.DISABLEMATCH1 task.
364 NRF_SPIM_SHORT_RXMATCH2_DISABLERXMATCH2_MASK = SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.DISABLEMATCH2 task.
365 NRF_SPIM_SHORT_RXMATCH3_DISABLERXMATCH3_MASK = SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.DISABLEMATCH3 task.
366 #endif
367 NRF_SPIM_ALL_SHORTS_MASK = SPIM_SHORTS_END_START_Msk
368 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
369 | SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk
370 | SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk
371 | SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk
372 | SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk
373 | SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk
374 | SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk
375 | SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk
376 | SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_DISABLEMATCH3_Msk ///< All SPIM shortcuts.
377 #endif
378 } nrf_spim_short_mask_t;
379
380 /** @brief SPIM interrupts. */
381 typedef enum
382 {
383 NRF_SPIM_INT_STARTED_MASK = SPIM_INTENSET_STARTED_Msk, ///< Interrupt on STARTED event.
384 NRF_SPIM_INT_STOPPED_MASK = SPIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
385 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
386 NRF_SPIM_INT_RXREADY_MASK = SPIM_INTENSET_DMARXREADY_Msk, ///< Interrupt on DMA.RX.READY event.
387 NRF_SPIM_INT_RXBUSERROR_MASK = SPIM_INTENSET_DMARXBUSERROR_Msk, ///< Interrupt on DMA.RX.BUSERROR event.
388 NRF_SPIM_INT_RXMATCH0_MASK = SPIM_INTENSET_DMARXMATCH0_Msk, ///< Interrupt on DMA.RX.MATCH0 event.
389 NRF_SPIM_INT_RXMATCH1_MASK = SPIM_INTENSET_DMARXMATCH1_Msk, ///< Interrupt on DMA.RX.MATCH1 event.
390 NRF_SPIM_INT_RXMATCH2_MASK = SPIM_INTENSET_DMARXMATCH2_Msk, ///< Interrupt on DMA.RX.MATCH2 event.
391 NRF_SPIM_INT_RXMATCH3_MASK = SPIM_INTENSET_DMARXMATCH3_Msk, ///< Interrupt on DMA.RX.MATCH3 event.
392 NRF_SPIM_INT_TXREADY_MASK = SPIM_INTENSET_DMATXREADY_Msk, ///< Interrupt on DMA.TX.READY event.
393 NRF_SPIM_INT_TXBUSERROR_MASK = SPIM_INTENSET_DMATXBUSERROR_Msk, ///< Interrupt on DMA.TX.BUSERROR event.
394 NRF_SPIM_INT_ENDRX_MASK = SPIM_INTENSET_DMARXEND_Msk, ///< Interrupt on ENDRX event.
395 NRF_SPIM_INT_ENDTX_MASK = SPIM_INTENSET_DMATXEND_Msk, ///< Interrupt on ENDTX event.
396 #else
397 NRF_SPIM_INT_ENDRX_MASK = SPIM_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
398 NRF_SPIM_INT_ENDTX_MASK = SPIM_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
399 #endif
400 NRF_SPIM_INT_END_MASK = SPIM_INTENSET_END_Msk, ///< Interrupt on END event.
401 NRF_SPIM_ALL_INTS_MASK = NRF_SPIM_INT_STARTED_MASK
402 | NRF_SPIM_INT_STOPPED_MASK
403 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
404 | NRF_SPIM_INT_RXREADY_MASK
405 | NRF_SPIM_INT_RXBUSERROR_MASK
406 | NRF_SPIM_INT_RXMATCH0_MASK
407 | NRF_SPIM_INT_RXMATCH1_MASK
408 | NRF_SPIM_INT_RXMATCH2_MASK
409 | NRF_SPIM_INT_RXMATCH3_MASK
410 | NRF_SPIM_INT_TXREADY_MASK
411 | NRF_SPIM_INT_TXBUSERROR_MASK
412 #endif
413 | NRF_SPIM_INT_ENDRX_MASK
414 | NRF_SPIM_INT_ENDTX_MASK
415 | NRF_SPIM_INT_END_MASK ///< All SPIM interrupts.
416 } nrf_spim_int_mask_t;
417
418 #if NRF_SPIM_HAS_FREQUENCY
419 /** @brief SPI master data rates. */
420 typedef enum
421 {
422 NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125, ///< 125 kbps.
423 NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
424 NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500, ///< 500 kbps.
425 NRF_SPIM_FREQ_1M = SPIM_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps.
426 NRF_SPIM_FREQ_2M = SPIM_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps.
427 NRF_SPIM_FREQ_4M = SPIM_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps.
428 // Conversion to int is needed to prevent compilers from getting an error message
429 // that the provided value (0x80000000UL) is out of range for int.
430 NRF_SPIM_FREQ_8M = (int)SPIM_FREQUENCY_FREQUENCY_M8, ///< 8 Mbps.
431 #if NRF_SPIM_HAS_16_MHZ_FREQ
432 NRF_SPIM_FREQ_16M = SPIM_FREQUENCY_FREQUENCY_M16, ///< 16 Mbps.
433 #endif
434 #if NRF_SPIM_HAS_32_MHZ_FREQ
435 NRF_SPIM_FREQ_32M = SPIM_FREQUENCY_FREQUENCY_M32 ///< 32 Mbps.
436 #endif
437 } nrf_spim_frequency_t;
438 #endif // NRF_SPIM_HAS_FREQUENCY
439
440 /** @brief SPI modes. */
441 typedef enum
442 {
443 NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock.
444 NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock.
445 NRF_SPIM_MODE_2, ///< SCK active low, sample on leading edge of clock.
446 NRF_SPIM_MODE_3 ///< SCK active low, sample on trailing edge of clock.
447 } nrf_spim_mode_t;
448
449 /** @brief SPI bit orders. */
450 typedef enum
451 {
452 NRF_SPIM_BIT_ORDER_MSB_FIRST = SPIM_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
453 NRF_SPIM_BIT_ORDER_LSB_FIRST = SPIM_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first.
454 } nrf_spim_bit_order_t;
455
456 #if NRF_SPIM_HAS_HW_CSN
457 /** @brief SPI CSN pin polarity. */
458 typedef enum
459 {
460 #if defined(SPIM_CSNPOL_CSNPOL0_LOW)
461 NRF_SPIM_CSN_POL_LOW = SPIM_CSNPOL_CSNPOL0_LOW, ///< Active low (idle state high).
462 NRF_SPIM_CSN_POL_HIGH = SPIM_CSNPOL_CSNPOL0_HIGH ///< Active high (idle state low).
463 #else
464 NRF_SPIM_CSN_POL_LOW = SPIM_CSNPOL_CSNPOL_LOW, ///< Active low (idle state high).
465 NRF_SPIM_CSN_POL_HIGH = SPIM_CSNPOL_CSNPOL_HIGH ///< Active high (idle state low).
466 #endif
467 } nrf_spim_csn_pol_t;
468 #endif
469
470 /**
471 * @brief Function for activating the specified SPIM task.
472 *
473 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
474 * @param[in] task Task to be activated.
475 */
476 NRF_STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
477 nrf_spim_task_t task);
478
479 /**
480 * @brief Function for getting the address of the specified SPIM task register.
481 *
482 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
483 * @param[in] task The specified task.
484 *
485 * @return Address of the specified task register.
486 */
487 NRF_STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type const * p_reg,
488 nrf_spim_task_t task);
489
490 /**
491 * @brief Function for clearing the specified SPIM event.
492 *
493 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
494 * @param[in] event Event to be cleared.
495 */
496 NRF_STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
497 nrf_spim_event_t event);
498
499 /**
500 * @brief Function for retrieving the state of the SPIM event.
501 *
502 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
503 * @param[in] event Event to be checked.
504 *
505 * @retval true The event has been generated.
506 * @retval false The event has not been generated.
507 */
508 NRF_STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type const * p_reg,
509 nrf_spim_event_t event);
510
511 /**
512 * @brief Function for getting the address of the specified SPIM event register.
513 *
514 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
515 * @param[in] event The specified event.
516 *
517 * @return Address of the specified event register.
518 */
519 NRF_STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type const * p_reg,
520 nrf_spim_event_t event);
521
522 /**
523 * @brief Function for enabling the specified shortcuts.
524 *
525 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
526 * @param[in] mask Shortcuts to be enabled.
527 */
528 NRF_STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
529 uint32_t mask);
530
531 /**
532 * @brief Function for disabling the specified shortcuts.
533 *
534 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
535 * @param[in] mask Shortcuts to be disabled.
536 */
537 NRF_STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
538 uint32_t mask);
539
540 /**
541 * @brief Function for getting the shortcut setting.
542 *
543 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
544 *
545 * @return Current shortcut configuration.
546 */
547 NRF_STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type const * p_reg);
548
549 /**
550 * @brief Function for enabling the specified interrupts.
551 *
552 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
553 * @param[in] mask Mask of interrupts to be enabled.
554 * Use @ref nrf_spim_int_mask_t values for bit masking.
555 */
556 NRF_STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
557 uint32_t mask);
558
559 /**
560 * @brief Function for disabling the specified interrupts.
561 *
562 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
563 * @param[in] mask Mask of interrupts to be disabled.
564 * Use @ref nrf_spim_int_mask_t values for bit masking.
565 */
566 NRF_STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
567 uint32_t mask);
568
569 /**
570 * @brief Function for checking if the specified interrupts are enabled.
571 *
572 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
573 * @param[in] mask Mask of interrupts to be checked.
574 * Use @ref nrf_spim_int_mask_t values for bit masking.
575 *
576 * @return Mask of enabled interrupts.
577 */
578 NRF_STATIC_INLINE uint32_t nrf_spim_int_enable_check(NRF_SPIM_Type const * p_reg, uint32_t mask);
579
580 #if NRF_SPIM_HAS_PRESCALER
581 /**
582 * @brief Function for setting the prescaler value.
583 *
584 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
585 * @param[in] prescaler Prescaler value.
586 */
587 NRF_STATIC_INLINE void nrf_spim_prescaler_set(NRF_SPIM_Type * p_reg,
588 uint32_t prescaler);
589
590 /**
591 * @brief Function for getting the prescaler value.
592 *
593 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
594 *
595 * @return Prescaler value.
596 */
597 NRF_STATIC_INLINE uint32_t nrf_spim_prescaler_get(NRF_SPIM_Type const * p_reg);
598 #endif
599
600 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
601 /**
602 * @brief Function for setting the subscribe configuration for a given
603 * SPIM task.
604 *
605 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
606 * @param[in] task Task for which to set the configuration.
607 * @param[in] channel Channel through which to subscribe events.
608 */
609 NRF_STATIC_INLINE void nrf_spim_subscribe_set(NRF_SPIM_Type * p_reg,
610 nrf_spim_task_t task,
611 uint8_t channel);
612
613 /**
614 * @brief Function for clearing the subscribe configuration for a given
615 * SPIM task.
616 *
617 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
618 * @param[in] task Task for which to clear the configuration.
619 */
620 NRF_STATIC_INLINE void nrf_spim_subscribe_clear(NRF_SPIM_Type * p_reg,
621 nrf_spim_task_t task);
622
623 /**
624 * @brief Function for setting the publish configuration for a given
625 * SPIM event.
626 *
627 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
628 * @param[in] event Event for which to set the configuration.
629 * @param[in] channel Channel through which to publish the event.
630 */
631 NRF_STATIC_INLINE void nrf_spim_publish_set(NRF_SPIM_Type * p_reg,
632 nrf_spim_event_t event,
633 uint8_t channel);
634
635 /**
636 * @brief Function for clearing the publish configuration for a given
637 * SPIM event.
638 *
639 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
640 * @param[in] event Event for which to clear the configuration.
641 */
642 NRF_STATIC_INLINE void nrf_spim_publish_clear(NRF_SPIM_Type * p_reg,
643 nrf_spim_event_t event);
644 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
645
646 /**
647 * @brief Function for enabling the SPIM peripheral.
648 *
649 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
650 */
651 NRF_STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg);
652
653 /**
654 * @brief Function for disabling the SPIM peripheral.
655 *
656 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
657 */
658 NRF_STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg);
659
660 /**
661 * @brief Function for checking if the SPIM peripheral is enabled.
662 *
663 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
664 *
665 * @retval true The SPIM is enabled.
666 * @retval false The SPIM is not enabled.
667 */
668 NRF_STATIC_INLINE bool nrf_spim_enable_check(NRF_SPIM_Type const * p_reg);
669
670 /**
671 * @brief Function for configuring SPIM pins.
672 *
673 * If a given signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
674 * value instead of its pin number.
675 *
676 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
677 * @param[in] sck_pin SCK pin number.
678 * @param[in] mosi_pin MOSI pin number.
679 * @param[in] miso_pin MISO pin number.
680 */
681 NRF_STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
682 uint32_t sck_pin,
683 uint32_t mosi_pin,
684 uint32_t miso_pin);
685
686 /**
687 * @brief Function for getting the SCK pin selection.
688 *
689 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
690 *
691 * @return SCK pin selection.
692 */
693 NRF_STATIC_INLINE uint32_t nrf_spim_sck_pin_get(NRF_SPIM_Type const * p_reg);
694
695 /**
696 * @brief Function for getting the MOSI pin selection.
697 *
698 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
699 *
700 * @return MOSI pin selection.
701 */
702 NRF_STATIC_INLINE uint32_t nrf_spim_mosi_pin_get(NRF_SPIM_Type const * p_reg);
703
704 /**
705 * @brief Function for getting the MISO pin selection.
706 *
707 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
708 *
709 * @return MISO pin selection.
710 */
711 NRF_STATIC_INLINE uint32_t nrf_spim_miso_pin_get(NRF_SPIM_Type const * p_reg);
712
713 #if NRF_SPIM_HAS_HW_CSN
714 /**
715 * @brief Function for configuring the SPIM hardware CSN pin.
716 *
717 * If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
718 * value instead of its pin number.
719 *
720 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
721 * @param[in] pin CSN pin number.
722 * @param[in] polarity CSN pin polarity.
723 * @param[in] duration Minimum duration between the edge of CSN and the edge of SCK
724 * and minimum duration of CSN must stay unselected between transactions.
725 * The value is specified in number of 64 MHz clock cycles (15.625 ns).
726 */
727 NRF_STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
728 uint32_t pin,
729 nrf_spim_csn_pol_t polarity,
730 uint32_t duration);
731
732 /**
733 * @brief Function for getting the CSN pin selection.
734 *
735 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
736 *
737 * @return CSN pin selection.
738 */
739 NRF_STATIC_INLINE uint32_t nrf_spim_csn_pin_get(NRF_SPIM_Type const * p_reg);
740 #endif
741
742 #if NRF_SPIM_HAS_DCX
743 /**
744 * @brief Function for configuring the SPIM DCX pin.
745 *
746 * If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
747 * value instead of its pin number.
748 *
749 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
750 * @param[in] dcx_pin DCX pin number.
751 */
752 NRF_STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,
753 uint32_t dcx_pin);
754
755 /**
756 * @brief Function for getting the DCX pin selection.
757 *
758 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
759 *
760 * @return DCX pin selection.
761 */
762 NRF_STATIC_INLINE uint32_t nrf_spim_dcx_pin_get(NRF_SPIM_Type const * p_reg);
763
764 /**
765 * @brief Function for configuring the number of command bytes.
766 *
767 * Maximum value available for dividing the transmitted bytes into command
768 * bytes and data bytes is @ref NRF_SPIM_DCX_CNT_ALL_CMD - 1.
769 * The @ref NRF_SPIM_DCX_CNT_ALL_CMD value passed as the @c count parameter
770 * causes all transmitted bytes to be marked as command bytes.
771 *
772 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
773 * @param[in] count Number of command bytes preceding the data bytes.
774 */
775 NRF_STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg,
776 uint32_t count);
777 #endif // NRF_SPIM_HAS_DCX
778
779 #if NRF_SPIM_HAS_RXDELAY
780 /**
781 * @brief Function for configuring the extended SPIM interface.
782 *
783 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
784 * @param[in] rxdelay Sample delay for input serial data on MISO,
785 * specified in 64 MHz clock cycles (15.625 ns) from the sampling edge of SCK.
786 */
787 NRF_STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,
788 uint32_t rxdelay);
789 #endif
790
791 #if NRF_SPIM_HAS_STALLSTAT
792 /**
793 * @brief Function for clearing stall status for RX EasyDMA RAM accesses.
794 *
795 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
796 */
797 NRF_STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg);
798
799 /**
800 * @brief Function for getting stall status for RX EasyDMA RAM accesses.
801 *
802 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
803 *
804 * @return Stall status of RX EasyDMA RAM accesses.
805 */
806 NRF_STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type const * p_reg);
807
808 /**
809 * @brief Function for clearing stall status for TX EasyDMA RAM accesses.
810 *
811 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
812 */
813 NRF_STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg);
814
815 /**
816 * @brief Function for getting stall status for TX EasyDMA RAM accesses.
817 *
818 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
819 *
820 * @return Stall status of TX EasyDMA RAM accesses.
821 */
822 NRF_STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type const * p_reg);
823 #endif // NRF_SPIM_HAS_STALLSTAT
824
825 #if NRF_SPIM_HAS_FREQUENCY
826 /**
827 * @brief Function for setting the SPI master data rate.
828 *
829 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
830 * @param[in] frequency SPI frequency.
831 */
832 NRF_STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
833 nrf_spim_frequency_t frequency);
834
835 /**
836 * @brief Function for getting the SPI master data rate.
837 *
838 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
839 *
840 * @retval SPI master frequency.
841 */
842 NRF_STATIC_INLINE nrf_spim_frequency_t nrf_spim_frequency_get(NRF_SPIM_Type * p_reg);
843 #endif
844
845 /**
846 * @brief Function for setting the transmit buffer.
847 *
848 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
849 * @param[in] p_buffer Pointer to the buffer with data to send.
850 * @param[in] length Maximum number of data bytes to transmit.
851 */
852 NRF_STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
853 uint8_t const * p_buffer,
854 size_t length);
855
856 /**
857 * @brief Function for getting number of bytes transmitted in the last transaction.
858 *
859 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
860 *
861 * @retval Amount of bytes transmitted.
862 */
863 NRF_STATIC_INLINE uint32_t nrf_spim_tx_amount_get(NRF_SPIM_Type const * p_reg);
864
865 /**
866 * @brief Function for getting number of bytes to be transmitted in the next transaction.
867 *
868 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
869 *
870 * @retval Amount of bytes to be transmitted.
871 */
872 NRF_STATIC_INLINE uint32_t nrf_spim_tx_maxcnt_get(NRF_SPIM_Type const * p_reg);
873
874 /**
875 * @brief Function for setting the receive buffer.
876 *
877 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
878 * @param[in] p_buffer Pointer to the buffer for received data.
879 * @param[in] length Maximum number of data bytes to receive.
880 */
881 NRF_STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
882 uint8_t * p_buffer,
883 size_t length);
884
885 /**
886 * @brief Function for getting number of bytes received in the last transaction.
887 *
888 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
889 *
890 * @retval Amount of bytes received.
891 */
892 NRF_STATIC_INLINE uint32_t nrf_spim_rx_amount_get(NRF_SPIM_Type const * p_reg);
893
894 /**
895 * @brief Function for getting number of bytes to be received in the next transaction.
896 *
897 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
898 *
899 * @retval Amount of bytes to be received.
900 */
901 NRF_STATIC_INLINE uint32_t nrf_spim_rx_maxcnt_get(NRF_SPIM_Type const * p_reg);
902
903 /**
904 * @brief Function for setting the SPI configuration.
905 *
906 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
907 * @param[in] spi_mode SPI mode.
908 * @param[in] spi_bit_order SPI bit order.
909 */
910 NRF_STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
911 nrf_spim_mode_t spi_mode,
912 nrf_spim_bit_order_t spi_bit_order);
913
914 /**
915 * @brief Function for setting the over-read character.
916 *
917 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
918 * @param[in] orc Over-read character that is clocked out in case of
919 * an over-read of the TXD buffer.
920 */
921 NRF_STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
922 uint8_t orc);
923
924 #if NRF_SPIM_HAS_ARRAY_LIST
925 /**
926 * @brief Function for enabling the TX list feature.
927 *
928 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
929 */
930 NRF_STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg);
931
932 /**
933 * @brief Function for disabling the TX list feature.
934 *
935 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
936 */
937 NRF_STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg);
938
939 /**
940 * @brief Function for enabling the RX list feature.
941 *
942 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
943 */
944 NRF_STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg);
945
946 /**
947 * @brief Function for disabling the RX list feature.
948 *
949 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
950 */
951 NRF_STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg);
952 #endif
953
954 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
955 /**
956 * @brief Function for enabling individual pattern match filters.
957 *
958 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
959 * @param[in] index Index of pattern match filter.
960 * @param[in] enable True if pattern match filter is to be enabled, false otherwise.
961 */
962 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_enable_set(NRF_SPIM_Type * p_reg,
963 uint8_t index,
964 bool enable);
965
966 /**
967 * @brief Function for checking if the specified pattern match filter is enabled.
968 *
969 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
970 * @param[in] index Index of pattern match filter.
971 *
972 * @retval true Pattern match filter is enabled.
973 * @retval false Pattern match filter is disabled.
974 */
975 NRF_STATIC_INLINE bool nrf_spim_rx_pattern_match_enable_check(NRF_SPIM_Type const * p_reg,
976 uint8_t index);
977
978 /**
979 * @brief Function for enabling one-shot operation for the specified match filter.
980 *
981 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
982 * @param[in] index Index of pattern match filter.
983 */
984 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_one_shot_enable(NRF_SPIM_Type * p_reg,
985 uint8_t index);
986
987 /**
988 * @brief Function for disabling one-shot operation for the specified match filter.
989 *
990 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
991 * @param[in] index Index of pattern match filter.
992 */
993 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_one_shot_disable(NRF_SPIM_Type * p_reg,
994 uint8_t index);
995
996 /**
997 * @brief Function for checking if specified pattern match filter is configured as one-shot.
998 *
999 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1000 * @param[in] index Index of pattern match filter.
1001 *
1002 * @retval true Pattern match filter is configured as one-shot.
1003 * @retval false Pattern match filter is configured as continuous.
1004 */
1005 NRF_STATIC_INLINE bool nrf_spim_rx_pattern_match_one_shot_check(NRF_SPIM_Type const * p_reg,
1006 uint8_t index);
1007
1008 /**
1009 * @brief Function for setting the pattern to be looked for by the specified match filter.
1010 *
1011 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1012 * @param[in] index Index of pattern match filter.
1013 * @param[in] pattern Pattern to be looked for.
1014 * Match will trigger the corresponding event, if enabled.
1015 */
1016 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_candidate_set(NRF_SPIM_Type * p_reg,
1017 uint8_t index,
1018 uint32_t pattern);
1019
1020 /**
1021 * @brief Function for getting the pattern that the specified match filter is looking for.
1022 *
1023 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1024 * @param[in] index Index of pattern match filter.
1025 *
1026 * @return Pattern that the specified match filter is looking for.
1027 */
1028 NRF_STATIC_INLINE uint32_t nrf_spim_rx_pattern_match_candidate_get(NRF_SPIM_Type const * p_reg,
1029 uint8_t index);
1030 #endif // NRF_SPIM_HAS_DMA_TASKS_EVENTS
1031
1032 #if NRF_SPIM_HAS_DMA_REG
1033 /**
1034 * @brief Function for enabling the termination of the RX transaction after detecting the BUSERROR event.
1035 *
1036 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1037 */
1038 NRF_STATIC_INLINE void nrf_spim_rx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg);
1039
1040 /**
1041 * @brief Function for disabling the termination of the RX transaction after detecting the BUSERROR event.
1042 *
1043 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1044 */
1045 NRF_STATIC_INLINE void nrf_spim_rx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg);
1046
1047 /**
1048 * @brief Function for checking if RX transaction termination after detecting the BUSERROR event is enabled.
1049 *
1050 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1051 *
1052 * @retval true RX transaction termination after detecting a BUSERROR event is enabled.
1053 * @retval false RX transaction termination after detecting a BUSERROR event is disabled.
1054 */
1055 NRF_STATIC_INLINE bool nrf_spim_rx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg);
1056
1057 /**
1058 * @brief Function for enabling the termination of the TX transaction after detecting the BUSERROR event.
1059 *
1060 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1061 */
1062 NRF_STATIC_INLINE void nrf_spim_tx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg);
1063
1064 /**
1065 * @brief Function for disabling the termination of the TX transaction after detecting the BUSERROR event.
1066 *
1067 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1068 */
1069 NRF_STATIC_INLINE void nrf_spim_tx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg);
1070
1071 /**
1072 * @brief Function for checking if TX transaction termination after detecting the BUSERROR event is enabled.
1073 *
1074 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
1075 *
1076 * @retval true TX transaction termination after detecting a BUSERROR event is enabled.
1077 * @retval false TX transaction termination after detecting a BUSERROR event is disabled.
1078 */
1079 NRF_STATIC_INLINE bool nrf_spim_tx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg);
1080 #endif // NRF_SPIM_HAS_DMA_REG
1081
1082 #ifndef NRF_DECLARE_ONLY
1083
nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,nrf_spim_task_t task)1084 NRF_STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_reg,
1085 nrf_spim_task_t task)
1086 {
1087 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
1088 }
1089
nrf_spim_task_address_get(NRF_SPIM_Type const * p_reg,nrf_spim_task_t task)1090 NRF_STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type const * p_reg,
1091 nrf_spim_task_t task)
1092 {
1093 return nrf_task_event_address_get(p_reg, task);
1094 }
1095
nrf_spim_event_clear(NRF_SPIM_Type * p_reg,nrf_spim_event_t event)1096 NRF_STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
1097 nrf_spim_event_t event)
1098 {
1099 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
1100 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
1101 }
1102
nrf_spim_event_check(NRF_SPIM_Type const * p_reg,nrf_spim_event_t event)1103 NRF_STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type const * p_reg,
1104 nrf_spim_event_t event)
1105 {
1106 return nrf_event_check(p_reg, event);
1107 }
1108
nrf_spim_event_address_get(NRF_SPIM_Type const * p_reg,nrf_spim_event_t event)1109 NRF_STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type const * p_reg,
1110 nrf_spim_event_t event)
1111 {
1112 return nrf_task_event_address_get(p_reg, event);
1113 }
1114
nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,uint32_t mask)1115 NRF_STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_reg,
1116 uint32_t mask)
1117 {
1118 p_reg->SHORTS |= mask;
1119 }
1120
nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,uint32_t mask)1121 NRF_STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_reg,
1122 uint32_t mask)
1123 {
1124 p_reg->SHORTS &= ~(mask);
1125 }
1126
nrf_spim_shorts_get(NRF_SPIM_Type const * p_reg)1127 NRF_STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type const * p_reg)
1128 {
1129 return p_reg->SHORTS;
1130 }
1131
nrf_spim_int_enable(NRF_SPIM_Type * p_reg,uint32_t mask)1132 NRF_STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_reg,
1133 uint32_t mask)
1134 {
1135 p_reg->INTENSET = mask;
1136 }
1137
nrf_spim_int_disable(NRF_SPIM_Type * p_reg,uint32_t mask)1138 NRF_STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_reg,
1139 uint32_t mask)
1140 {
1141 p_reg->INTENCLR = mask;
1142 }
1143
nrf_spim_int_enable_check(NRF_SPIM_Type const * p_reg,uint32_t mask)1144 NRF_STATIC_INLINE uint32_t nrf_spim_int_enable_check(NRF_SPIM_Type const * p_reg, uint32_t mask)
1145 {
1146 return p_reg->INTENSET & mask;
1147 }
1148
1149 #if NRF_SPIM_HAS_PRESCALER
nrf_spim_prescaler_set(NRF_SPIM_Type * p_reg,uint32_t prescaler)1150 NRF_STATIC_INLINE void nrf_spim_prescaler_set(NRF_SPIM_Type * p_reg,
1151 uint32_t prescaler)
1152 {
1153 NRFX_ASSERT(prescaler >= NRF_SPIM_PRESCALER_MIN_GET(p_reg));
1154 NRFX_ASSERT(prescaler <= NRF_SPIM_PRESCALER_MAX_GET(p_reg));
1155 NRFX_ASSERT(NRFX_IS_EVEN(prescaler));
1156 p_reg->PRESCALER = prescaler;
1157 }
1158
nrf_spim_prescaler_get(NRF_SPIM_Type const * p_reg)1159 NRF_STATIC_INLINE uint32_t nrf_spim_prescaler_get(NRF_SPIM_Type const * p_reg)
1160 {
1161 return p_reg->PRESCALER;
1162 }
1163 #endif
1164
1165 #if defined(DPPI_PRESENT)
nrf_spim_subscribe_set(NRF_SPIM_Type * p_reg,nrf_spim_task_t task,uint8_t channel)1166 NRF_STATIC_INLINE void nrf_spim_subscribe_set(NRF_SPIM_Type * p_reg,
1167 nrf_spim_task_t task,
1168 uint8_t channel)
1169 {
1170 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
1171 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
1172 }
1173
nrf_spim_subscribe_clear(NRF_SPIM_Type * p_reg,nrf_spim_task_t task)1174 NRF_STATIC_INLINE void nrf_spim_subscribe_clear(NRF_SPIM_Type * p_reg,
1175 nrf_spim_task_t task)
1176 {
1177 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
1178 }
1179
nrf_spim_publish_set(NRF_SPIM_Type * p_reg,nrf_spim_event_t event,uint8_t channel)1180 NRF_STATIC_INLINE void nrf_spim_publish_set(NRF_SPIM_Type * p_reg,
1181 nrf_spim_event_t event,
1182 uint8_t channel)
1183 {
1184 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
1185 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
1186 }
1187
nrf_spim_publish_clear(NRF_SPIM_Type * p_reg,nrf_spim_event_t event)1188 NRF_STATIC_INLINE void nrf_spim_publish_clear(NRF_SPIM_Type * p_reg,
1189 nrf_spim_event_t event)
1190 {
1191 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
1192 }
1193 #endif
1194
nrf_spim_enable(NRF_SPIM_Type * p_reg)1195 NRF_STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_reg)
1196 {
1197 p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
1198 }
1199
nrf_spim_disable(NRF_SPIM_Type * p_reg)1200 NRF_STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg)
1201 {
1202 p_reg->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
1203 }
1204
nrf_spim_enable_check(NRF_SPIM_Type const * p_reg)1205 NRF_STATIC_INLINE bool nrf_spim_enable_check(NRF_SPIM_Type const * p_reg)
1206 {
1207 return p_reg->ENABLE == SPIM_ENABLE_ENABLE_Enabled;
1208 }
1209
nrf_spim_pins_set(NRF_SPIM_Type * p_reg,uint32_t sck_pin,uint32_t mosi_pin,uint32_t miso_pin)1210 NRF_STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
1211 uint32_t sck_pin,
1212 uint32_t mosi_pin,
1213 uint32_t miso_pin)
1214 {
1215 p_reg->PSEL.SCK = sck_pin;
1216 p_reg->PSEL.MOSI = mosi_pin;
1217 p_reg->PSEL.MISO = miso_pin;
1218 }
1219
nrf_spim_sck_pin_get(NRF_SPIM_Type const * p_reg)1220 NRF_STATIC_INLINE uint32_t nrf_spim_sck_pin_get(NRF_SPIM_Type const * p_reg)
1221 {
1222 return p_reg->PSEL.SCK;
1223 }
1224
nrf_spim_mosi_pin_get(NRF_SPIM_Type const * p_reg)1225 NRF_STATIC_INLINE uint32_t nrf_spim_mosi_pin_get(NRF_SPIM_Type const * p_reg)
1226 {
1227 return p_reg->PSEL.MOSI;
1228 }
1229
nrf_spim_miso_pin_get(NRF_SPIM_Type const * p_reg)1230 NRF_STATIC_INLINE uint32_t nrf_spim_miso_pin_get(NRF_SPIM_Type const * p_reg)
1231 {
1232 return p_reg->PSEL.MISO;
1233 }
1234
1235 #if NRF_SPIM_HAS_HW_CSN
nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,uint32_t pin,nrf_spim_csn_pol_t polarity,uint32_t duration)1236 NRF_STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
1237 uint32_t pin,
1238 nrf_spim_csn_pol_t polarity,
1239 uint32_t duration)
1240 {
1241 #if defined(SPIM_CSNPOL_CSNPOL0_LOW) && defined(SPIM_PSEL_CSN_MaxCount)
1242 p_reg->PSEL.CSN[0] = pin;
1243 #else
1244 p_reg->PSEL.CSN = pin;
1245 #endif
1246 p_reg->CSNPOL = polarity;
1247 p_reg->IFTIMING.CSNDUR = duration;
1248 }
1249
nrf_spim_csn_pin_get(NRF_SPIM_Type const * p_reg)1250 NRF_STATIC_INLINE uint32_t nrf_spim_csn_pin_get(NRF_SPIM_Type const * p_reg)
1251 {
1252 #if defined(SPIM_CSNPOL_CSNPOL0_LOW) && defined(SPIM_PSEL_CSN_MaxCount)
1253 return p_reg->PSEL.CSN[0];
1254 #else
1255 return p_reg->PSEL.CSN;
1256 #endif
1257 }
1258 #endif // NRF_SPIM_HAS_HW_CSN
1259
1260 #if NRF_SPIM_HAS_DCX
nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,uint32_t dcx_pin)1261 NRF_STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg, uint32_t dcx_pin)
1262 {
1263 #if defined(SPIM_PSEL_DCX_PIN_Msk)
1264 p_reg->PSEL.DCX = dcx_pin;
1265 #else
1266 p_reg->PSELDCX = dcx_pin;
1267 #endif
1268 }
1269
nrf_spim_dcx_pin_get(NRF_SPIM_Type const * p_reg)1270 NRF_STATIC_INLINE uint32_t nrf_spim_dcx_pin_get(NRF_SPIM_Type const * p_reg)
1271 {
1272 #if defined(SPIM_PSEL_DCX_PIN_Msk)
1273 return p_reg->PSEL.DCX;
1274 #else
1275 return p_reg->PSELDCX;
1276 #endif
1277 }
1278
nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg,uint32_t dcx_cnt)1279 NRF_STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg, uint32_t dcx_cnt)
1280 {
1281 p_reg->DCXCNT = dcx_cnt;
1282 }
1283 #endif // NRF_SPIM_HAS_DCX
1284
1285 #if NRF_SPIM_HAS_RXDELAY
nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,uint32_t rxdelay)1286 NRF_STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,
1287 uint32_t rxdelay)
1288 {
1289 p_reg->IFTIMING.RXDELAY = rxdelay;
1290 }
1291 #endif
1292
1293 #if NRF_SPIM_HAS_STALLSTAT
nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg)1294 NRF_STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg)
1295 {
1296 p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_RX_Msk);
1297 }
1298
nrf_spim_stallstat_rx_get(NRF_SPIM_Type const * p_reg)1299 NRF_STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type const * p_reg)
1300 {
1301 return (p_reg->STALLSTAT & SPIM_STALLSTAT_RX_Msk) != 0;
1302 }
1303
nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg)1304 NRF_STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg)
1305 {
1306 p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_TX_Msk);
1307 }
1308
nrf_spim_stallstat_tx_get(NRF_SPIM_Type const * p_reg)1309 NRF_STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type const * p_reg)
1310 {
1311 return (p_reg->STALLSTAT & SPIM_STALLSTAT_TX_Msk) != 0;
1312 }
1313 #endif
1314
1315 #if NRF_SPIM_HAS_FREQUENCY
nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,nrf_spim_frequency_t frequency)1316 NRF_STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
1317 nrf_spim_frequency_t frequency)
1318 {
1319 p_reg->FREQUENCY = (uint32_t)frequency;
1320 }
1321
nrf_spim_frequency_get(NRF_SPIM_Type * p_reg)1322 NRF_STATIC_INLINE nrf_spim_frequency_t nrf_spim_frequency_get(NRF_SPIM_Type * p_reg)
1323 {
1324 return (nrf_spim_frequency_t)(p_reg->FREQUENCY);
1325 }
1326 #endif
1327
nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,uint8_t const * p_buffer,size_t length)1328 NRF_STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
1329 uint8_t const * p_buffer,
1330 size_t length)
1331 {
1332 #if NRF_SPIM_HAS_DMA_REG
1333 p_reg->DMA.TX.PTR = (uint32_t)p_buffer;
1334 p_reg->DMA.TX.MAXCNT = length;
1335 #else
1336 p_reg->TXD.PTR = (uint32_t)p_buffer;
1337 p_reg->TXD.MAXCNT = length;
1338 #endif
1339 }
1340
nrf_spim_tx_amount_get(NRF_SPIM_Type const * p_reg)1341 NRF_STATIC_INLINE uint32_t nrf_spim_tx_amount_get(NRF_SPIM_Type const * p_reg)
1342 {
1343 #if NRF_SPIM_HAS_DMA_REG
1344 return p_reg->DMA.TX.AMOUNT;
1345 #else
1346 return p_reg->TXD.AMOUNT;
1347 #endif
1348 }
1349
nrf_spim_tx_maxcnt_get(NRF_SPIM_Type const * p_reg)1350 NRF_STATIC_INLINE uint32_t nrf_spim_tx_maxcnt_get(NRF_SPIM_Type const * p_reg)
1351 {
1352 #if NRF_SPIM_HAS_DMA_REG
1353 return p_reg->DMA.TX.MAXCNT;
1354 #else
1355 return p_reg->TXD.MAXCNT;
1356 #endif
1357 }
1358
nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,uint8_t * p_buffer,size_t length)1359 NRF_STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
1360 uint8_t * p_buffer,
1361 size_t length)
1362 {
1363 #if NRF_SPIM_HAS_DMA_REG
1364 p_reg->DMA.RX.PTR = (uint32_t)p_buffer;
1365 p_reg->DMA.RX.MAXCNT = length;
1366 #else
1367 p_reg->RXD.PTR = (uint32_t)p_buffer;
1368 p_reg->RXD.MAXCNT = length;
1369 #endif
1370 }
1371
nrf_spim_rx_amount_get(NRF_SPIM_Type const * p_reg)1372 NRF_STATIC_INLINE uint32_t nrf_spim_rx_amount_get(NRF_SPIM_Type const * p_reg)
1373 {
1374 #if NRF_SPIM_HAS_DMA_REG
1375 return p_reg->DMA.RX.AMOUNT;
1376 #else
1377 return p_reg->RXD.AMOUNT;
1378 #endif
1379 }
1380
nrf_spim_rx_maxcnt_get(NRF_SPIM_Type const * p_reg)1381 NRF_STATIC_INLINE uint32_t nrf_spim_rx_maxcnt_get(NRF_SPIM_Type const * p_reg)
1382 {
1383 #if NRF_SPIM_HAS_DMA_REG
1384 return p_reg->DMA.RX.MAXCNT;
1385 #else
1386 return p_reg->RXD.MAXCNT;
1387 #endif
1388 }
1389
nrf_spim_configure(NRF_SPIM_Type * p_reg,nrf_spim_mode_t spi_mode,nrf_spim_bit_order_t spi_bit_order)1390 NRF_STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_reg,
1391 nrf_spim_mode_t spi_mode,
1392 nrf_spim_bit_order_t spi_bit_order)
1393 {
1394 uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ?
1395 SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst);
1396 switch (spi_mode)
1397 {
1398 default:
1399 case NRF_SPIM_MODE_0:
1400 config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
1401 (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
1402 break;
1403
1404 case NRF_SPIM_MODE_1:
1405 config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
1406 (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
1407 break;
1408
1409 case NRF_SPIM_MODE_2:
1410 config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
1411 (SPIM_CONFIG_CPHA_Leading << SPIM_CONFIG_CPHA_Pos);
1412 break;
1413
1414 case NRF_SPIM_MODE_3:
1415 config |= (SPIM_CONFIG_CPOL_ActiveLow << SPIM_CONFIG_CPOL_Pos) |
1416 (SPIM_CONFIG_CPHA_Trailing << SPIM_CONFIG_CPHA_Pos);
1417 break;
1418 }
1419 p_reg->CONFIG = config;
1420 }
1421
nrf_spim_orc_set(NRF_SPIM_Type * p_reg,uint8_t orc)1422 NRF_STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_reg,
1423 uint8_t orc)
1424 {
1425 p_reg->ORC = orc;
1426 }
1427
1428 #if NRF_SPIM_HAS_ARRAY_LIST
nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg)1429 NRF_STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_reg)
1430 {
1431 p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_ArrayList << SPIM_TXD_LIST_LIST_Pos;
1432 }
1433
nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg)1434 NRF_STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_reg)
1435 {
1436 p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_Disabled << SPIM_TXD_LIST_LIST_Pos;
1437 }
1438
nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg)1439 NRF_STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_reg)
1440 {
1441 p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_ArrayList << SPIM_RXD_LIST_LIST_Pos;
1442 }
1443
nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg)1444 NRF_STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_reg)
1445 {
1446 p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_Disabled << SPIM_RXD_LIST_LIST_Pos;
1447 }
1448 #endif
1449
1450 #if NRF_SPIM_HAS_DMA_TASKS_EVENTS
nrf_spim_rx_pattern_match_enable_set(NRF_SPIM_Type * p_reg,uint8_t index,bool enable)1451 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_enable_set(NRF_SPIM_Type * p_reg,
1452 uint8_t index,
1453 bool enable)
1454 {
1455 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1456 switch (index)
1457 {
1458 case 0:
1459 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1460 ~SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk) |
1461 ((enable ?
1462 SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled :
1463 SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Disabled)
1464 << SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos));
1465 break;
1466 case 1:
1467 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1468 ~SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk) |
1469 ((enable ?
1470 SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled :
1471 SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Disabled)
1472 << SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos));
1473 break;
1474 case 2:
1475 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1476 ~SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk) |
1477 ((enable ?
1478 SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled :
1479 SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Disabled)
1480 << SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos));
1481 break;
1482 case 3:
1483 p_reg->DMA.RX.MATCH.CONFIG = ((p_reg->DMA.RX.MATCH.CONFIG &
1484 ~SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk) |
1485 ((enable ?
1486 SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled :
1487 SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Disabled)
1488 << SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos));
1489 break;
1490 default:
1491 NRFX_ASSERT(false);
1492 break;
1493 }
1494 }
1495
nrf_spim_rx_pattern_match_enable_check(NRF_SPIM_Type const * p_reg,uint8_t index)1496 NRF_STATIC_INLINE bool nrf_spim_rx_pattern_match_enable_check(NRF_SPIM_Type const * p_reg,
1497 uint8_t index)
1498 {
1499 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1500 switch (index)
1501 {
1502 case 0:
1503 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Msk)
1504 >> SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Pos) ==
1505 SPIM_DMA_RX_MATCH_CONFIG_ENABLE0_Enabled;
1506 case 1:
1507 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Msk)
1508 >> SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Pos) ==
1509 SPIM_DMA_RX_MATCH_CONFIG_ENABLE1_Enabled;
1510 case 2:
1511 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Msk)
1512 >> SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Pos) ==
1513 SPIM_DMA_RX_MATCH_CONFIG_ENABLE2_Enabled;
1514 case 3:
1515 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Msk)
1516 >> SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Pos) ==
1517 SPIM_DMA_RX_MATCH_CONFIG_ENABLE3_Enabled;
1518 default:
1519 NRFX_ASSERT(false);
1520 return 0;
1521 }
1522 }
1523
nrf_spim_rx_pattern_match_one_shot_enable(NRF_SPIM_Type * p_reg,uint8_t index)1524 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_one_shot_enable(NRF_SPIM_Type * p_reg,
1525 uint8_t index)
1526 {
1527 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1528 switch (index)
1529 {
1530 case 0:
1531 p_reg->DMA.RX.MATCH.CONFIG |= SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk;
1532 break;
1533 case 1:
1534 p_reg->DMA.RX.MATCH.CONFIG |= SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk;
1535 break;
1536 case 2:
1537 p_reg->DMA.RX.MATCH.CONFIG |= SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk;
1538 break;
1539 case 3:
1540 p_reg->DMA.RX.MATCH.CONFIG |= SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk;
1541 break;
1542 default:
1543 NRFX_ASSERT(false);
1544 break;
1545 }
1546 }
1547
nrf_spim_rx_pattern_match_one_shot_disable(NRF_SPIM_Type * p_reg,uint8_t index)1548 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_one_shot_disable(NRF_SPIM_Type * p_reg,
1549 uint8_t index)
1550 {
1551 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1552 switch (index)
1553 {
1554 case 0:
1555 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk);
1556 break;
1557 case 1:
1558 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk);
1559 break;
1560 case 2:
1561 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk);
1562 break;
1563 case 3:
1564 p_reg->DMA.RX.MATCH.CONFIG &= ~(SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk);
1565 break;
1566 default:
1567 NRFX_ASSERT(false);
1568 break;
1569 }
1570 }
1571
nrf_spim_rx_pattern_match_one_shot_check(NRF_SPIM_Type const * p_reg,uint8_t index)1572 NRF_STATIC_INLINE bool nrf_spim_rx_pattern_match_one_shot_check(NRF_SPIM_Type const * p_reg,
1573 uint8_t index)
1574 {
1575 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1576 switch (index)
1577 {
1578 case 0:
1579 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Msk)
1580 >> SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Pos) ==
1581 SPIM_DMA_RX_MATCH_CONFIG_ONESHOT0_Oneshot;
1582 case 1:
1583 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Msk)
1584 >> SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Pos) ==
1585 SPIM_DMA_RX_MATCH_CONFIG_ONESHOT1_Oneshot;
1586 case 2:
1587 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Msk)
1588 >> SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Pos) ==
1589 SPIM_DMA_RX_MATCH_CONFIG_ONESHOT2_Oneshot;
1590 case 3:
1591 return ((p_reg->DMA.RX.MATCH.CONFIG & SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Msk)
1592 >> SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Pos) ==
1593 SPIM_DMA_RX_MATCH_CONFIG_ONESHOT3_Oneshot;
1594 default:
1595 NRFX_ASSERT(false);
1596 return 0;
1597 }
1598 }
1599
nrf_spim_rx_pattern_match_candidate_set(NRF_SPIM_Type * p_reg,uint8_t index,uint32_t pattern)1600 NRF_STATIC_INLINE void nrf_spim_rx_pattern_match_candidate_set(NRF_SPIM_Type * p_reg,
1601 uint8_t index,
1602 uint32_t pattern)
1603 {
1604 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1605 p_reg->DMA.RX.MATCH.CANDIDATE[index] = pattern;
1606 }
1607
nrf_spim_rx_pattern_match_candidate_get(NRF_SPIM_Type const * p_reg,uint8_t index)1608 NRF_STATIC_INLINE uint32_t nrf_spim_rx_pattern_match_candidate_get(NRF_SPIM_Type const * p_reg,
1609 uint8_t index)
1610 {
1611 NRFX_ASSERT(index < NRF_SPIM_DMA_RX_PATTERN_MAX_COUNT);
1612 return p_reg->DMA.RX.MATCH.CANDIDATE[index];
1613 }
1614 #endif // NRF_SPIM_HAS_DMA_TASKS_EVENTS
1615
1616 #if NRF_SPIM_HAS_DMA_REG
nrf_spim_rx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg)1617 NRF_STATIC_INLINE void nrf_spim_rx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg)
1618 {
1619 p_reg->DMA.RX.TERMINATEONBUSERROR |= SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk;
1620 }
1621
nrf_spim_rx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg)1622 NRF_STATIC_INLINE void nrf_spim_rx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg)
1623 {
1624 p_reg->DMA.RX.TERMINATEONBUSERROR &= ~(SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk);
1625 }
1626
nrf_spim_rx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg)1627 NRF_STATIC_INLINE bool nrf_spim_rx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg)
1628 {
1629 return ((p_reg->DMA.RX.TERMINATEONBUSERROR & SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Msk)
1630 >> SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Pos) ==
1631 SPIM_DMA_RX_TERMINATEONBUSERROR_ENABLE_Enabled;
1632 }
1633
nrf_spim_tx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg)1634 NRF_STATIC_INLINE void nrf_spim_tx_terminate_on_bus_error_enable(NRF_SPIM_Type * p_reg)
1635 {
1636 p_reg->DMA.TX.TERMINATEONBUSERROR |= SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk;
1637 }
1638
nrf_spim_tx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg)1639 NRF_STATIC_INLINE void nrf_spim_tx_terminate_on_bus_error_disable(NRF_SPIM_Type * p_reg)
1640 {
1641 p_reg->DMA.TX.TERMINATEONBUSERROR &= ~(SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk);
1642 }
1643
nrf_spim_tx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg)1644 NRF_STATIC_INLINE bool nrf_spim_tx_terminate_on_bus_error_check(NRF_SPIM_Type const * p_reg)
1645 {
1646 return ((p_reg->DMA.TX.TERMINATEONBUSERROR & SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Msk)
1647 >> SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Pos) ==
1648 SPIM_DMA_TX_TERMINATEONBUSERROR_ENABLE_Enabled;
1649 }
1650 #endif // NRF_SPIM_HAS_DMA_REG
1651
1652 #endif // NRF_DECLARE_ONLY
1653
1654 /** @} */
1655
1656 #ifdef __cplusplus
1657 }
1658 #endif
1659
1660 #endif // NRF_SPIM_H__
1661
