1 /*
2 * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_POWER_H__
35 #define NRF_POWER_H__
36
37 #include <nrfx.h>
38 #include <nrf_erratas.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /**
45 * @defgroup nrf_power_hal POWER HAL
46 * @{
47 * @ingroup nrf_power
48 * @brief Hardware access layer for managing the POWER peripheral.
49 */
50
51 #if defined(POWER_INTENSET_SLEEPENTER_Msk) || defined(__NRFX_DOXYGEN__)
52 /** @brief Symbol indicating whether sleep events are present. */
53 #define NRF_POWER_HAS_SLEEPEVT 1
54 #else
55 #define NRF_POWER_HAS_SLEEPEVT 0
56 #endif
57
58 #if defined(POWER_USBREGSTATUS_VBUSDETECT_Msk) || defined(__NRFX_DOXYGEN__)
59 /** @brief Symbol indicating whether the POWER peripheral controls the USB regulator. */
60 #define NRF_POWER_HAS_USBREG 1
61 #else
62 #define NRF_POWER_HAS_USBREG 0
63 #endif
64
65 #if defined(POWER_DCDCEN0_DCDCEN_Msk) || defined(__NRFX_DOXYGEN__)
66 /** @brief Symbol indicating whether DCDCEN for REG0 is present. */
67 #define NRF_POWER_HAS_DCDCEN_VDDH 1
68 #else
69 #define NRF_POWER_HAS_DCDCEN_VDDH 0
70 #endif
71
72 #if defined(POWER_DCDCEN_DCDCEN_Msk) || defined(__NRFX_DOXYGEN__)
73 /** @brief Symbol indicating whether DCDCEN for REG1 is present. */
74 #define NRF_POWER_HAS_DCDCEN 1
75 #else
76 #define NRF_POWER_HAS_DCDCEN 0
77 #endif
78
79 #if defined(POWER_INTENSET_POFWARN_Msk) || defined(__NRFX_DOXYGEN__)
80 /** @brief Symbol indicating whether power failure event is present. */
81 #define NRF_POWER_HAS_POFWARN 1
82 #else
83 #define NRF_POWER_HAS_POFWARN 0
84 #endif
85
86 #if defined(POWER_POFCON_THRESHOLD_Msk) || defined(__NRFX_DOXYGEN__)
87 /** @brief Symbol indicating whether power failure comparator is present. */
88 #define NRF_POWER_HAS_POFCON 1
89 #else
90 #define NRF_POWER_HAS_POFCON 0
91 #endif
92
93 #if defined(POWER_POFCON_THRESHOLDVDDH_Msk) || defined(__NRFX_DOXYGEN__)
94 /** @brief Symbol indicating whether power failure comparator for VDDH is present. */
95 #define NRF_POWER_HAS_POFCON_VDDH 1
96 #else
97 #define NRF_POWER_HAS_POFCON_VDDH 0
98 #endif
99
100 #if defined(POWER_RESETREAS_RESETPIN_Msk) || defined(__NRFX_DOXYGEN__)
101 /** @brief Auxiliary definition to mark the fact that RESETREAS register is present in POWER */
102 #define NRF_POWER_HAS_RESETREAS 1
103 #else
104 #define NRF_POWER_HAS_RESETREAS 0
105 #endif
106
107 #if defined(POWER_MAINREGSTATUS_MAINREGSTATUS_Msk) || defined(__NRFX_DOXYGEN__)
108 /** @brief Symbol indicating whether MAINREGSTATUS register is present. */
109 #define NRF_POWER_HAS_MAINREGSTATUS 1
110 #else
111 #define NRF_POWER_HAS_MAINREGSTATUS 0
112 #endif
113
114 #if (!defined(POWER_GPREGRET2_GPREGRET_Msk) && !defined(NRF51)) || defined(__NRFX_DOXYGEN__)
115 /** @brief Symbol indicating whether GPREGRET register is treated as an array. */
116 #define NRF_POWER_HAS_GPREGRET_ARRAY 1
117 #else
118 #define NRF_POWER_HAS_GPREGRET_ARRAY 0
119 #endif
120
121 /** @brief POWER tasks. */
122 typedef enum
123 {
124 NRF_POWER_TASK_CONSTLAT = offsetof(NRF_POWER_Type, TASKS_CONSTLAT), /**< Enable constant latency mode. */
125 NRF_POWER_TASK_LOWPWR = offsetof(NRF_POWER_Type, TASKS_LOWPWR ), /**< Enable low-power mode (variable latency). */
126 } nrf_power_task_t;
127
128 /** @brief POWER events. */
129 typedef enum
130 {
131 #if NRF_POWER_HAS_POFWARN
132 NRF_POWER_EVENT_POFWARN = offsetof(NRF_POWER_Type, EVENTS_POFWARN ), /**< Power failure warning. */
133 #endif
134 #if NRF_POWER_HAS_SLEEPEVT
135 NRF_POWER_EVENT_SLEEPENTER = offsetof(NRF_POWER_Type, EVENTS_SLEEPENTER ), /**< CPU entered WFI/WFE sleep. */
136 NRF_POWER_EVENT_SLEEPEXIT = offsetof(NRF_POWER_Type, EVENTS_SLEEPEXIT ), /**< CPU exited WFI/WFE sleep. */
137 #endif
138 #if NRF_POWER_HAS_USBREG
139 NRF_POWER_EVENT_USBDETECTED = offsetof(NRF_POWER_Type, EVENTS_USBDETECTED), /**< Voltage supply detected on VBUS. */
140 NRF_POWER_EVENT_USBREMOVED = offsetof(NRF_POWER_Type, EVENTS_USBREMOVED ), /**< Voltage supply removed from VBUS. */
141 NRF_POWER_EVENT_USBPWRRDY = offsetof(NRF_POWER_Type, EVENTS_USBPWRRDY ), /**< USB 3.3 V supply ready. */
142 #endif
143 } nrf_power_event_t;
144
145 /** @brief POWER interrupts. */
146 typedef enum
147 {
148 #if NRF_POWER_HAS_POFWARN
149 NRF_POWER_INT_POFWARN_MASK = POWER_INTENSET_POFWARN_Msk , /**< Write '1' to Enable interrupt for POFWARN event. */
150 #endif
151 #if NRF_POWER_HAS_SLEEPEVT
152 NRF_POWER_INT_SLEEPENTER_MASK = POWER_INTENSET_SLEEPENTER_Msk , /**< Write '1' to Enable interrupt for SLEEPENTER event. */
153 NRF_POWER_INT_SLEEPEXIT_MASK = POWER_INTENSET_SLEEPEXIT_Msk , /**< Write '1' to Enable interrupt for SLEEPEXIT event. */
154 #endif
155 #if NRF_POWER_HAS_USBREG
156 NRF_POWER_INT_USBDETECTED_MASK = POWER_INTENSET_USBDETECTED_Msk, /**< Write '1' to Enable interrupt for USBDETECTED event. */
157 NRF_POWER_INT_USBREMOVED_MASK = POWER_INTENSET_USBREMOVED_Msk , /**< Write '1' to Enable interrupt for USBREMOVED event. */
158 NRF_POWER_INT_USBPWRRDY_MASK = POWER_INTENSET_USBPWRRDY_Msk , /**< Write '1' to Enable interrupt for USBPWRRDY event. */
159 #endif
160 } nrf_power_int_mask_t;
161
162 /** @brief Reset reason. */
163 #if NRF_POWER_HAS_RESETREAS
164 typedef enum
165 {
166 NRF_POWER_RESETREAS_RESETPIN_MASK = POWER_RESETREAS_RESETPIN_Msk, /**< Bit mask of RESETPIN field. */
167 NRF_POWER_RESETREAS_DOG_MASK = POWER_RESETREAS_DOG_Msk , /**< Bit mask of DOG field. */
168 NRF_POWER_RESETREAS_SREQ_MASK = POWER_RESETREAS_SREQ_Msk , /**< Bit mask of SREQ field. */
169 NRF_POWER_RESETREAS_LOCKUP_MASK = POWER_RESETREAS_LOCKUP_Msk , /**< Bit mask of LOCKUP field. */
170 NRF_POWER_RESETREAS_OFF_MASK = POWER_RESETREAS_OFF_Msk , /**< Bit mask of OFF field. */
171 #if defined(POWER_RESETREAS_LPCOMP_Msk) || defined(__NRFX_DOXYGEN__)
172 NRF_POWER_RESETREAS_LPCOMP_MASK = POWER_RESETREAS_LPCOMP_Msk , /**< Bit mask of LPCOMP field. */
173 #endif
174 NRF_POWER_RESETREAS_DIF_MASK = POWER_RESETREAS_DIF_Msk , /**< Bit mask of DIF field. */
175 #if defined(POWER_RESETREAS_NFC_Msk) || defined(__NRFX_DOXYGEN__)
176 NRF_POWER_RESETREAS_NFC_MASK = POWER_RESETREAS_NFC_Msk , /**< Bit mask of NFC field. */
177 #endif
178 #if defined(POWER_RESETREAS_VBUS_Msk) || defined(__NRFX_DOXYGEN__)
179 NRF_POWER_RESETREAS_VBUS_MASK = POWER_RESETREAS_VBUS_Msk , /**< Bit mask of VBUS field. */
180 #endif
181 } nrf_power_resetreas_mask_t;
182 #endif // NRF_POWER_HAS_RESETREAS
183
184 #if NRF_POWER_HAS_USBREG
185 /**
186 * @brief USBREGSTATUS register bit masks
187 *
188 * @sa nrf_power_usbregstatus_get
189 */
190 typedef enum
191 {
192 NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK = POWER_USBREGSTATUS_VBUSDETECT_Msk, /**< USB detected or removed. */
193 NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK = POWER_USBREGSTATUS_OUTPUTRDY_Msk /**< USB 3.3 V supply ready. */
194 } nrf_power_usbregstatus_mask_t;
195 #endif // NRF_POWER_HAS_USBREG
196
197 #if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
198 /**
199 * @brief Numbers of RAM blocks
200 *
201 * @sa nrf_power_ramblock_mask_t
202 * @note
203 * RAM blocks must be used in nRF51.
204 * In newer SoCs, RAM is divided into segments and this functionality is not supported.
205 * See the PS for mapping between the internal RAM and RAM blocks, because this
206 * mapping is not 1:1, and functions related to old style blocks must not be used.
207 */
208 typedef enum
209 {
210 NRF_POWER_RAMBLOCK0 = POWER_RAMSTATUS_RAMBLOCK0_Pos,
211 NRF_POWER_RAMBLOCK1 = POWER_RAMSTATUS_RAMBLOCK1_Pos,
212 #if defined(POWER_RAMSTATUS_RAMBLOCK2_Pos) || defined(__NRFX_DOXYGEN__)
213 NRF_POWER_RAMBLOCK2 = POWER_RAMSTATUS_RAMBLOCK2_Pos,
214 #endif
215 #if defined(POWER_RAMSTATUS_RAMBLOCK3_Pos) || defined(__NRFX_DOXYGEN__)
216 NRF_POWER_RAMBLOCK3 = POWER_RAMSTATUS_RAMBLOCK3_Pos
217 #endif
218 } nrf_power_ramblock_t;
219
220 /**
221 * @brief Masks of RAM blocks.
222 *
223 * @sa nrf_power_ramblock_t
224 */
225 typedef enum
226 {
227 NRF_POWER_RAMBLOCK0_MASK = POWER_RAMSTATUS_RAMBLOCK0_Msk,
228 NRF_POWER_RAMBLOCK1_MASK = POWER_RAMSTATUS_RAMBLOCK1_Msk,
229 #if defined(POWER_RAMSTATUS_RAMBLOCK2_Msk) || defined(__NRFX_DOXYGEN__)
230 NRF_POWER_RAMBLOCK2_MASK = POWER_RAMSTATUS_RAMBLOCK2_Msk,
231 #endif
232 #if defined(POWER_RAMSTATUS_RAMBLOCK3_Msk) || defined(__NRFX_DOXYGEN__)
233 NRF_POWER_RAMBLOCK3_MASK = POWER_RAMSTATUS_RAMBLOCK3_Msk
234 #endif
235 } nrf_power_ramblock_mask_t;
236 #endif // defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
237
238 /**
239 * @brief RAM power state position of the bits
240 *
241 * @sa nrf_power_onoffram_mask_t
242 */
243 typedef enum
244 {
245 NRF_POWER_ONRAM0, /**< Keep RAM block 0 ON or OFF in System ON mode. */
246 NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched OFF. */
247 NRF_POWER_ONRAM1, /**< Keep RAM block 1 ON or OFF in System ON mode. */
248 NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched OFF. */
249 NRF_POWER_ONRAM2, /**< Keep RAM block 2 ON or OFF in System ON mode. */
250 NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched OFF. */
251 NRF_POWER_ONRAM3, /**< Keep RAM block 3 ON or OFF in System ON mode. */
252 NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched OFF. */
253 }nrf_power_onoffram_t;
254
255 /**
256 * @brief RAM power state bit masks
257 *
258 * @sa nrf_power_onoffram_t
259 */
260 typedef enum
261 {
262 NRF_POWER_ONRAM0_MASK = 1U << NRF_POWER_ONRAM0, /**< Keep RAM block 0 ON or OFF in System ON mode. */
263 NRF_POWER_OFFRAM0_MASK = 1U << NRF_POWER_OFFRAM0, /**< Keep retention on RAM block 0 when RAM block is switched OFF. */
264 NRF_POWER_ONRAM1_MASK = 1U << NRF_POWER_ONRAM1, /**< Keep RAM block 1 ON or OFF in System ON mode. */
265 NRF_POWER_OFFRAM1_MASK = 1U << NRF_POWER_OFFRAM1, /**< Keep retention on RAM block 1 when RAM block is switched OFF. */
266 NRF_POWER_ONRAM2_MASK = 1U << NRF_POWER_ONRAM2, /**< Keep RAM block 2 ON or OFF in System ON mode. */
267 NRF_POWER_OFFRAM2_MASK = 1U << NRF_POWER_OFFRAM2, /**< Keep retention on RAM block 2 when RAM block is switched OFF. */
268 NRF_POWER_ONRAM3_MASK = 1U << NRF_POWER_ONRAM3, /**< Keep RAM block 3 ON or OFF in System ON mode. */
269 NRF_POWER_OFFRAM3_MASK = 1U << NRF_POWER_OFFRAM3, /**< Keep retention on RAM block 3 when RAM block is switched OFF. */
270 }nrf_power_onoffram_mask_t;
271
272 #if NRF_POWER_HAS_POFCON
273 /** @brief Power failure comparator thresholds. */
274 typedef enum
275 {
276 NRF_POWER_POFTHR_V21 = POWER_POFCON_THRESHOLD_V21, /**< Set threshold to 2.1 V. */
277 NRF_POWER_POFTHR_V23 = POWER_POFCON_THRESHOLD_V23, /**< Set threshold to 2.3 V. */
278 NRF_POWER_POFTHR_V25 = POWER_POFCON_THRESHOLD_V25, /**< Set threshold to 2.5 V. */
279 NRF_POWER_POFTHR_V27 = POWER_POFCON_THRESHOLD_V27, /**< Set threshold to 2.7 V. */
280 #if defined(POWER_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__)
281 NRF_POWER_POFTHR_V17 = POWER_POFCON_THRESHOLD_V17, /**< Set threshold to 1.7 V. */
282 NRF_POWER_POFTHR_V18 = POWER_POFCON_THRESHOLD_V18, /**< Set threshold to 1.8 V. */
283 NRF_POWER_POFTHR_V19 = POWER_POFCON_THRESHOLD_V19, /**< Set threshold to 1.9 V. */
284 NRF_POWER_POFTHR_V20 = POWER_POFCON_THRESHOLD_V20, /**< Set threshold to 2.0 V. */
285 NRF_POWER_POFTHR_V22 = POWER_POFCON_THRESHOLD_V22, /**< Set threshold to 2.2 V. */
286 NRF_POWER_POFTHR_V24 = POWER_POFCON_THRESHOLD_V24, /**< Set threshold to 2.4 V. */
287 NRF_POWER_POFTHR_V26 = POWER_POFCON_THRESHOLD_V26, /**< Set threshold to 2.6 V. */
288 NRF_POWER_POFTHR_V28 = POWER_POFCON_THRESHOLD_V28, /**< Set threshold to 2.8 V. */
289 #endif // defined(POWER_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__)
290 } nrf_power_pof_thr_t;
291 #endif // NRF_POWER_HAS_POFCON
292
293 #if NRF_POWER_HAS_POFCON_VDDH
294 /** @brief Power failure comparator thresholds for VDDH. */
295 typedef enum
296 {
297 NRF_POWER_POFTHRVDDH_V27 = POWER_POFCON_THRESHOLDVDDH_V27, /**< Set threshold to 2.7 V. */
298 NRF_POWER_POFTHRVDDH_V28 = POWER_POFCON_THRESHOLDVDDH_V28, /**< Set threshold to 2.8 V. */
299 NRF_POWER_POFTHRVDDH_V29 = POWER_POFCON_THRESHOLDVDDH_V29, /**< Set threshold to 2.9 V. */
300 NRF_POWER_POFTHRVDDH_V30 = POWER_POFCON_THRESHOLDVDDH_V30, /**< Set threshold to 3.0 V. */
301 NRF_POWER_POFTHRVDDH_V31 = POWER_POFCON_THRESHOLDVDDH_V31, /**< Set threshold to 3.1 V. */
302 NRF_POWER_POFTHRVDDH_V32 = POWER_POFCON_THRESHOLDVDDH_V32, /**< Set threshold to 3.2 V. */
303 NRF_POWER_POFTHRVDDH_V33 = POWER_POFCON_THRESHOLDVDDH_V33, /**< Set threshold to 3.3 V. */
304 NRF_POWER_POFTHRVDDH_V34 = POWER_POFCON_THRESHOLDVDDH_V34, /**< Set threshold to 3.4 V. */
305 NRF_POWER_POFTHRVDDH_V35 = POWER_POFCON_THRESHOLDVDDH_V35, /**< Set threshold to 3.5 V. */
306 NRF_POWER_POFTHRVDDH_V36 = POWER_POFCON_THRESHOLDVDDH_V36, /**< Set threshold to 3.6 V. */
307 NRF_POWER_POFTHRVDDH_V37 = POWER_POFCON_THRESHOLDVDDH_V37, /**< Set threshold to 3.7 V. */
308 NRF_POWER_POFTHRVDDH_V38 = POWER_POFCON_THRESHOLDVDDH_V38, /**< Set threshold to 3.8 V. */
309 NRF_POWER_POFTHRVDDH_V39 = POWER_POFCON_THRESHOLDVDDH_V39, /**< Set threshold to 3.9 V. */
310 NRF_POWER_POFTHRVDDH_V40 = POWER_POFCON_THRESHOLDVDDH_V40, /**< Set threshold to 4.0 V. */
311 NRF_POWER_POFTHRVDDH_V41 = POWER_POFCON_THRESHOLDVDDH_V41, /**< Set threshold to 4.1 V. */
312 NRF_POWER_POFTHRVDDH_V42 = POWER_POFCON_THRESHOLDVDDH_V42, /**< Set threshold to 4.2 V. */
313 } nrf_power_pof_thrvddh_t;
314 #endif // NRF_POWER_HAS_POFCON_VDDH
315
316 #if NRF_POWER_HAS_MAINREGSTATUS
317 /** @brief Main regulator status. */
318 typedef enum
319 {
320 NRF_POWER_MAINREGSTATUS_NORMAL = POWER_MAINREGSTATUS_MAINREGSTATUS_Normal, /**< Normal voltage mode. Voltage supplied on VDD. */
321 NRF_POWER_MAINREGSTATUS_HIGH = POWER_MAINREGSTATUS_MAINREGSTATUS_High /**< High voltage mode. Voltage supplied on VDDH. */
322 } nrf_power_mainregstatus_t;
323 #endif
324
325 #if defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__)
326 /**
327 * @brief Bit positions for RAMPOWER register
328 *
329 * All possible bits described, even if they are not used in selected MCU.
330 */
331 typedef enum
332 {
333 /** Keep RAM section S0 ON in System ON mode */
334 NRF_POWER_RAMPOWER_S0POWER = POWER_RAM_POWER_S0POWER_Pos,
335 NRF_POWER_RAMPOWER_S1POWER, /**< Keep RAM section S1 ON in System ON mode. */
336 NRF_POWER_RAMPOWER_S2POWER, /**< Keep RAM section S2 ON in System ON mode. */
337 NRF_POWER_RAMPOWER_S3POWER, /**< Keep RAM section S3 ON in System ON mode. */
338 NRF_POWER_RAMPOWER_S4POWER, /**< Keep RAM section S4 ON in System ON mode. */
339 NRF_POWER_RAMPOWER_S5POWER, /**< Keep RAM section S5 ON in System ON mode. */
340 NRF_POWER_RAMPOWER_S6POWER, /**< Keep RAM section S6 ON in System ON mode. */
341 NRF_POWER_RAMPOWER_S7POWER, /**< Keep RAM section S7 ON in System ON mode. */
342 NRF_POWER_RAMPOWER_S8POWER, /**< Keep RAM section S8 ON in System ON mode. */
343 NRF_POWER_RAMPOWER_S9POWER, /**< Keep RAM section S9 ON in System ON mode. */
344 NRF_POWER_RAMPOWER_S10POWER, /**< Keep RAM section S10 ON in System ON mode. */
345 NRF_POWER_RAMPOWER_S11POWER, /**< Keep RAM section S11 ON in System ON mode. */
346 NRF_POWER_RAMPOWER_S12POWER, /**< Keep RAM section S12 ON in System ON mode. */
347 NRF_POWER_RAMPOWER_S13POWER, /**< Keep RAM section S13 ON in System ON mode. */
348 NRF_POWER_RAMPOWER_S14POWER, /**< Keep RAM section S14 ON in System ON mode. */
349 NRF_POWER_RAMPOWER_S15POWER, /**< Keep RAM section S15 ON in System ON mode. */
350
351 /** Keep section retention in OFF mode when section is OFF */
352 NRF_POWER_RAMPOWER_S0RETENTION = POWER_RAM_POWER_S0RETENTION_Pos,
353 NRF_POWER_RAMPOWER_S1RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
354 NRF_POWER_RAMPOWER_S2RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
355 NRF_POWER_RAMPOWER_S3RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
356 NRF_POWER_RAMPOWER_S4RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
357 NRF_POWER_RAMPOWER_S5RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
358 NRF_POWER_RAMPOWER_S6RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
359 NRF_POWER_RAMPOWER_S7RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
360 NRF_POWER_RAMPOWER_S8RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
361 NRF_POWER_RAMPOWER_S9RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
362 NRF_POWER_RAMPOWER_S10RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
363 NRF_POWER_RAMPOWER_S11RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
364 NRF_POWER_RAMPOWER_S12RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
365 NRF_POWER_RAMPOWER_S13RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
366 NRF_POWER_RAMPOWER_S14RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
367 NRF_POWER_RAMPOWER_S15RETENTION, /**< Keep section retention in OFF mode when section is OFF. */
368 } nrf_power_rampower_t;
369
370 /**
371 * @brief Bit masks for RAMPOWER register
372 *
373 * All possible bits described, even if they are not used in selected MCU.
374 */
375 typedef enum
376 {
377 NRF_POWER_RAMPOWER_S0POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S0POWER ,
378 NRF_POWER_RAMPOWER_S1POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S1POWER ,
379 NRF_POWER_RAMPOWER_S2POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S2POWER ,
380 NRF_POWER_RAMPOWER_S3POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S3POWER ,
381 NRF_POWER_RAMPOWER_S4POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S4POWER ,
382 NRF_POWER_RAMPOWER_S5POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S5POWER ,
383 NRF_POWER_RAMPOWER_S7POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S7POWER ,
384 NRF_POWER_RAMPOWER_S8POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S8POWER ,
385 NRF_POWER_RAMPOWER_S9POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S9POWER ,
386 NRF_POWER_RAMPOWER_S10POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S10POWER,
387 NRF_POWER_RAMPOWER_S11POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S11POWER,
388 NRF_POWER_RAMPOWER_S12POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S12POWER,
389 NRF_POWER_RAMPOWER_S13POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S13POWER,
390 NRF_POWER_RAMPOWER_S14POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S14POWER,
391 NRF_POWER_RAMPOWER_S15POWER_MASK = 1UL << NRF_POWER_RAMPOWER_S15POWER,
392
393 NRF_POWER_RAMPOWER_S0RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S0RETENTION ,
394 NRF_POWER_RAMPOWER_S1RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S1RETENTION ,
395 NRF_POWER_RAMPOWER_S2RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S2RETENTION ,
396 NRF_POWER_RAMPOWER_S3RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S3RETENTION ,
397 NRF_POWER_RAMPOWER_S4RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S4RETENTION ,
398 NRF_POWER_RAMPOWER_S5RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S5RETENTION ,
399 NRF_POWER_RAMPOWER_S7RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S7RETENTION ,
400 NRF_POWER_RAMPOWER_S8RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S8RETENTION ,
401 NRF_POWER_RAMPOWER_S9RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S9RETENTION ,
402 NRF_POWER_RAMPOWER_S10RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S10RETENTION,
403 NRF_POWER_RAMPOWER_S11RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S11RETENTION,
404 NRF_POWER_RAMPOWER_S12RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S12RETENTION,
405 NRF_POWER_RAMPOWER_S13RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S13RETENTION,
406 NRF_POWER_RAMPOWER_S14RETENTION_MASK = 1UL << NRF_POWER_RAMPOWER_S14RETENTION,
407 NRF_POWER_RAMPOWER_S15RETENTION_MASK = (int)(1UL << NRF_POWER_RAMPOWER_S15RETENTION),
408 } nrf_power_rampower_mask_t;
409 #endif // defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__)
410
411 /**
412 * @brief Function for activating a specific POWER task.
413 *
414 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
415 * @param[in] task Task.
416 */
417 NRF_STATIC_INLINE void nrf_power_task_trigger(NRF_POWER_Type * p_reg, nrf_power_task_t task);
418
419 /**
420 * @brief Function for returning the address of a specific POWER task register.
421 *
422 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
423 * @param[in] task Task.
424 *
425 * @return Task address.
426 */
427 NRF_STATIC_INLINE uint32_t nrf_power_task_address_get(NRF_POWER_Type const * p_reg,
428 nrf_power_task_t task);
429
430 /**
431 * @brief Function for clearing a specific event.
432 *
433 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
434 * @param[in] event Event.
435 */
436 NRF_STATIC_INLINE void nrf_power_event_clear(NRF_POWER_Type * p_reg, nrf_power_event_t event);
437
438 /**
439 * @brief Function for retrieving the state of the POWER event.
440 *
441 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
442 * @param[in] event Event to be checked.
443 *
444 * @retval true The event has been generated.
445 * @retval false The event has not been generated.
446 */
447 NRF_STATIC_INLINE bool nrf_power_event_check(NRF_POWER_Type const * p_reg, nrf_power_event_t event);
448
449 /**
450 * @brief Function for getting and clearing the state of specific event
451 *
452 * This function checks the state of the event and clears it.
453 *
454 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
455 * @param[in] event Event.
456 *
457 * @retval true The event was set.
458 * @retval false The event was not set.
459 */
460 NRF_STATIC_INLINE bool nrf_power_event_get_and_clear(NRF_POWER_Type * p_reg,
461 nrf_power_event_t event);
462
463 /**
464 * @brief Function for returning the address of a specific POWER event register.
465 *
466 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
467 * @param[in] event Event.
468 *
469 * @return Address.
470 */
471 NRF_STATIC_INLINE uint32_t nrf_power_event_address_get(NRF_POWER_Type const * p_reg,
472 nrf_power_event_t event);
473
474 /**
475 * @brief Function for enabling selected interrupts.
476 *
477 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
478 * @param[in] mask Mask of interrupts to be enabled.
479 */
480 NRF_STATIC_INLINE void nrf_power_int_enable(NRF_POWER_Type * p_reg, uint32_t mask);
481
482 /**
483 * @brief Function for checking if the specified interrupts are enabled.
484 *
485 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
486 * @param[in] mask Mask of interrupts to be checked.
487 *
488 * @return Mask of enabled interrupts.
489 */
490 NRF_STATIC_INLINE uint32_t nrf_power_int_enable_check(NRF_POWER_Type const * p_reg, uint32_t mask);
491
492 /**
493 * @brief Function for retrieving the information about enabled interrupts.
494 *
495 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
496 *
497 * @return The flags of enabled interrupts.
498 */
499 NRF_STATIC_INLINE uint32_t nrf_power_int_enable_get(NRF_POWER_Type const * p_reg);
500
501 /**
502 * @brief Function for disabling selected interrupts.
503 *
504 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
505 * @param[in] mask Mask of interrupts to be disabled.
506 */
507 NRF_STATIC_INLINE void nrf_power_int_disable(NRF_POWER_Type * p_reg, uint32_t mask);
508
509 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
510 /**
511 * @brief Function for setting the subscribe configuration for a given
512 * POWER task.
513 *
514 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
515 * @param[in] task Task for which to set the configuration.
516 * @param[in] channel Channel through which to subscribe events.
517 */
518 NRF_STATIC_INLINE void nrf_power_subscribe_set(NRF_POWER_Type * p_reg,
519 nrf_power_task_t task,
520 uint8_t channel);
521
522 /**
523 * @brief Function for clearing the subscribe configuration for a given
524 * POWER task.
525 *
526 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
527 * @param[in] task Task for which to clear the configuration.
528 */
529 NRF_STATIC_INLINE void nrf_power_subscribe_clear(NRF_POWER_Type * p_reg, nrf_power_task_t task);
530
531 /**
532 * @brief Function for setting the publish configuration for a given
533 * POWER event.
534 *
535 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
536 * @param[in] event Event for which to set the configuration.
537 * @param[in] channel Channel through which to publish the event.
538 */
539 NRF_STATIC_INLINE void nrf_power_publish_set(NRF_POWER_Type * p_reg,
540 nrf_power_event_t event,
541 uint8_t channel);
542
543 /**
544 * @brief Function for clearing the publish configuration for a given
545 * POWER event.
546 *
547 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
548 * @param[in] event Event for which to clear the configuration.
549 */
550 NRF_STATIC_INLINE void nrf_power_publish_clear(NRF_POWER_Type * p_reg, nrf_power_event_t event);
551 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
552
553 #if NRF_POWER_HAS_RESETREAS
554 /**
555 * @brief Function for getting the reset reason bitmask.
556 *
557 * This function returns the reset reason bitmask.
558 * Unless cleared, the RESETREAS register is cumulative.
559 * A field is cleared by writing '1' to it (see @ref nrf_power_resetreas_clear).
560 * If none of the reset sources is flagged,
561 * the chip was reset from the on-chip reset generator,
562 * which indicates a power-on-reset or a brown out reset.
563 *
564 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
565 *
566 * @return The mask of reset reasons constructed with @ref nrf_power_resetreas_mask_t.
567 */
568 NRF_STATIC_INLINE uint32_t nrf_power_resetreas_get(NRF_POWER_Type const * p_reg);
569
570 /**
571 * @brief Function for clearing the selected reset reason field.
572 *
573 * This function clears the selected reset reason field.
574 *
575 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
576 * @param[in] mask The mask constructed from @ref nrf_power_resetreas_mask_t enumerator values.
577 *
578 * @sa nrf_power_resetreas_get
579 */
580 NRF_STATIC_INLINE void nrf_power_resetreas_clear(NRF_POWER_Type * p_reg, uint32_t mask);
581 #endif // NRF_POWER_HAS_RESETREAS
582
583 #if defined(POWER_POWERSTATUS_LTEMODEM_Msk) || defined(__NRFX_DOXYGEN__)
584 /**
585 * @brief Function for getting power status of the LTE Modem domain.
586 *
587 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
588 *
589 * @retval true The LTE Modem domain is powered on.
590 * @retval false The LTE Modem domain is powered off.
591 */
592 NRF_STATIC_INLINE bool nrf_power_powerstatus_get(NRF_POWER_Type const * p_reg);
593 #endif
594
595 #if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
596 /**
597 * @brief Function for getting the RAMSTATUS register.
598 *
599 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
600 *
601 * @return Value with bits set according to the masks in @ref nrf_power_ramblock_mask_t.
602 */
603 NRF_STATIC_INLINE uint32_t nrf_power_ramstatus_get(NRF_POWER_Type const * p_reg);
604 #endif // defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
605
606 #if defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
607 /**
608 * @brief Function for going into System OFF mode.
609 *
610 * This function puts the CPU in System OFF mode.
611 * The only way to wake up the CPU is by reset.
612 *
613 * @note This function never returns.
614 *
615 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
616 */
617 NRF_STATIC_INLINE void nrf_power_system_off(NRF_POWER_Type * p_reg);
618 #endif // defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
619
620 #if NRF_POWER_HAS_POFCON
621 /**
622 * @brief Function for setting the power failure comparator configuration.
623 *
624 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
625 * @param[in] enable True if the power failure comparator is to be enabled, false otherwise.
626 * @param[in] thr voltage threshold value.
627 */
628 NRF_STATIC_INLINE void nrf_power_pofcon_set(NRF_POWER_Type * p_reg,
629 bool enable,
630 nrf_power_pof_thr_t thr);
631
632 /**
633 * @brief Function for getting the power failure comparator configuration.
634 *
635 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
636 * @param[out] p_enabled Function sets this boolean variable to true
637 * if power failure comparator is enabled.
638 * The pointer can be NULL if we do not need this information.
639 *
640 * @return Threshold setting for power failure comparator.
641 */
642 NRF_STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(NRF_POWER_Type const * p_reg,
643 bool * p_enabled);
644 #endif // NRF_POWER_HAS_POFCON
645
646 #if NRF_POWER_HAS_POFCON_VDDH
647 /**
648 * @brief Function for setting the VDDH power failure comparator threshold.
649 *
650 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
651 * @param[in] thr Threshold to be set.
652 */
653 NRF_STATIC_INLINE void nrf_power_pofcon_vddh_set(NRF_POWER_Type * p_reg,
654 nrf_power_pof_thrvddh_t thr);
655
656 /**
657 * @brief Function for getting the VDDH power failure comparator threshold.
658 *
659 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
660 *
661 * @return VDDH threshold currently configured.
662 */
663 NRF_STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(NRF_POWER_Type const * p_reg);
664 #endif // NRF_POWER_HAS_POFCON_VDDH
665
666 /**
667 * @brief Function for setting the general purpose retention register.
668 *
669 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
670 * @param[in] val Value to be set in the register.
671 */
672 NRF_STATIC_INLINE void nrf_power_gpregret_set(NRF_POWER_Type * p_reg, uint8_t val);
673
674 /**
675 * @brief Function for getting general purpose retention register.
676 *
677 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
678 *
679 * @return The value from the register.
680 */
681 NRF_STATIC_INLINE uint8_t nrf_power_gpregret_get(NRF_POWER_Type const * p_reg);
682
683 #if defined(POWER_GPREGRET2_GPREGRET_Msk) || defined(__NRFX_DOXYGEN__)
684 /**
685 * @brief Function for setting the general purpose retention register 2.
686 *
687 * @note This register is not available in the nRF51 MCU family.
688 *
689 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
690 * @param[in] val Value to be set in the register.
691 */
692 NRF_STATIC_INLINE void nrf_power_gpregret2_set(NRF_POWER_Type * p_reg, uint8_t val);
693
694 /**
695 * @brief Function for getting the general purpose retention register 2.
696 *
697 * @note This register is not available in all MCUs.
698 *
699 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
700 *
701 * @return The value from the register.
702 */
703 NRF_STATIC_INLINE uint8_t nrf_power_gpregret2_get(NRF_POWER_Type const * p_reg);
704 #endif // defined(POWER_GPREGRET2_GPREGRET_Msk) || defined(__NRFX_DOXYGEN__)
705
706 /**
707 * @brief Function for getting value of the particular general purpose retention register
708 *
709 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
710 * @param[in] reg_num General purpose retention register number.
711 *
712 * @return The value from the register
713 */
714 NRF_STATIC_INLINE uint8_t nrf_power_gpregret_ext_get(NRF_POWER_Type const * p_reg, uint8_t reg_num);
715
716 /**
717 * @brief Function for setting particular general purpose retention register.
718 *
719 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
720 * @param[in] reg_num General purpose retention register number.
721 * @param[in] val Value to be set in the register
722 */
723 NRF_STATIC_INLINE void nrf_power_gpregret_ext_set(NRF_POWER_Type * p_reg,
724 uint8_t reg_num,
725 uint8_t val);
726
727 #if NRF_POWER_HAS_DCDCEN
728 /**
729 * @brief Enable or disable DCDC converter
730 *
731 * @note If the device consist of high voltage power input (VDDH), this setting
732 * will relate to the converter on low voltage side (1.3 V output).
733 *
734 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
735 * @param[in] enable True if DCDC converter is to be enabled, false otherwise.
736 */
737 NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable);
738
739 /**
740 * @brief Function for getting the state of the DCDC converter.
741 *
742 * @note If the device consist of high voltage power input (VDDH), this setting
743 * will relate to the converter on low voltage side (1.3 V output).
744 *
745 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
746 *
747 * @retval true Converter is enabled.
748 * @retval false Converter is disabled.
749 */
750 NRF_STATIC_INLINE bool nrf_power_dcdcen_get(NRF_POWER_Type const * p_reg);
751 #endif // NRF_POWER_HAS_DCDCEN
752
753 #if defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__)
754 /**
755 * @brief Turn ON sections in the selected RAM block.
756 *
757 * This function turns ON several sections in one block and also block retention.
758 *
759 * @sa nrf_power_rampower_mask_t
760 * @sa nrf_power_rampower_mask_off
761 *
762 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
763 * @param[in] block RAM block index.
764 * @param[in] section_mask Mask of the sections created by merging
765 * @ref nrf_power_rampower_mask_t flags.
766 */
767 NRF_STATIC_INLINE void nrf_power_rampower_mask_on(NRF_POWER_Type * p_reg,
768 uint8_t block,
769 uint32_t section_mask);
770
771 /**
772 * @brief Turn ON sections in the selected RAM block.
773 *
774 * This function turns OFF several sections in one block and also block retention.
775 *
776 * @sa nrf_power_rampower_mask_t
777 * @sa nrf_power_rampower_mask_off
778 *
779 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
780 * @param[in] block RAM block index.
781 * @param[in] section_mask Mask of the sections created by merging
782 * @ref nrf_power_rampower_mask_t flags.
783 */
784 NRF_STATIC_INLINE void nrf_power_rampower_mask_off(NRF_POWER_Type * p_reg,
785 uint8_t block,
786 uint32_t section_mask);
787
788 /**
789 * @brief Function for getting the ON mask and retention sections in the selected RAM block.
790 *
791 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
792 * @param[in] block RAM block index.
793 *
794 * @return Mask of sections state composed from @ref nrf_power_rampower_mask_t flags.
795 */
796 NRF_STATIC_INLINE uint32_t nrf_power_rampower_mask_get(NRF_POWER_Type const * p_reg, uint8_t block);
797 #endif /* defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__) */
798
799 #if NRF_POWER_HAS_DCDCEN_VDDH
800 /**
801 * @brief Function for enabling or disabling the DCDC converter on VDDH.
802 *
803 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
804 * @param[in] enable True if DCDC converter on VDDH is to be enabled, false otherwise.
805 */
806 NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable);
807
808 /**
809 * @brief Function for getting the state of DCDC converter on VDDH.
810 *
811 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
812 *
813 * @retval true Converter is enabled.
814 * @retval false Converter is disabled.
815 */
816 NRF_STATIC_INLINE bool nrf_power_dcdcen_vddh_get(NRF_POWER_Type const * p_reg);
817 #endif // NRF_POWER_HAS_DCDCEN_VDDH
818
819 #if NRF_POWER_HAS_MAINREGSTATUS
820 /**
821 * @brief Function for getting the main supply status.
822 *
823 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
824 *
825 * @return The current main supply status.
826 */
827 NRF_STATIC_INLINE
828 nrf_power_mainregstatus_t nrf_power_mainregstatus_get(NRF_POWER_Type const * p_reg);
829 #endif // NRF_POWER_HAS_MAINREGSTATUS
830
831 #if NRF_POWER_HAS_USBREG
832 /**
833 * @brief Function for getting the whole USBREGSTATUS register.
834 *
835 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
836 *
837 * @return The USBREGSTATUS register value.
838 * Use @ref nrf_power_usbregstatus_mask_t values for bit masking.
839 *
840 * @sa nrf_power_usbregstatus_vbusdet_get
841 * @sa nrf_power_usbregstatus_outrdy_get
842 */
843 NRF_STATIC_INLINE uint32_t nrf_power_usbregstatus_get(NRF_POWER_Type const * p_reg);
844
845 /**
846 * @brief Function for getting the VBUS input detection status.
847 *
848 * USBDETECTED and USBREMOVED events are derived from this information
849 *
850 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
851 *
852 * @retval false VBUS voltage below valid threshold.
853 * @retval true VBUS voltage above valid threshold.
854 *
855 * @sa nrf_power_usbregstatus_get
856 */
857 NRF_STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(NRF_POWER_Type const * p_reg);
858
859 /**
860 * @brief Function for getting the state of the elapsed time for the USB supply output settling.
861 *
862 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
863 *
864 * @retval false USBREG output settling time not elapsed.
865 * @retval true USBREG output settling time elapsed
866 * (same information as USBPWRRDY event).
867 *
868 * @sa nrf_power_usbregstatus_get
869 */
870 NRF_STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(NRF_POWER_Type const * p_reg);
871 #endif // NRF_POWER_HAS_USBREG
872
873 #ifndef NRF_DECLARE_ONLY
874
nrf_power_task_trigger(NRF_POWER_Type * p_reg,nrf_power_task_t task)875 NRF_STATIC_INLINE void nrf_power_task_trigger(NRF_POWER_Type * p_reg, nrf_power_task_t task)
876 {
877 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
878 }
879
nrf_power_task_address_get(NRF_POWER_Type const * p_reg,nrf_power_task_t task)880 NRF_STATIC_INLINE uint32_t nrf_power_task_address_get(NRF_POWER_Type const * p_reg,
881 nrf_power_task_t task)
882 {
883 return ((uint32_t)p_reg + (uint32_t)task);
884 }
885
nrf_power_event_clear(NRF_POWER_Type * p_reg,nrf_power_event_t event)886 NRF_STATIC_INLINE void nrf_power_event_clear(NRF_POWER_Type * p_reg, nrf_power_event_t event)
887 {
888 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
889 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
890 }
891
nrf_power_event_check(NRF_POWER_Type const * p_reg,nrf_power_event_t event)892 NRF_STATIC_INLINE bool nrf_power_event_check(NRF_POWER_Type const * p_reg, nrf_power_event_t event)
893 {
894 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
895 }
896
nrf_power_event_get_and_clear(NRF_POWER_Type * p_reg,nrf_power_event_t event)897 NRF_STATIC_INLINE bool nrf_power_event_get_and_clear(NRF_POWER_Type * p_reg,
898 nrf_power_event_t event)
899 {
900 bool ret = nrf_power_event_check(p_reg, event);
901 if (ret)
902 {
903 nrf_power_event_clear(p_reg, event);
904 }
905 return ret;
906 }
907
nrf_power_event_address_get(NRF_POWER_Type const * p_reg,nrf_power_event_t event)908 NRF_STATIC_INLINE uint32_t nrf_power_event_address_get(NRF_POWER_Type const * p_reg,
909 nrf_power_event_t event)
910 {
911 return ((uint32_t)p_reg + (uint32_t)event);
912 }
913
nrf_power_int_enable(NRF_POWER_Type * p_reg,uint32_t mask)914 NRF_STATIC_INLINE void nrf_power_int_enable(NRF_POWER_Type * p_reg, uint32_t mask)
915 {
916 p_reg->INTENSET = mask;
917 }
918
nrf_power_int_enable_check(NRF_POWER_Type const * p_reg,uint32_t mask)919 NRF_STATIC_INLINE uint32_t nrf_power_int_enable_check(NRF_POWER_Type const * p_reg, uint32_t mask)
920 {
921 return p_reg->INTENSET & mask;
922 }
923
nrf_power_int_enable_get(NRF_POWER_Type const * p_reg)924 NRF_STATIC_INLINE uint32_t nrf_power_int_enable_get(NRF_POWER_Type const * p_reg)
925 {
926 return p_reg->INTENSET;
927 }
928
nrf_power_int_disable(NRF_POWER_Type * p_reg,uint32_t mask)929 NRF_STATIC_INLINE void nrf_power_int_disable(NRF_POWER_Type * p_reg, uint32_t mask)
930 {
931 p_reg->INTENCLR = mask;
932 }
933
934 #if defined(DPPI_PRESENT)
nrf_power_subscribe_set(NRF_POWER_Type * p_reg,nrf_power_task_t task,uint8_t channel)935 NRF_STATIC_INLINE void nrf_power_subscribe_set(NRF_POWER_Type * p_reg,
936 nrf_power_task_t task,
937 uint8_t channel)
938 {
939 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
940 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
941 }
942
nrf_power_subscribe_clear(NRF_POWER_Type * p_reg,nrf_power_task_t task)943 NRF_STATIC_INLINE void nrf_power_subscribe_clear(NRF_POWER_Type * p_reg, nrf_power_task_t task)
944 {
945 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
946 }
947
nrf_power_publish_set(NRF_POWER_Type * p_reg,nrf_power_event_t event,uint8_t channel)948 NRF_STATIC_INLINE void nrf_power_publish_set(NRF_POWER_Type * p_reg,
949 nrf_power_event_t event,
950 uint8_t channel)
951 {
952 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
953 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
954 }
955
nrf_power_publish_clear(NRF_POWER_Type * p_reg,nrf_power_event_t event)956 NRF_STATIC_INLINE void nrf_power_publish_clear(NRF_POWER_Type * p_reg, nrf_power_event_t event)
957 {
958 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
959 }
960 #endif // defined(DPPI_PRESENT)
961
962 #if NRF_POWER_HAS_RESETREAS
nrf_power_resetreas_get(NRF_POWER_Type const * p_reg)963 NRF_STATIC_INLINE uint32_t nrf_power_resetreas_get(NRF_POWER_Type const * p_reg)
964 {
965 return p_reg->RESETREAS;
966 }
967
nrf_power_resetreas_clear(NRF_POWER_Type * p_reg,uint32_t mask)968 NRF_STATIC_INLINE void nrf_power_resetreas_clear(NRF_POWER_Type * p_reg, uint32_t mask)
969 {
970 p_reg->RESETREAS = mask;
971 }
972 #endif // NRF_POWER_HAS_RESETREAS
973
974 #if defined(POWER_POWERSTATUS_LTEMODEM_Msk)
nrf_power_powerstatus_get(NRF_POWER_Type const * p_reg)975 NRF_STATIC_INLINE bool nrf_power_powerstatus_get(NRF_POWER_Type const * p_reg)
976 {
977 return (p_reg->POWERSTATUS & POWER_POWERSTATUS_LTEMODEM_Msk) ==
978 (POWER_POWERSTATUS_LTEMODEM_ON << POWER_POWERSTATUS_LTEMODEM_Pos);
979 }
980 #endif // (POWER_POWERSTATUS_LTEMODEM_Msk)
981
982 #if defined(POWER_RAMSTATUS_RAMBLOCK0_Msk)
nrf_power_ramstatus_get(NRF_POWER_Type const * p_reg)983 NRF_STATIC_INLINE uint32_t nrf_power_ramstatus_get(NRF_POWER_Type const * p_reg)
984 {
985 return p_reg->RAMSTATUS;
986 }
987 #endif // defined(POWER_RAMSTATUS_RAMBLOCK0_Msk)
988
989 #if defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
nrf_power_system_off(NRF_POWER_Type * p_reg)990 NRF_STATIC_INLINE void nrf_power_system_off(NRF_POWER_Type * p_reg)
991 {
992 p_reg->SYSTEMOFF = POWER_SYSTEMOFF_SYSTEMOFF_Enter;
993 __DSB();
994
995 /* Solution for simulated System OFF in debug mode */
996 while (true)
997 {
998 __WFE();
999 }
1000 }
1001 #endif // defined(POWER_SYSTEMOFF_SYSTEMOFF_Enter)
1002
1003 #if NRF_POWER_HAS_POFCON
nrf_power_pofcon_set(NRF_POWER_Type * p_reg,bool enable,nrf_power_pof_thr_t thr)1004 NRF_STATIC_INLINE void nrf_power_pofcon_set(NRF_POWER_Type * p_reg,
1005 bool enable,
1006 nrf_power_pof_thr_t thr)
1007 {
1008 NRFX_ASSERT(thr == (thr & (POWER_POFCON_THRESHOLD_Msk >> POWER_POFCON_THRESHOLD_Pos)));
1009 #if NRF_POWER_HAS_POFCON_VDDH
1010 uint32_t pofcon = p_reg->POFCON;
1011 pofcon &= ~(POWER_POFCON_THRESHOLD_Msk | POWER_POFCON_POF_Msk);
1012 pofcon |=
1013 #else // NRF_POWER_HAS_POFCON_VDDH
1014 p_reg->POFCON =
1015 #endif
1016 (((uint32_t)thr) << POWER_POFCON_THRESHOLD_Pos) |
1017 (enable ?
1018 (POWER_POFCON_POF_Enabled << POWER_POFCON_POF_Pos)
1019 :
1020 (POWER_POFCON_POF_Disabled << POWER_POFCON_POF_Pos));
1021 #if NRF_POWER_HAS_POFCON_VDDH
1022 p_reg->POFCON = pofcon;
1023 #endif
1024 }
1025
nrf_power_pofcon_get(NRF_POWER_Type const * p_reg,bool * p_enabled)1026 NRF_STATIC_INLINE nrf_power_pof_thr_t nrf_power_pofcon_get(NRF_POWER_Type const * p_reg,
1027 bool * p_enabled)
1028 {
1029 uint32_t pofcon = p_reg->POFCON;
1030 if (NULL != p_enabled)
1031 {
1032 (*p_enabled) = ((pofcon & POWER_POFCON_POF_Msk) >> POWER_POFCON_POF_Pos)
1033 == POWER_POFCON_POF_Enabled;
1034 }
1035 return (nrf_power_pof_thr_t)((pofcon & POWER_POFCON_THRESHOLD_Msk) >>
1036 POWER_POFCON_THRESHOLD_Pos);
1037 }
1038 #endif // NRF_POWER_HAS_POFCON
1039
1040 #if NRF_POWER_HAS_POFCON_VDDH
nrf_power_pofcon_vddh_set(NRF_POWER_Type * p_reg,nrf_power_pof_thrvddh_t thr)1041 NRF_STATIC_INLINE void nrf_power_pofcon_vddh_set(NRF_POWER_Type * p_reg,
1042 nrf_power_pof_thrvddh_t thr)
1043 {
1044 NRFX_ASSERT(thr == (thr & (POWER_POFCON_THRESHOLDVDDH_Msk >> POWER_POFCON_THRESHOLDVDDH_Pos)));
1045 uint32_t pofcon = p_reg->POFCON;
1046 pofcon &= ~POWER_POFCON_THRESHOLDVDDH_Msk;
1047 pofcon |= (((uint32_t)thr) << POWER_POFCON_THRESHOLDVDDH_Pos);
1048 p_reg->POFCON = pofcon;
1049 }
1050
nrf_power_pofcon_vddh_get(NRF_POWER_Type const * p_reg)1051 NRF_STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(NRF_POWER_Type const * p_reg)
1052 {
1053 return (nrf_power_pof_thrvddh_t)((p_reg->POFCON & POWER_POFCON_THRESHOLDVDDH_Msk) >>
1054 POWER_POFCON_THRESHOLDVDDH_Pos);
1055 }
1056 #endif // NRF_POWER_HAS_POFCON_VDDH
1057
nrf_power_gpregret_set(NRF_POWER_Type * p_reg,uint8_t val)1058 NRF_STATIC_INLINE void nrf_power_gpregret_set(NRF_POWER_Type * p_reg, uint8_t val)
1059 {
1060 volatile uint32_t * p_gpregret;
1061 if (sizeof(p_reg->GPREGRET) > sizeof(uint32_t))
1062 {
1063 p_gpregret = &((volatile uint32_t *)p_reg->GPREGRET)[0];
1064 }
1065 else
1066 {
1067 p_gpregret = &((volatile uint32_t *)&p_reg->GPREGRET)[0];
1068 }
1069 *p_gpregret = val;
1070 }
1071
nrf_power_gpregret_get(NRF_POWER_Type const * p_reg)1072 NRF_STATIC_INLINE uint8_t nrf_power_gpregret_get(NRF_POWER_Type const * p_reg)
1073 {
1074 volatile uint32_t * p_gpregret;
1075 if (sizeof(p_reg->GPREGRET) > sizeof(uint32_t))
1076 {
1077 p_gpregret = &((volatile uint32_t *)p_reg->GPREGRET)[0];
1078 }
1079 else
1080 {
1081 p_gpregret = &((volatile uint32_t *)&p_reg->GPREGRET)[0];
1082 }
1083 return (uint8_t)*p_gpregret;
1084 }
1085
nrf_power_gpregret_ext_set(NRF_POWER_Type * p_reg,uint8_t reg_num,uint8_t val)1086 NRF_STATIC_INLINE void nrf_power_gpregret_ext_set(NRF_POWER_Type * p_reg,
1087 uint8_t reg_num,
1088 uint8_t val)
1089 {
1090 #if NRF_POWER_HAS_GPREGRET_ARRAY
1091 p_reg->GPREGRET[reg_num] = val;
1092 #else
1093 NRFX_ASSERT(reg_num < 1);
1094 p_reg->GPREGRET = val;
1095 #endif
1096 }
1097
nrf_power_gpregret_ext_get(NRF_POWER_Type const * p_reg,uint8_t reg_num)1098 NRF_STATIC_INLINE uint8_t nrf_power_gpregret_ext_get(NRF_POWER_Type const * p_reg, uint8_t reg_num)
1099 {
1100 #if NRF_POWER_HAS_GPREGRET_ARRAY
1101 return p_reg->GPREGRET[reg_num];
1102 #else
1103 NRFX_ASSERT(reg_num < 1);
1104 return (uint8_t)p_reg->GPREGRET;
1105 #endif
1106 }
1107
1108 #if defined(POWER_GPREGRET2_GPREGRET_Msk)
nrf_power_gpregret2_set(NRF_POWER_Type * p_reg,uint8_t val)1109 NRF_STATIC_INLINE void nrf_power_gpregret2_set(NRF_POWER_Type * p_reg, uint8_t val)
1110 {
1111 p_reg->GPREGRET2 = val;
1112 }
1113
nrf_power_gpregret2_get(NRF_POWER_Type const * p_reg)1114 NRF_STATIC_INLINE uint8_t nrf_power_gpregret2_get(NRF_POWER_Type const * p_reg)
1115 {
1116 return (uint8_t)p_reg->GPREGRET2;
1117 }
1118 #endif
1119
1120 #if NRF_POWER_HAS_DCDCEN
nrf_power_dcdcen_set(NRF_POWER_Type * p_reg,bool enable)1121 NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable)
1122 {
1123 p_reg->DCDCEN = (enable ? POWER_DCDCEN_DCDCEN_Enabled : POWER_DCDCEN_DCDCEN_Disabled) <<
1124 POWER_DCDCEN_DCDCEN_Pos;
1125 }
1126
nrf_power_dcdcen_get(NRF_POWER_Type const * p_reg)1127 NRF_STATIC_INLINE bool nrf_power_dcdcen_get(NRF_POWER_Type const * p_reg)
1128 {
1129 return (p_reg->DCDCEN & POWER_DCDCEN_DCDCEN_Msk)
1130 ==
1131 (POWER_DCDCEN_DCDCEN_Enabled << POWER_DCDCEN_DCDCEN_Pos);
1132 }
1133 #endif // NRF_POWER_HAS_DCDCEN
1134
1135 #if defined(POWER_RAM_POWER_S0POWER_Msk)
nrf_power_rampower_mask_on(NRF_POWER_Type * p_reg,uint8_t block,uint32_t section_mask)1136 NRF_STATIC_INLINE void nrf_power_rampower_mask_on(NRF_POWER_Type * p_reg,
1137 uint8_t block,
1138 uint32_t section_mask)
1139 {
1140 p_reg->RAM[block].POWERSET = section_mask;
1141 }
1142
nrf_power_rampower_mask_off(NRF_POWER_Type * p_reg,uint8_t block,uint32_t section_mask)1143 NRF_STATIC_INLINE void nrf_power_rampower_mask_off(NRF_POWER_Type * p_reg,
1144 uint8_t block,
1145 uint32_t section_mask)
1146 {
1147 p_reg->RAM[block].POWERCLR = section_mask;
1148 }
1149
nrf_power_rampower_mask_get(NRF_POWER_Type const * p_reg,uint8_t block)1150 NRF_STATIC_INLINE uint32_t nrf_power_rampower_mask_get(NRF_POWER_Type const * p_reg, uint8_t block)
1151 {
1152 return p_reg->RAM[block].POWER;
1153 }
1154 #endif // defined(POWER_RAM_POWER_S0POWER_Msk)
1155
1156 #if NRF_POWER_HAS_DCDCEN_VDDH
nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg,bool enable)1157 NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable)
1158 {
1159 if (enable && nrf52_errata_197())
1160 {
1161 // Workaround for anomaly 197 "POWER: DCDC of REG0 not functional".
1162 *(volatile uint32_t *)0x40000638ul = 1ul;
1163 }
1164 p_reg->DCDCEN0 = (enable ? POWER_DCDCEN0_DCDCEN_Enabled : POWER_DCDCEN0_DCDCEN_Disabled) <<
1165 POWER_DCDCEN0_DCDCEN_Pos;
1166 }
1167
nrf_power_dcdcen_vddh_get(NRF_POWER_Type const * p_reg)1168 NRF_STATIC_INLINE bool nrf_power_dcdcen_vddh_get(NRF_POWER_Type const * p_reg)
1169 {
1170 return (p_reg->DCDCEN0 & POWER_DCDCEN0_DCDCEN_Msk)
1171 ==
1172 (POWER_DCDCEN0_DCDCEN_Enabled << POWER_DCDCEN0_DCDCEN_Pos);
1173 }
1174 #endif // NRF_POWER_HAS_DCDCEN_VDDH
1175
1176 #if NRF_POWER_HAS_MAINREGSTATUS
1177 NRF_STATIC_INLINE
nrf_power_mainregstatus_get(NRF_POWER_Type const * p_reg)1178 nrf_power_mainregstatus_t nrf_power_mainregstatus_get(NRF_POWER_Type const * p_reg)
1179 {
1180 return (nrf_power_mainregstatus_t)(((p_reg->MAINREGSTATUS) &
1181 POWER_MAINREGSTATUS_MAINREGSTATUS_Msk) >>
1182 POWER_MAINREGSTATUS_MAINREGSTATUS_Pos);
1183 }
1184 #endif // NRF_POWER_HAS_MAINREGSTATUS
1185
1186 #if NRF_POWER_HAS_USBREG
nrf_power_usbregstatus_get(NRF_POWER_Type const * p_reg)1187 NRF_STATIC_INLINE uint32_t nrf_power_usbregstatus_get(NRF_POWER_Type const * p_reg)
1188 {
1189 return p_reg->USBREGSTATUS;
1190 }
1191
nrf_power_usbregstatus_vbusdet_get(NRF_POWER_Type const * p_reg)1192 NRF_STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(NRF_POWER_Type const * p_reg)
1193 {
1194 return (nrf_power_usbregstatus_get(p_reg) & NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK) != 0;
1195 }
1196
nrf_power_usbregstatus_outrdy_get(NRF_POWER_Type const * p_reg)1197 NRF_STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(NRF_POWER_Type const * p_reg)
1198 {
1199 return (nrf_power_usbregstatus_get(p_reg) & NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK) != 0;
1200 }
1201 #endif // NRF_POWER_HAS_USBREG
1202
1203 #endif // NRF_DECLARE_ONLY
1204
1205 /** @} */
1206
1207 #ifdef __cplusplus
1208 }
1209 #endif
1210
1211 #endif // NRF_POWER_H__
1212
